arch/x86/dts/minnowmax.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/x86-gpio.h>
  10 #include <dt-bindings/interrupt-router/intel-irq.h>
  11
  12 /include/ "skeleton.dtsi"
  13 /include/ "serial.dtsi"
  14 /include/ "rtc.dtsi"
  15
  16 / {
  17         model = "Intel Minnowboard Max";
  18         compatible = "intel,minnowmax", "intel,baytrail";
  19
  20         aliases {
  21                 serial0 = &serial;
  22                 spi0 = "/spi";
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         pch_pinctrl {
  30                 compatible = "intel,x86-pinctrl";
  31                 io-base = <0x4c>;
  32
  33                 /* GPIO E0 */
  34                 soc_gpio_s5_0@0 {
  35                         gpio-offset = <0x80 0>;
  36                         pad-offset = <0x1d0>;
  37                         mode-gpio;
  38                         output-value = <0>;
  39                         direction = <PIN_OUTPUT>;
  40                 };
  41
  42                 /* GPIO E1 */
  43                 soc_gpio_s5_1@0 {
  44                         gpio-offset = <0x80 1>;
  45                         pad-offset = <0x210>;
  46                         mode-gpio;
  47                         output-value = <0>;
  48                         direction = <PIN_OUTPUT>;
  49                 };
  50
  51                 /* GPIO E2 */
  52                 soc_gpio_s5_2@0 {
  53                         gpio-offset = <0x80 2>;
  54                         pad-offset = <0x1e0>;
  55                         mode-gpio;
  56                         output-value = <0>;
  57                         direction = <PIN_OUTPUT>;
  58                 };
  59
  60                 pin_usb_host_en0@0 {
  61                         gpio-offset = <0x80 8>;
  62                         pad-offset = <0x260>;
  63                         mode-gpio;
  64                         output-value = <1>;
  65                         direction = <PIN_OUTPUT>;
  66                 };
  67
  68                 pin_usb_host_en1@0 {
  69                         gpio-offset = <0x80 9>;
  70                         pad-offset = <0x258>;
  71                         mode-gpio;
  72                         output-value = <1>;
  73                         direction = <PIN_OUTPUT>;
  74                 };
  75         };
  76
  77         gpioa {
  78                 compatible = "intel,ich6-gpio";
  79                 u-boot,dm-pre-reloc;
  80                 reg = <0 0x20>;
  81                 bank-name = "A";
  82         };
  83
  84         gpiob {
  85                 compatible = "intel,ich6-gpio";
  86                 u-boot,dm-pre-reloc;
  87                 reg = <0x20 0x20>;
  88                 bank-name = "B";
  89         };
  90
  91         gpioc {
  92                 compatible = "intel,ich6-gpio";
  93                 u-boot,dm-pre-reloc;
  94                 reg = <0x40 0x20>;
  95                 bank-name = "C";
  96         };
  97
  98         gpiod {
  99                 compatible = "intel,ich6-gpio";
 100                 u-boot,dm-pre-reloc;
 101                 reg = <0x60 0x20>;
 102                 bank-name = "D";
 103         };
 104
 105         gpioe {
 106                 compatible = "intel,ich6-gpio";
 107                 u-boot,dm-pre-reloc;
 108                 reg = <0x80 0x20>;
 109                 bank-name = "E";
 110         };
 111
 112         gpiof {
 113                 compatible = "intel,ich6-gpio";
 114                 u-boot,dm-pre-reloc;
 115                 reg = <0xA0 0x20>;
 116                 bank-name = "F";
 117         };
 118
 119         chosen {
 120                 stdout-path = "/serial";
 121         };
 122
 123         cpus {
 124                 #address-cells = <1>;
 125                 #size-cells = <0>;
 126
 127                 cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "intel,baytrail-cpu";
 130                         reg = <0>;
 131                         intel,apic-id = <0>;
 132                 };
 133
 134                 cpu@1 {
 135                         device_type = "cpu";
 136                         compatible = "intel,baytrail-cpu";
 137                         reg = <1>;
 138                         intel,apic-id = <4>;
 139                 };
 140
 141         };
 142
 143         pci {
 144                 compatible = "intel,pci-baytrail", "pci-x86";
 145                 #address-cells = <3>;
 146                 #size-cells = <2>;
 147                 u-boot,dm-pre-reloc;
 148                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 149                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 150                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 151
 152                 irq-router@1f,0 {
 153                         reg = <0x0000f800 0 0 0 0>;
 154                         compatible = "intel,irq-router";
 155                         intel,pirq-config = "ibase";
 156                         intel,ibase-offset = <0x50>;
 157                         intel,pirq-link = <8 8>;
 158                         intel,pirq-mask = <0xdee0>;
 159                         intel,pirq-routing = <
 160                                 /* BayTrail PCI devices */
 161                                 PCI_BDF(0, 2, 0) INTA PIRQA
 162                                 PCI_BDF(0, 3, 0) INTA PIRQA
 163                                 PCI_BDF(0, 16, 0) INTA PIRQA
 164                                 PCI_BDF(0, 17, 0) INTA PIRQA
 165                                 PCI_BDF(0, 18, 0) INTA PIRQA
 166                                 PCI_BDF(0, 19, 0) INTA PIRQA
 167                                 PCI_BDF(0, 20, 0) INTA PIRQA
 168                                 PCI_BDF(0, 21, 0) INTA PIRQA
 169                                 PCI_BDF(0, 22, 0) INTA PIRQA
 170                                 PCI_BDF(0, 23, 0) INTA PIRQA
 171                                 PCI_BDF(0, 24, 0) INTA PIRQA
 172                                 PCI_BDF(0, 24, 1) INTC PIRQC
 173                                 PCI_BDF(0, 24, 2) INTD PIRQD
 174                                 PCI_BDF(0, 24, 3) INTB PIRQB
 175                                 PCI_BDF(0, 24, 4) INTA PIRQA
 176                                 PCI_BDF(0, 24, 5) INTC PIRQC
 177                                 PCI_BDF(0, 24, 6) INTD PIRQD
 178                                 PCI_BDF(0, 24, 7) INTB PIRQB
 179                                 PCI_BDF(0, 26, 0) INTA PIRQA
 180                                 PCI_BDF(0, 27, 0) INTA PIRQA
 181                                 PCI_BDF(0, 28, 0) INTA PIRQA
 182                                 PCI_BDF(0, 28, 1) INTB PIRQB
 183                                 PCI_BDF(0, 28, 2) INTC PIRQC
 184                                 PCI_BDF(0, 28, 3) INTD PIRQD
 185                                 PCI_BDF(0, 29, 0) INTA PIRQA
 186                                 PCI_BDF(0, 30, 0) INTA PIRQA
 187                                 PCI_BDF(0, 30, 1) INTD PIRQD
 188                                 PCI_BDF(0, 30, 2) INTB PIRQB
 189                                 PCI_BDF(0, 30, 3) INTC PIRQC
 190                                 PCI_BDF(0, 30, 4) INTD PIRQD
 191                                 PCI_BDF(0, 30, 5) INTB PIRQB
 192                                 PCI_BDF(0, 31, 3) INTB PIRQB
 193
 194                                 /* PCIe root ports downstream interrupts */
 195                                 PCI_BDF(1, 0, 0) INTA PIRQA
 196                                 PCI_BDF(1, 0, 0) INTB PIRQB
 197                                 PCI_BDF(1, 0, 0) INTC PIRQC
 198                                 PCI_BDF(1, 0, 0) INTD PIRQD
 199                                 PCI_BDF(2, 0, 0) INTA PIRQB
 200                                 PCI_BDF(2, 0, 0) INTB PIRQC
 201                                 PCI_BDF(2, 0, 0) INTC PIRQD
 202                                 PCI_BDF(2, 0, 0) INTD PIRQA
 203                                 PCI_BDF(3, 0, 0) INTA PIRQC
 204                                 PCI_BDF(3, 0, 0) INTB PIRQD
 205                                 PCI_BDF(3, 0, 0) INTC PIRQA
 206                                 PCI_BDF(3, 0, 0) INTD PIRQB
 207                                 PCI_BDF(4, 0, 0) INTA PIRQD
 208                                 PCI_BDF(4, 0, 0) INTB PIRQA
 209                                 PCI_BDF(4, 0, 0) INTC PIRQB
 210                                 PCI_BDF(4, 0, 0) INTD PIRQC
 211                         >;
 212                 };
 213         };
 214
 215         fsp {
 216                 compatible = "intel,baytrail-fsp";
 217                 fsp,mrc-init-tseg-size = <0>;
 218                 fsp,mrc-init-mmio-size = <0x800>;
 219                 fsp,mrc-init-spd-addr1 = <0xa0>;
 220                 fsp,mrc-init-spd-addr2 = <0xa2>;
 221                 fsp,emmc-boot-mode = <2>;
 222                 fsp,enable-sdio;
 223                 fsp,enable-sdcard;
 224                 fsp,enable-hsuart1;
 225                 fsp,enable-spi;
 226                 fsp,enable-sata;
 227                 fsp,sata-mode = <1>;
 228                 fsp,enable-lpe;
 229                 fsp,lpss-sio-enable-pci-mode;
 230                 fsp,enable-dma0;
 231                 fsp,enable-dma1;
 232                 fsp,enable-i2c0;
 233                 fsp,enable-i2c1;
 234                 fsp,enable-i2c2;
 235                 fsp,enable-i2c3;
 236                 fsp,enable-i2c4;
 237                 fsp,enable-i2c5;
 238                 fsp,enable-i2c6;
 239                 fsp,enable-pwm0;
 240                 fsp,enable-pwm1;
 241                 fsp,igd-dvmt50-pre-alloc = <2>;
 242                 fsp,aperture-size = <2>;
 243                 fsp,gtt-size = <2>;
 244                 fsp,serial-debug-port-address = <0x3f8>;
 245                 fsp,serial-debug-port-type = <1>;
 246                 fsp,scc-enable-pci-mode;
 247                 fsp,os-selection = <4>;
 248                 fsp,emmc45-ddr50-enabled;
 249                 fsp,emmc45-retune-timer-value = <8>;
 250                 fsp,enable-igd;
 251                 fsp,enable-memory-down;
 252                 fsp,memory-down-params {
 253                         compatible = "intel,baytrail-fsp-mdp";
 254                         fsp,dram-speed = <1>;
 255                         fsp,dram-type = <1>;
 256                         fsp,dimm-0-enable;
 257                         fsp,dimm-width = <1>;
 258                         fsp,dimm-density = <2>;
 259                         fsp,dimm-bus-width = <3>;
 260                         fsp,dimm-sides = <0>;
 261                         fsp,dimm-tcl = <0xb>;
 262                         fsp,dimm-trpt-rcd = <0xb>;
 263                         fsp,dimm-twr = <0xc>;
 264                         fsp,dimm-twtr = <6>;
 265                         fsp,dimm-trrd = <6>;
 266                         fsp,dimm-trtp = <6>;
 267                         fsp,dimm-tfaw = <0x14>;
 268                 };
 269         };
 270
 271         spi {
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274                 compatible = "intel,ich-spi";
 275                 spi-flash@0 {
 276                         reg = <0>;
 277                         compatible = "stmicro,n25q064a", "spi-flash";
 278                         memory-map = <0xff800000 0x00800000>;
 279                 };
 280         };
 281
 282         microcode {
 283                 update@0 {
 284 #include "microcode/m0130673322.dtsi"
 285                 };
 286                 update@1 {
 287 #include "microcode/m0130679901.dtsi"
 288                 };
 289         };
 290
 291 };