board/Marvell/db64360/sdram_init.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * adaption for the Marvell DB64360 Board
  26  * Ingo Assmus (ingo.assmus@keymile.com)
  27  ************************************************************************/
  28
  29
  30 /* sdram_init.c - automatic memory sizing */
  31
  32 #include <common.h>
  33 #include <74xx_7xx.h>
  34 #include "../include/memory.h"
  35 #include "../include/pci.h"
  36 #include "../include/mv_gen_reg.h"
  37 #include <net.h>
  38
  39 #include "eth.h"
  40 #include "mpsc.h"
  41 #include "../common/i2c.h"
  42 #include "64360.h"
  43 #include "mv_regs.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 #define MAP_PCI
  48
  49 int set_dfcdlInit (void);       /* setup delay line of Mv64360 */
  50 int mvDmaIsChannelActive (int);
  51 int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
  52 int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
  53
  54 /* ------------------------------------------------------------------------- */
  55
  56 int
  57 memory_map_bank (unsigned int bankNo,
  58                  unsigned int bankBase, unsigned int bankLength)
  59 {
  60 #ifdef MAP_PCI
  61         PCI_HOST host;
  62 #endif
  63
  64
  65 #ifdef DEBUG
  66         if (bankLength > 0) {
  67                 printf ("mapping bank %d at %08x - %08x\n",
  68                         bankNo, bankBase, bankBase + bankLength - 1);
  69         } else {
  70                 printf ("unmapping bank %d\n", bankNo);
  71         }
  72 #endif
  73
  74         memoryMapBank (bankNo, bankBase, bankLength);
  75
  76 #ifdef MAP_PCI
  77         for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
  78                 const int features =
  79                         PREFETCH_ENABLE |
  80                         DELAYED_READ_ENABLE |
  81                         AGGRESSIVE_PREFETCH |
  82                         READ_LINE_AGGRESSIVE_PREFETCH |
  83                         READ_MULTI_AGGRESSIVE_PREFETCH |
  84                         MAX_BURST_4 | PCI_NO_SWAP;
  85
  86                 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
  87
  88                 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
  89                                        bankLength);
  90
  91                 pciSetRegionFeatures (host, bankNo, features, bankBase,
  92                                       bankLength);
  93         }
  94 #endif
  95         return 0;
  96 }
  97
  98 #define GB         (1 << 30)
  99
 100 /* much of this code is based on (or is) the code in the pip405 port */
 101 /* thanks go to the authors of said port - Josh */
 102
 103 /* structure to store the relevant information about an sdram bank */
 104 typedef struct sdram_info {
 105         uchar drb_size;
 106         uchar registered, ecc;
 107         uchar tpar;
 108         uchar tras_clocks;
 109         uchar burst_len;
 110         uchar banks, slot;
 111 } sdram_info_t;
 112
 113 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
 114
 115 typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
 116
 117 typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
 118         SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
 119 } VOLTAGE_INTERFACE;
 120
 121 typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
 122                 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
 123                 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
 124 typedef enum _max_CL_supported_SD { SD_CL_1 =
 125                 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
 126                 SD_FAULT } MAX_CL_SUPPORTED_SD;
 127
 128
 129 /* SDRAM/DDR information struct */
 130 typedef struct _gtMemoryDimmInfo {
 131         MEMORY_TYPE memoryType;
 132         unsigned int numOfRowAddresses;
 133         unsigned int numOfColAddresses;
 134         unsigned int numOfModuleBanks;
 135         unsigned int dataWidth;
 136         VOLTAGE_INTERFACE voltageInterface;
 137         unsigned int errorCheckType;    /* ECC , PARITY.. */
 138         unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
 139         unsigned int errorCheckDataWidth;       /* 0 - no, 1 - Yes */
 140         unsigned int minClkDelay;
 141         unsigned int burstLengthSupported;
 142         unsigned int numOfBanksOnEachDevice;
 143         unsigned int suportedCasLatencies;
 144         unsigned int RefreshInterval;
 145         unsigned int maxCASlatencySupported_LoP;        /* LoP left of point (measured in ns) */
 146         unsigned int maxCASlatencySupported_RoP;        /* RoP right of point (measured in ns) */
 147         MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
 148         MAX_CL_SUPPORTED_SD maxClSupported_SD;
 149         unsigned int moduleBankDensity;
 150         /* module attributes (true for yes) */
 151         bool bufferedAddrAndControlInputs;
 152         bool registeredAddrAndControlInputs;
 153         bool onCardPLL;
 154         bool bufferedDQMBinputs;
 155         bool registeredDQMBinputs;
 156         bool differentialClockInput;
 157         bool redundantRowAddressing;
 158
 159         /* module general attributes */
 160         bool suportedAutoPreCharge;
 161         bool suportedPreChargeAll;
 162         bool suportedEarlyRasPreCharge;
 163         bool suportedWrite1ReadBurst;
 164         bool suported5PercentLowVCC;
 165         bool suported5PercentUpperVCC;
 166         /* module timing parameters */
 167         unsigned int minRasToCasDelay;
 168         unsigned int minRowActiveRowActiveDelay;
 169         unsigned int minRasPulseWidth;
 170         unsigned int minRowPrechargeTime;       /* measured in ns */
 171
 172         int addrAndCommandHoldTime;     /* LoP left of point (measured in ns) */
 173         int addrAndCommandSetupTime;    /* (measured in ns/100) */
 174         int dataInputSetupTime; /* LoP left of point (measured in ns) */
 175         int dataInputHoldTime;  /* LoP left of point (measured in ns) */
 176 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
 177         unsigned int clockToDataOut_LoP;        /* LoP left of point (measured in ns) */
 178         unsigned int clockToDataOut_RoP;        /* RoP right of point (measured in ns) */
 179         unsigned int clockToDataOutMinus1_LoP;  /* LoP left of point (measured in ns) */
 180         unsigned int clockToDataOutMinus1_RoP;  /* RoP right of point (measured in ns) */
 181         unsigned int clockToDataOutMinus2_LoP;  /* LoP left of point (measured in ns) */
 182         unsigned int clockToDataOutMinus2_RoP;  /* RoP right of point (measured in ns) */
 183
 184         unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;       /* LoP left of point (measured in ns) */
 185         unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;       /* RoP right of point (measured in ns) */
 186
 187         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
 188         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
 189
 190         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
 191         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
 192
 193         /* Parameters calculated from
 194            the extracted DIMM information */
 195         unsigned int size;
 196         unsigned int deviceDensity;     /* 16,64,128,256 or 512 Mbit */
 197         unsigned int numberOfDevices;
 198         uchar drb_size;         /* DRAM size in n*64Mbit */
 199         uchar slot;             /* Slot Number this module is inserted in */
 200         uchar spd_raw_data[128];        /* Content of SPD-EEPROM copied 1:1 */
 201 #ifdef DEBUG
 202         uchar manufactura[8];   /* Content of SPD-EEPROM Byte 64-71 */
 203         uchar modul_id[18];     /* Content of SPD-EEPROM Byte 73-90 */
 204         uchar vendor_data[27];  /* Content of SPD-EEPROM Byte 99-125 */
 205         unsigned long modul_serial_no;  /* Content of SPD-EEPROM Byte 95-98 */
 206         unsigned int manufac_date;      /* Content of SPD-EEPROM Byte 93-94 */
 207         unsigned int modul_revision;    /* Content of SPD-EEPROM Byte 91-92 */
 208         uchar manufac_place;    /* Content of SPD-EEPROM Byte 72 */
 209
 210 #endif
 211 } AUX_MEM_DIMM_INFO;
 212
 213
 214 /*
 215  * translate ns.ns/10 coding of SPD timing values
 216  * into 10 ps unit values
 217  */
 218 static inline unsigned short NS10to10PS (unsigned char spd_byte)
 219 {
 220         unsigned short ns, ns10;
 221
 222         /* isolate upper nibble */
 223         ns = (spd_byte >> 4) & 0x0F;
 224         /* isolate lower nibble */
 225         ns10 = (spd_byte & 0x0F);
 226
 227         return (ns * 100 + ns10 * 10);
 228 }
 229
 230 /*
 231  * translate ns coding of SPD timing values
 232  * into 10 ps unit values
 233  */
 234 static inline unsigned short NSto10PS (unsigned char spd_byte)
 235 {
 236         return (spd_byte * 100);
 237 }
 238
 239 /* This code reads the SPD chip on the sdram and populates
 240  * the array which is passed in with the relevant information */
 241 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 242 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 243 {
 244         unsigned long spd_checksum;
 245
 246 #ifdef ZUMA_NTL
 247         /* zero all the values */
 248         memset (info, 0, sizeof (*info));
 249
 250 /*
 251         if (!slot) {
 252             info->slot = 0;
 253             info->banks = 1;
 254             info->registered = 0;
 255                     info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
 256 /*          info->tpar = 3;
 257             info->tras_clocks = 5;
 258             info->burst_len = 4;
 259 */
 260 #ifdef CONFIG_MV64360_ECC
 261         /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
 262         dimmInfo->errorCheckType = 2;
 263 /*          info->ecc = 2;*/
 264 #endif
 265 }
 266
 267 return 0;
 268
 269 #else
 270         uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 271         int ret;
 272         unsigned int i, j, density = 1;
 273
 274 #ifdef DEBUG
 275         unsigned int k;
 276 #endif
 277         unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
 278         int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
 279         uchar supp_cal, cal_val;
 280         ulong memclk, tmemclk;
 281         ulong tmp;
 282         uchar trp_clocks = 0, tras_clocks;
 283         uchar data[128];
 284
 285         memclk = gd->bus_clk;
 286         tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
 287
 288         debug("before i2c read\n");
 289
 290         ret = i2c_read (addr, 0, 1, data, 128);
 291
 292         debug("after i2c read\n");
 293
 294         /* zero all the values */
 295         memset (dimmInfo, 0, sizeof (*dimmInfo));
 296
 297         /* copy the SPD content 1:1 into the dimmInfo structure */
 298         for (i = 0; i <= 127; i++) {
 299                 dimmInfo->spd_raw_data[i] = data[i];
 300         }
 301
 302         if (ret) {
 303                 debug("No DIMM in slot %d [err = %x]\n", slot, ret);
 304                 return 0;
 305         } else
 306                 dimmInfo->slot = slot;  /* start to fill up dimminfo for this "slot" */
 307
 308 #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 309
 310         for (i = 0; i <= 127; i++) {
 311                 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
 312                         data[i]);
 313         }
 314
 315 #endif
 316 #ifdef DEBUG
 317 /* find Manufactura of Dimm Module */
 318         for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
 319                 dimmInfo->manufactura[i] = data[64 + i];
 320         }
 321         printf ("\nThis RAM-Module is produced by:              %s\n",
 322                 dimmInfo->manufactura);
 323
 324 /* find Manul-ID of Dimm Module */
 325         for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
 326                 dimmInfo->modul_id[i] = data[73 + i];
 327         }
 328         printf ("The Module-ID of this RAM-Module is:           %s\n",
 329                 dimmInfo->modul_id);
 330
 331 /* find Vendor-Data of Dimm Module */
 332         for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
 333                 dimmInfo->vendor_data[i] = data[99 + i];
 334         }
 335         printf ("Vendor Data of this RAM-Module is:             %s\n",
 336                 dimmInfo->vendor_data);
 337
 338 /* find modul_serial_no of Dimm Module */
 339         dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
 340         printf ("Serial No. of this RAM-Module is:              %ld (%lx)\n",
 341                 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 342
 343 /* find Manufac-Data of Dimm Module */
 344         dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
 345         printf ("Manufactoring Date of this RAM-Module is:      %d.%d\n", data[93], data[94]);  /*dimmInfo->manufac_date */
 346
 347 /* find modul_revision of Dimm Module */
 348         dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
 349         printf ("Module Revision of this RAM-Module is:                 %d.%d\n", data[91], data[92]);  /* dimmInfo->modul_revision */
 350
 351 /* find manufac_place of Dimm Module */
 352         dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
 353         printf ("manufac_place of this RAM-Module is:           %d\n",
 354                 dimmInfo->manufac_place);
 355
 356 #endif
 357
 358 /*------------------------------------------------------------------------------------------------------------------------------*/
 359 /* calculate SPD checksum */
 360 /*------------------------------------------------------------------------------------------------------------------------------*/
 361         spd_checksum = 0;
 362
 363         for (i = 0; i <= 62; i++) {
 364                 spd_checksum += data[i];
 365         }
 366
 367         if ((spd_checksum & 0xff) != data[63]) {
 368                 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
 369                 hang ();
 370         }
 371
 372         else
 373                 printf ("SPD Checksum ok!\n");
 374
 375
 376 /*------------------------------------------------------------------------------------------------------------------------------*/
 377         for (i = 2; i <= 35; i++) {
 378                 switch (i) {
 379                 case 2: /* Memory type (DDR / SDRAM) */
 380                         dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
 381                         if (dimmInfo->memoryType == 0)
 382                                 debug
 383                                     ("Dram_type in slot %d is:                  SDRAM\n",
 384                                      dimmInfo->slot);
 385                         if (dimmInfo->memoryType == 1)
 386                                 debug
 387                                     ("Dram_type in slot %d is:                  DDRAM\n",
 388                                      dimmInfo->slot);
 389                         break;
 390 /*------------------------------------------------------------------------------------------------------------------------------*/
 391
 392                 case 3: /* Number Of Row Addresses */
 393                         dimmInfo->numOfRowAddresses = data[i];
 394                         debug
 395                             ("Module Number of row addresses:           %d\n",
 396                              dimmInfo->numOfRowAddresses);
 397                         break;
 398 /*------------------------------------------------------------------------------------------------------------------------------*/
 399
 400                 case 4: /* Number Of Column Addresses */
 401                         dimmInfo->numOfColAddresses = data[i];
 402                         debug
 403                             ("Module Number of col addresses:           %d\n",
 404                              dimmInfo->numOfColAddresses);
 405                         break;
 406 /*------------------------------------------------------------------------------------------------------------------------------*/
 407
 408                 case 5: /* Number Of Module Banks */
 409                         dimmInfo->numOfModuleBanks = data[i];
 410                         debug
 411                             ("Number of Banks on Mod. :                                 %d\n",
 412                              dimmInfo->numOfModuleBanks);
 413                         break;
 414 /*------------------------------------------------------------------------------------------------------------------------------*/
 415
 416                 case 6: /* Data Width */
 417                         dimmInfo->dataWidth = data[i];
 418                         debug
 419                             ("Module Data Width:                                %d\n",
 420                              dimmInfo->dataWidth);
 421                         break;
 422 /*------------------------------------------------------------------------------------------------------------------------------*/
 423
 424                 case 8: /* Voltage Interface */
 425                         switch (data[i]) {
 426                         case 0x0:
 427                                 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
 428                                 debug
 429                                     ("Module is                                         TTL_5V_TOLERANT\n");
 430                                 break;
 431                         case 0x1:
 432                                 dimmInfo->voltageInterface = LVTTL;
 433                                 debug
 434                                     ("Module is                                         LVTTL\n");
 435                                 break;
 436                         case 0x2:
 437                                 dimmInfo->voltageInterface = HSTL_1_5V;
 438                                 debug
 439                                     ("Module is                                         TTL_5V_TOLERANT\n");
 440                                 break;
 441                         case 0x3:
 442                                 dimmInfo->voltageInterface = SSTL_3_3V;
 443                                 debug
 444                                     ("Module is                                         HSTL_1_5V\n");
 445                                 break;
 446                         case 0x4:
 447                                 dimmInfo->voltageInterface = SSTL_2_5V;
 448                                 debug
 449                                     ("Module is                                         SSTL_2_5V\n");
 450                                 break;
 451                         default:
 452                                 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
 453                                 debug
 454                                     ("Module is                                         VOLTAGE_UNKNOWN\n");
 455                                 break;
 456                         }
 457                         break;
 458 /*------------------------------------------------------------------------------------------------------------------------------*/
 459
 460                 case 9: /* Minimum Cycle Time At Max CasLatancy */
 461                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 462                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 463                         maskLeftOfPoint =
 464                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 465                         maskRightOfPoint =
 466                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 467                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 468                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 469                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
 470                                 leftOfPoint;
 471                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
 472                                 rightOfPoint;
 473                         debug
 474                             ("Minimum Cycle Time At Max CasLatancy:             %d.%d [ns]\n",
 475                              leftOfPoint, rightOfPoint);
 476                         break;
 477 /*------------------------------------------------------------------------------------------------------------------------------*/
 478
 479                 case 10:        /* Clock To Data Out */
 480                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 481                         time_tmp =
 482                                 (((data[i] & 0xf0) >> 4) * 10) +
 483                                 ((data[i] & 0x0f));
 484                         leftOfPoint = time_tmp / div;
 485                         rightOfPoint = time_tmp % div;
 486                         dimmInfo->clockToDataOut_LoP = leftOfPoint;
 487                         dimmInfo->clockToDataOut_RoP = rightOfPoint;
 488                         debug("Clock To Data Out:                                       %d.%2d [ns]\n", leftOfPoint, rightOfPoint);     /*dimmInfo->clockToDataOut */
 489                         break;
 490 /*------------------------------------------------------------------------------------------------------------------------------*/
 491
 492 /*#ifdef CONFIG_ECC */
 493                 case 11:        /* Error Check Type */
 494                         dimmInfo->errorCheckType = data[i];
 495                         debug
 496                             ("Error Check Type (0=NONE):                        %d\n",
 497                              dimmInfo->errorCheckType);
 498                         break;
 499 /* #endif */
 500 /*------------------------------------------------------------------------------------------------------------------------------*/
 501
 502                 case 12:        /* Refresh Interval */
 503                         dimmInfo->RefreshInterval = data[i];
 504                         debug
 505                             ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
 506                              dimmInfo->RefreshInterval);
 507                         break;
 508 /*------------------------------------------------------------------------------------------------------------------------------*/
 509
 510                 case 13:        /* Sdram Width */
 511                         dimmInfo->sdramWidth = data[i];
 512                         debug
 513                             ("Sdram Width:                                      %d\n",
 514                              dimmInfo->sdramWidth);
 515                         break;
 516 /*------------------------------------------------------------------------------------------------------------------------------*/
 517
 518                 case 14:        /* Error Check Data Width */
 519                         dimmInfo->errorCheckDataWidth = data[i];
 520                         debug
 521                             ("Error Check Data Width:                   %d\n",
 522                              dimmInfo->errorCheckDataWidth);
 523                         break;
 524 /*------------------------------------------------------------------------------------------------------------------------------*/
 525
 526                 case 15:        /* Minimum Clock Delay */
 527                         dimmInfo->minClkDelay = data[i];
 528                         debug
 529                             ("Minimum Clock Delay:                              %d\n",
 530                              dimmInfo->minClkDelay);
 531                         break;
 532 /*------------------------------------------------------------------------------------------------------------------------------*/
 533
 534                 case 16:        /* Burst Length Supported */
 535                            /******-******-******-*******
 536                            * bit3 | bit2 | bit1 | bit0 *
 537                            *******-******-******-*******
 538             burst length = *  8   |  4   |   2  |   1  *
 539                            *****************************
 540
 541             If for example bit0 and bit2 are set, the burst
 542             length supported are 1 and 4. */
 543
 544                         dimmInfo->burstLengthSupported = data[i];
 545 #ifdef DEBUG
 546                         debug
 547                             ("Burst Length Supported:                   ");
 548                         if (dimmInfo->burstLengthSupported & 0x01)
 549                                 debug("1, ");
 550                         if (dimmInfo->burstLengthSupported & 0x02)
 551                                 debug("2, ");
 552                         if (dimmInfo->burstLengthSupported & 0x04)
 553                                 debug("4, ");
 554                         if (dimmInfo->burstLengthSupported & 0x08)
 555                                 debug("8, ");
 556                         debug(" Bit \n");
 557 #endif
 558                         break;
 559 /*------------------------------------------------------------------------------------------------------------------------------*/
 560
 561                 case 17:        /* Number Of Banks On Each Device */
 562                         dimmInfo->numOfBanksOnEachDevice = data[i];
 563                         debug
 564                             ("Number Of Banks On Each Chip:                     %d\n",
 565                              dimmInfo->numOfBanksOnEachDevice);
 566                         break;
 567 /*------------------------------------------------------------------------------------------------------------------------------*/
 568
 569                 case 18:        /* Suported Cas Latencies */
 570
 571                         /*     DDR:
 572                          *******-******-******-******-******-******-******-*******
 573                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 574                          *******-******-******-******-******-******-******-*******
 575                          CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 576                          *********************************************************
 577                          SDRAM:
 578                          *******-******-******-******-******-******-******-*******
 579                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 580                          *******-******-******-******-******-******-******-*******
 581                          CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
 582                          ********************************************************/
 583                         dimmInfo->suportedCasLatencies = data[i];
 584 #ifdef DEBUG
 585                         debug
 586                             ("Suported Cas Latencies: (CL)                      ");
 587                         if (dimmInfo->memoryType == 0) {        /* SDRAM */
 588                                 for (k = 0; k <= 7; k++) {
 589                                         if (dimmInfo->
 590                                             suportedCasLatencies & (1 << k))
 591                                                 debug
 592                                                     ("%d,                       ",
 593                                                      k + 1);
 594                                 }
 595
 596                         } else {        /* DDR-RAM */
 597
 598                                 if (dimmInfo->suportedCasLatencies & 1)
 599                                         debug("1, ");
 600                                 if (dimmInfo->suportedCasLatencies & 2)
 601                                         debug("1.5, ");
 602                                 if (dimmInfo->suportedCasLatencies & 4)
 603                                         debug("2, ");
 604                                 if (dimmInfo->suportedCasLatencies & 8)
 605                                         debug("2.5, ");
 606                                 if (dimmInfo->suportedCasLatencies & 16)
 607                                         debug("3, ");
 608                                 if (dimmInfo->suportedCasLatencies & 32)
 609                                         debug("3.5, ");
 610
 611                         }
 612                         debug("\n");
 613 #endif
 614                         /* Calculating MAX CAS latency */
 615                         for (j = 7; j > 0; j--) {
 616                                 if (((dimmInfo->
 617                                       suportedCasLatencies >> j) & 0x1) ==
 618                                     1) {
 619                                         switch (dimmInfo->memoryType) {
 620                                         case DDR:
 621                                                 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
 622                                                 switch (j) {
 623                                                 case 7:
 624                                                         debug
 625                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n");
 626                                                         dimmInfo->
 627                                                                 maxClSupported_DDR
 628                                                                 =
 629                                                                 DDR_CL_FAULT;
 630                                                         hang ();
 631                                                         break;
 632                                                 case 6:
 633                                                         debug
 634                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n");
 635                                                         dimmInfo->
 636                                                                 maxClSupported_DDR
 637                                                                 =
 638                                                                 DDR_CL_FAULT;
 639                                                         hang ();
 640                                                         break;
 641                                                 case 5:
 642                                                         debug
 643                                                             ("Max. Cas Latencies (DDR):                         3.5 clk's\n");
 644                                                         dimmInfo->
 645                                                                 maxClSupported_DDR
 646                                                                 = DDR_CL_3_5;
 647                                                         break;
 648                                                 case 4:
 649                                                         debug
 650                                                             ("Max. Cas Latencies (DDR):                         3 clk's \n");
 651                                                         dimmInfo->
 652                                                                 maxClSupported_DDR
 653                                                                 = DDR_CL_3;
 654                                                         break;
 655                                                 case 3:
 656                                                         debug
 657                                                             ("Max. Cas Latencies (DDR):                         2.5 clk's \n");
 658                                                         dimmInfo->
 659                                                                 maxClSupported_DDR
 660                                                                 = DDR_CL_2_5;
 661                                                         break;
 662                                                 case 2:
 663                                                         debug
 664                                                             ("Max. Cas Latencies (DDR):                         2 clk's \n");
 665                                                         dimmInfo->
 666                                                                 maxClSupported_DDR
 667                                                                 = DDR_CL_2;
 668                                                         break;
 669                                                 case 1:
 670                                                         debug
 671                                                             ("Max. Cas Latencies (DDR):                         1.5 clk's \n");
 672                                                         dimmInfo->
 673                                                                 maxClSupported_DDR
 674                                                                 = DDR_CL_1_5;
 675                                                         break;
 676                                                 }
 677
 678                                                 /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
 679                                                    lower then our SDRAM cycle count, we won't be able to support this CAL
 680                                                    and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
 681                                                 if ((dimmInfo->
 682                                                      minimumCycleTimeAtMaxCasLatancy_LoP
 683                                                      <
 684                                                      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 685                                                     ||
 686                                                     ((dimmInfo->
 687                                                       minimumCycleTimeAtMaxCasLatancy_LoP
 688                                                       ==
 689                                                       CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 690                                                      && (dimmInfo->
 691                                                          minimumCycleTimeAtMaxCasLatancy_RoP
 692                                                          <
 693                                                          CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 694                                                 {
 695                                                         dimmInfo->
 696                                                                 maxClSupported_DDR
 697                                                                 =
 698                                                                 dimmInfo->
 699                                                                 maxClSupported_DDR
 700                                                                 >> 1;
 701                                                         debug
 702                                                             ("*** Change actual Cas Latencies cause of minimumCycleTime n");
 703                                                 }
 704                                                 /* ronen - checkif the Dimm frequency compared to the Sysclock. */
 705                                                 if ((dimmInfo->
 706                                                      minimumCycleTimeAtMaxCasLatancy_LoP
 707                                                      >
 708                                                      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 709                                                     ||
 710                                                     ((dimmInfo->
 711                                                       minimumCycleTimeAtMaxCasLatancy_LoP
 712                                                       ==
 713                                                       CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 714                                                      && (dimmInfo->
 715                                                          minimumCycleTimeAtMaxCasLatancy_RoP
 716                                                          >
 717                                                          CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 718                                                 {
 719                                                         printf ("*********************************************************\n");
 720                                                         printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
 721                                                         printf ("*********************************************************\n");
 722                                                         hang ();
 723                                                 }
 724
 725                                                 dimmInfo->
 726                                                         maxCASlatencySupported_LoP
 727                                                         =
 728                                                         1 +
 729                                                         (int) (5 * j / 10);
 730                                                 if (((5 * j) % 10) != 0)
 731                                                         dimmInfo->
 732                                                                 maxCASlatencySupported_RoP
 733                                                                 = 5;
 734                                                 else
 735                                                         dimmInfo->
 736                                                                 maxCASlatencySupported_RoP
 737                                                                 = 0;
 738                                                 debug
 739                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation):        %d.%d \n",
 740                                                      dimmInfo->
 741                                                      maxCASlatencySupported_LoP,
 742                                                      dimmInfo->
 743                                                      maxCASlatencySupported_RoP);
 744                                                 break;
 745                                         case SDRAM:
 746                                                 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
 747                                                 dimmInfo->maxClSupported_SD = j;        /*  Cas Latency DDR-RAM Coded                   */
 748                                                 debug
 749                                                     ("Max. Cas Latencies (SD): %d\n",
 750                                                      dimmInfo->
 751                                                      maxClSupported_SD);
 752                                                 dimmInfo->
 753                                                         maxCASlatencySupported_LoP
 754                                                         = j;
 755                                                 dimmInfo->
 756                                                         maxCASlatencySupported_RoP
 757                                                         = 0;
 758                                                 debug
 759                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
 760                                                      dimmInfo->
 761                                                      maxCASlatencySupported_LoP,
 762                                                      dimmInfo->
 763                                                      maxCASlatencySupported_RoP);
 764                                                 break;
 765                                         }
 766                                         break;
 767                                 }
 768                         }
 769                         break;
 770 /*------------------------------------------------------------------------------------------------------------------------------*/
 771
 772                 case 21:        /* Buffered Address And Control Inputs */
 773                         debug("\nModul Attributes (SPD Byte 21): \n");
 774                         dimmInfo->bufferedAddrAndControlInputs =
 775                                 data[i] & BIT0;
 776                         dimmInfo->registeredAddrAndControlInputs =
 777                                 (data[i] & BIT1) >> 1;
 778                         dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
 779                         dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
 780                         dimmInfo->registeredDQMBinputs =
 781                                 (data[i] & BIT4) >> 4;
 782                         dimmInfo->differentialClockInput =
 783                                 (data[i] & BIT5) >> 5;
 784                         dimmInfo->redundantRowAddressing =
 785                                 (data[i] & BIT6) >> 6;
 786 #ifdef DEBUG
 787                         if (dimmInfo->bufferedAddrAndControlInputs == 1)
 788                                 debug
 789                                     (" - Buffered Address/Control Input:                Yes \n");
 790                         else
 791                                 debug
 792                                     (" - Buffered Address/Control Input:                No \n");
 793
 794                         if (dimmInfo->registeredAddrAndControlInputs == 1)
 795                                 debug
 796                                     (" - Registered Address/Control Input:              Yes \n");
 797                         else
 798                                 debug
 799                                     (" - Registered Address/Control Input:              No \n");
 800
 801                         if (dimmInfo->onCardPLL == 1)
 802                                 debug
 803                                     (" - On-Card PLL (clock):                           Yes \n");
 804                         else
 805                                 debug
 806                                     (" - On-Card PLL (clock):                           No \n");
 807
 808                         if (dimmInfo->bufferedDQMBinputs == 1)
 809                                 debug
 810                                     (" - Bufferd DQMB Inputs:                           Yes \n");
 811                         else
 812                                 debug
 813                                     (" - Bufferd DQMB Inputs:                           No \n");
 814
 815                         if (dimmInfo->registeredDQMBinputs == 1)
 816                                 debug
 817                                     (" - Registered DQMB Inputs:                        Yes \n");
 818                         else
 819                                 debug
 820                                     (" - Registered DQMB Inputs:                        No \n");
 821
 822                         if (dimmInfo->differentialClockInput == 1)
 823                                 debug
 824                                     (" - Differential Clock Input:                      Yes \n");
 825                         else
 826                                 debug
 827                                     (" - Differential Clock Input:                      No \n");
 828
 829                         if (dimmInfo->redundantRowAddressing == 1)
 830                                 debug
 831                                     (" - redundant Row Addressing:                      Yes \n");
 832                         else
 833                                 debug
 834                                     (" - redundant Row Addressing:                      No \n");
 835
 836 #endif
 837                         break;
 838 /*------------------------------------------------------------------------------------------------------------------------------*/
 839
 840                 case 22:        /* Suported AutoPreCharge */
 841                         debug("\nModul Attributes (SPD Byte 22): \n");
 842                         dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
 843                         dimmInfo->suportedAutoPreCharge =
 844                                 (data[i] & BIT1) >> 1;
 845                         dimmInfo->suportedPreChargeAll =
 846                                 (data[i] & BIT2) >> 2;
 847                         dimmInfo->suportedWrite1ReadBurst =
 848                                 (data[i] & BIT3) >> 3;
 849                         dimmInfo->suported5PercentLowVCC =
 850                                 (data[i] & BIT4) >> 4;
 851                         dimmInfo->suported5PercentUpperVCC =
 852                                 (data[i] & BIT5) >> 5;
 853 #ifdef DEBUG
 854                         if (dimmInfo->suportedEarlyRasPreCharge == 1)
 855                                 debug
 856                                     (" - Early Ras Precharge:                   Yes \n");
 857                         else
 858                                 debug
 859                                     (" -  Early Ras Precharge:                  No \n");
 860
 861                         if (dimmInfo->suportedAutoPreCharge == 1)
 862                                 debug
 863                                     (" - AutoPreCharge:                         Yes \n");
 864                         else
 865                                 debug
 866                                     (" -  AutoPreCharge:                                No \n");
 867
 868                         if (dimmInfo->suportedPreChargeAll == 1)
 869                                 debug
 870                                     (" - Precharge All:                         Yes \n");
 871                         else
 872                                 debug
 873                                     (" -  Precharge All:                                No \n");
 874
 875                         if (dimmInfo->suportedWrite1ReadBurst == 1)
 876                                 debug
 877                                     (" - Write 1/ReadBurst:                             Yes \n");
 878                         else
 879                                 debug
 880                                     (" -  Write 1/ReadBurst:                            No \n");
 881
 882                         if (dimmInfo->suported5PercentLowVCC == 1)
 883                                 debug
 884                                     (" - lower VCC tolerance:                   5 Percent \n");
 885                         else
 886                                 debug
 887                                     ("  - lower VCC tolerance:                  10 Percent \n");
 888
 889                         if (dimmInfo->suported5PercentUpperVCC == 1)
 890                                 debug
 891                                     (" - upper VCC tolerance:                   5 Percent \n");
 892                         else
 893                                 debug
 894                                     (" -  upper VCC tolerance:                  10 Percent \n");
 895
 896 #endif
 897                         break;
 898 /*------------------------------------------------------------------------------------------------------------------------------*/
 899
 900                 case 23:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
 901                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 902                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 903                         maskLeftOfPoint =
 904                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 905                         maskRightOfPoint =
 906                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 907                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 908                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 909                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
 910                                 leftOfPoint;
 911                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
 912                                 rightOfPoint;
 913                         debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint);     /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 914                         break;
 915 /*------------------------------------------------------------------------------------------------------------------------------*/
 916
 917                 case 24:        /* Clock To Data Out 2nd highest Cas Latency Value */
 918                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 919                         time_tmp =
 920                                 (((data[i] & 0xf0) >> 4) * 10) +
 921                                 ((data[i] & 0x0f));
 922                         leftOfPoint = time_tmp / div;
 923                         rightOfPoint = time_tmp % div;
 924                         dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
 925                         dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
 926                         debug
 927                             ("Clock To Data Out (2nd CL value):                 %d.%2d [ns]\n",
 928                              leftOfPoint, rightOfPoint);
 929                         break;
 930 /*------------------------------------------------------------------------------------------------------------------------------*/
 931
 932                 case 25:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
 933                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 934                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 935                         maskLeftOfPoint =
 936                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 937                         maskRightOfPoint =
 938                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 939                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 940                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 941                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
 942                                 leftOfPoint;
 943                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
 944                                 rightOfPoint;
 945                         debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint);     /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 946                         break;
 947 /*------------------------------------------------------------------------------------------------------------------------------*/
 948
 949                 case 26:        /* Clock To Data Out 3rd highest Cas Latency Value */
 950                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 951                         time_tmp =
 952                                 (((data[i] & 0xf0) >> 4) * 10) +
 953                                 ((data[i] & 0x0f));
 954                         leftOfPoint = time_tmp / div;
 955                         rightOfPoint = time_tmp % div;
 956                         dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
 957                         dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
 958                         debug
 959                             ("Clock To Data Out (3rd CL value):                 %d.%2d [ns]\n",
 960                              leftOfPoint, rightOfPoint);
 961                         break;
 962 /*------------------------------------------------------------------------------------------------------------------------------*/
 963
 964                 case 27:        /* Minimum Row Precharge Time */
 965                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 966                         maskLeftOfPoint =
 967                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 968                         maskRightOfPoint =
 969                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 970                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 971                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 972
 973                         dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);   /* measured in n times 10ps Intervals */
 974                         trp_clocks =
 975                                 (dimmInfo->minRowPrechargeTime +
 976                                  (tmemclk - 1)) / tmemclk;
 977                         debug
 978                             ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
 979                              tmemclk, tmemclk / 100, tmemclk % 100);
 980                         debug
 981                             ("Minimum Row Precharge Time [ns]:          %d.%2d = in Clk cycles %d\n",
 982                              leftOfPoint, rightOfPoint, trp_clocks);
 983                         break;
 984 /*------------------------------------------------------------------------------------------------------------------------------*/
 985
 986                 case 28:        /* Minimum Row Active to Row Active Time */
 987                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 988                         maskLeftOfPoint =
 989                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 990                         maskRightOfPoint =
 991                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 992                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 993                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 994
 995                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
 996                         debug
 997                             ("Minimum Row Active -To- Row Active Delay [ns]:    %d.%2d = in Clk cycles %d\n",
 998                              leftOfPoint, rightOfPoint, trp_clocks);
 999                         break;
1000 /*------------------------------------------------------------------------------------------------------------------------------*/
1001
1002                 case 29:        /* Minimum Ras-To-Cas Delay */
1003                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
1004                         maskLeftOfPoint =
1005                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1006                         maskRightOfPoint =
1007                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1008                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1009                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1010
1011                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
1012                         debug
1013                             ("Minimum Ras-To-Cas Delay [ns]:                    %d.%2d = in Clk cycles %d\n",
1014                              leftOfPoint, rightOfPoint, trp_clocks);
1015                         break;
1016 /*------------------------------------------------------------------------------------------------------------------------------*/
1017
1018                 case 30:        /* Minimum Ras Pulse Width */
1019                         dimmInfo->minRasPulseWidth = data[i];
1020                         tras_clocks =
1021                                 (NSto10PS (data[i]) +
1022                                  (tmemclk - 1)) / tmemclk;
1023                         debug
1024                             ("Minimum Ras Pulse Width [ns]:                     %d = in Clk cycles %d\n",
1025                              dimmInfo->minRasPulseWidth, tras_clocks);
1026
1027                         break;
1028 /*------------------------------------------------------------------------------------------------------------------------------*/
1029
1030                 case 31:        /* Module Bank Density */
1031                         dimmInfo->moduleBankDensity = data[i];
1032                         debug
1033                             ("Module Bank Density:                              %d\n",
1034                              dimmInfo->moduleBankDensity);
1035 #ifdef DEBUG
1036                         debug
1037                             ("*** Offered Densities (more than 1 = Multisize-Module): ");
1038                         {
1039                                 if (dimmInfo->moduleBankDensity & 1)
1040                                         debug("4MB, ");
1041                                 if (dimmInfo->moduleBankDensity & 2)
1042                                         debug("8MB, ");
1043                                 if (dimmInfo->moduleBankDensity & 4)
1044                                         debug("16MB, ");
1045                                 if (dimmInfo->moduleBankDensity & 8)
1046                                         debug("32MB, ");
1047                                 if (dimmInfo->moduleBankDensity & 16)
1048                                         debug("64MB, ");
1049                                 if (dimmInfo->moduleBankDensity & 32)
1050                                         debug("128MB, ");
1051                                 if ((dimmInfo->moduleBankDensity & 64)
1052                                     || (dimmInfo->moduleBankDensity & 128)) {
1053                                         debug("ERROR, ");
1054                                         hang ();
1055                                 }
1056                         }
1057                         debug("\n");
1058 #endif
1059                         break;
1060 /*------------------------------------------------------------------------------------------------------------------------------*/
1061
1062                 case 32:        /* Address And Command Setup Time (measured in ns/1000) */
1063                         sign = 1;
1064                         switch (dimmInfo->memoryType) {
1065                         case DDR:
1066                                 time_tmp =
1067                                         (((data[i] & 0xf0) >> 4) * 10) +
1068                                         ((data[i] & 0x0f));
1069                                 leftOfPoint = time_tmp / 100;
1070                                 rightOfPoint = time_tmp % 100;
1071                                 break;
1072                         case SDRAM:
1073                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1074                                 if (leftOfPoint > 7) {
1075                                         leftOfPoint = data[i] & 0x70 >> 4;
1076                                         sign = -1;
1077                                 }
1078                                 rightOfPoint = (data[i] & 0x0f);
1079                                 break;
1080                         }
1081                         dimmInfo->addrAndCommandSetupTime =
1082                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1083                         debug
1084                             ("Address And Command Setup Time [ns]:              %d.%d\n",
1085                              sign * leftOfPoint, rightOfPoint);
1086                         break;
1087 /*------------------------------------------------------------------------------------------------------------------------------*/
1088
1089                 case 33:        /* Address And Command Hold Time */
1090                         sign = 1;
1091                         switch (dimmInfo->memoryType) {
1092                         case DDR:
1093                                 time_tmp =
1094                                         (((data[i] & 0xf0) >> 4) * 10) +
1095                                         ((data[i] & 0x0f));
1096                                 leftOfPoint = time_tmp / 100;
1097                                 rightOfPoint = time_tmp % 100;
1098                                 break;
1099                         case SDRAM:
1100                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1101                                 if (leftOfPoint > 7) {
1102                                         leftOfPoint = data[i] & 0x70 >> 4;
1103                                         sign = -1;
1104                                 }
1105                                 rightOfPoint = (data[i] & 0x0f);
1106                                 break;
1107                         }
1108                         dimmInfo->addrAndCommandHoldTime =
1109                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1110                         debug
1111                             ("Address And Command Hold Time [ns]:               %d.%d\n",
1112                              sign * leftOfPoint, rightOfPoint);
1113                         break;
1114 /*------------------------------------------------------------------------------------------------------------------------------*/
1115
1116                 case 34:        /* Data Input Setup Time */
1117                         sign = 1;
1118                         switch (dimmInfo->memoryType) {
1119                         case DDR:
1120                                 time_tmp =
1121                                         (((data[i] & 0xf0) >> 4) * 10) +
1122                                         ((data[i] & 0x0f));
1123                                 leftOfPoint = time_tmp / 100;
1124                                 rightOfPoint = time_tmp % 100;
1125                                 break;
1126                         case SDRAM:
1127                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1128                                 if (leftOfPoint > 7) {
1129                                         leftOfPoint = data[i] & 0x70 >> 4;
1130                                         sign = -1;
1131                                 }
1132                                 rightOfPoint = (data[i] & 0x0f);
1133                                 break;
1134                         }
1135                         dimmInfo->dataInputSetupTime =
1136                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1137                         debug
1138                             ("Data Input Setup Time [ns]:                       %d.%d\n",
1139                              sign * leftOfPoint, rightOfPoint);
1140                         break;
1141 /*------------------------------------------------------------------------------------------------------------------------------*/
1142
1143                 case 35:        /* Data Input Hold Time */
1144                         sign = 1;
1145                         switch (dimmInfo->memoryType) {
1146                         case DDR:
1147                                 time_tmp =
1148                                         (((data[i] & 0xf0) >> 4) * 10) +
1149                                         ((data[i] & 0x0f));
1150                                 leftOfPoint = time_tmp / 100;
1151                                 rightOfPoint = time_tmp % 100;
1152                                 break;
1153                         case SDRAM:
1154                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1155                                 if (leftOfPoint > 7) {
1156                                         leftOfPoint = data[i] & 0x70 >> 4;
1157                                         sign = -1;
1158                                 }
1159                                 rightOfPoint = (data[i] & 0x0f);
1160                                 break;
1161                         }
1162                         dimmInfo->dataInputHoldTime =
1163                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1164                         debug
1165                             ("Data Input Hold Time [ns]:                        %d.%d\n\n",
1166                              sign * leftOfPoint, rightOfPoint);
1167                         break;
1168 /*------------------------------------------------------------------------------------------------------------------------------*/
1169                 }
1170         }
1171         /* calculating the sdram density */
1172         for (i = 0;
1173              i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1174              i++) {
1175                 density = density * 2;
1176         }
1177         dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1178                 dimmInfo->sdramWidth;
1179         dimmInfo->numberOfDevices =
1180                 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1181                 dimmInfo->numOfModuleBanks;
1182         if ((dimmInfo->errorCheckType == 0x1)
1183             || (dimmInfo->errorCheckType == 0x2)
1184             || (dimmInfo->errorCheckType == 0x3)) {
1185                 dimmInfo->size =
1186                         (dimmInfo->deviceDensity / 8) *
1187                         (dimmInfo->numberOfDevices -
1188                          /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
1189                          dimmInfo->numberOfDevices / 8);
1190         } else {
1191                 dimmInfo->size =
1192                         (dimmInfo->deviceDensity / 8) *
1193                         dimmInfo->numberOfDevices;
1194         }
1195
1196         /* compute the module DRB size */
1197         tmp = (1 <<
1198                (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1199         tmp *= dimmInfo->numOfModuleBanks;
1200         tmp *= dimmInfo->sdramWidth;
1201         tmp = tmp >> 24;        /* div by 0x4000000 (64M)       */
1202         dimmInfo->drb_size = (uchar) tmp;
1203         debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
1204
1205         /* try a CAS latency of 3 first... */
1206
1207         /* bit 1 is CL2, bit 2 is CL3 */
1208         supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
1209
1210         cal_val = 0;
1211         if (supp_cal & 3) {
1212                 if (NS10to10PS (data[9]) <= tmemclk)
1213                         cal_val = 3;
1214         }
1215
1216         /* then 2... */
1217         if (supp_cal & 2) {
1218                 if (NS10to10PS (data[23]) <= tmemclk)
1219                         cal_val = 2;
1220         }
1221
1222         debug("cal_val = %d\n", cal_val);
1223
1224         /* bummer, did't work... */
1225         if (cal_val == 0) {
1226                 debug("Couldn't find a good CAS latency\n");
1227                 hang ();
1228                 return 0;
1229         }
1230
1231         return true;
1232
1233 #endif
1234 }
1235
1236 /* sets up the GT properly with information passed in */
1237 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1238 {
1239         ulong tmp, check;
1240         ulong tmp_sdram_mode = 0;       /* 0x141c */
1241         ulong tmp_dunit_control_low = 0;        /* 0x1404 */
1242         int i;
1243
1244         /* added 8/21/2003 P. Marchese */
1245         unsigned int sdram_config_reg;
1246
1247         /* added 10/10/2003 P. Marchese */
1248         ulong sdram_chip_size;
1249
1250         /* sanity checking */
1251         if (!info->numOfModuleBanks) {
1252                 printf ("setup_sdram called with 0 banks\n");
1253                 return 1;
1254         }
1255
1256         /* delay line */
1257         set_dfcdlInit ();       /* may be its not needed */
1258         debug("Delay line set done\n");
1259
1260         /* set SDRAM mode NOP */ /* To_do check it */
1261         GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1262         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1263                 debug
1264                     ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
1265         }
1266
1267         /* SDRAM configuration */
1268 /* added 8/21/2003 P. Marchese */
1269 /* code allows usage of registered DIMMS */
1270
1271         /* figure out the memory refresh internal */
1272         switch (info->RefreshInterval) {
1273         case 0x0:
1274         case 0x80:              /* refresh period is 15.625 usec */
1275                 sdram_config_reg =
1276                         (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
1277                                         / (float) 1000000.0);
1278                 break;
1279         case 0x1:
1280         case 0x81:              /* refresh period is 3.9 usec */
1281                 sdram_config_reg =
1282                         (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
1283                                         (float) 1000000.0);
1284                 break;
1285         case 0x2:
1286         case 0x82:              /* refresh period is 7.8 usec */
1287                 sdram_config_reg =
1288                         (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
1289                                         (float) 1000000.0);
1290                 break;
1291         case 0x3:
1292         case 0x83:              /* refresh period is 31.3 usec */
1293                 sdram_config_reg =
1294                         (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
1295                                         (float) 1000000.0);
1296                 break;
1297         case 0x4:
1298         case 0x84:              /* refresh period is 62.5 usec */
1299                 sdram_config_reg =
1300                         (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
1301                                         (float) 1000000.0);
1302                 break;
1303         case 0x5:
1304         case 0x85:              /* refresh period is 125 usec */
1305                 sdram_config_reg =
1306                         (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
1307                                         (float) 1000000.0);
1308                 break;
1309         default:                /* refresh period undefined */
1310                 printf ("DRAM refresh period is unknown!\n");
1311                 printf ("Aborting DRAM setup with an error\n");
1312                 hang ();
1313                 break;
1314         }
1315         debug("calculated refresh interval %0x\n", sdram_config_reg);
1316
1317         /* make sure the refresh value is only 14 bits */
1318         if (sdram_config_reg > 0x1fff)
1319                 sdram_config_reg = 0x1fff;
1320         debug("adjusted refresh interval %0x\n", sdram_config_reg);
1321
1322         /* we want physical bank interleaving and */
1323         /* virtual bank interleaving enabled so do nothing */
1324         /* since these bits need to be zero to enable the interleaving */
1325
1326         /*  registered DRAM ? */
1327         if (info->registeredAddrAndControlInputs == 1) {
1328                 /* it's registered DRAM, so set the reg. DRAM bit */
1329                 sdram_config_reg = sdram_config_reg | BIT17;
1330                 debug("Enabling registered DRAM bit\n");
1331         }
1332         /* turn on DRAM ECC? */
1333 #ifdef CONFIG_MV64360_ECC
1334         if (info->errorCheckType == 0x2) {
1335                 /* DRAM has ECC, so turn it on */
1336                 sdram_config_reg = sdram_config_reg | BIT18;
1337                 debug("Enabling ECC\n");
1338         }
1339 #endif
1340         /* set the data DQS pin configuration */
1341         switch (info->sdramWidth) {
1342         case 0x4:               /* memory is x4 */
1343                 sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
1344                 debug("Data DQS pins set for 16 pins\n");
1345                 break;
1346         case 0x8:               /* memory is x8 or x16 */
1347         case 0x10:
1348                 sdram_config_reg = sdram_config_reg | BIT21;
1349                 debug("Data DQS pins set for 8 pins\n");
1350                 break;
1351         case 0x20:              /* memory is x32 */
1352                 /* both bits are cleared for x32 so nothing to do */
1353                 debug("Data DQS pins set for 2 pins\n");
1354                 break;
1355         default:                /* memory width unsupported */
1356                 printf ("DRAM chip width is unknown!\n");
1357                 printf ("Aborting DRAM setup with an error\n");
1358                 hang ();
1359                 break;
1360         }
1361
1362         /* perform read buffer assignments */
1363         /* we are going to use the Power-up defaults */
1364         /* bit 26 = CPU = buffer 1 */
1365         /* bit 27 = PCI bus #0 = buffer 0 */
1366         /* bit 28 = PCI bus #1 = buffer 0 */
1367         /* bit 29 = MPSC = buffer 0 */
1368         /* bit 30 = IDMA = buffer 0 */
1369         /* bit 31 = Gigabit = buffer 0 */
1370         sdram_config_reg = sdram_config_reg | BIT26;
1371         /*  sdram_config_reg = sdram_config_reg | 0x58000000; */
1372         /* sdram_config_reg = sdram_config_reg & 0xffffff00;  */
1373
1374         /* write the value into the SDRAM configuration register */
1375         GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
1376         debug
1377             ("OOOOOOOOO sdram_conf 0x1400: %08x\n",
1378              GTREGREAD (SDRAM_CONFIG));
1379
1380         /* SDRAM open pages control keep open as much as I can */
1381         GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1382         debug
1383             ("sdram_open_pages_controll 0x1414: %08x\n",
1384              GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
1385
1386         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1387         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1388         if (tmp == 0)
1389                 debug("Core Signals are sync (by HW-Setting)!!!\n");
1390         else
1391                 debug
1392                     ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
1393
1394         /* SDRAM set CAS Latency according to SPD information */
1395         switch (info->memoryType) {
1396         case SDRAM:
1397                 printf ("### SD-RAM not supported !!!\n");
1398                 printf ("Aborting!!!\n");
1399                 hang ();
1400                 /* ToDo fill SD-RAM if needed !!!!! */
1401                 break;
1402                 /* Calculate the settings for SDRAM mode and Dunit control low registers */
1403                 /* Values set according to technical bulletin TB-92 rev. c */
1404         case DDR:
1405                 debug("### SET-CL for DDR-RAM\n");
1406                 switch (info->maxClSupported_DDR) {
1407                 case DDR_CL_3:
1408                         tmp_sdram_mode = 0x32;  /* CL=3 Burstlength = 4 */
1409                         if (tmp == 1) { /* clocks sync */
1410                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1411                                         tmp_dunit_control_low = 0x05110051;
1412                                 else
1413                                         tmp_dunit_control_low = 0x24110051;
1414                                 debug
1415                                     ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1416                                      tmp_sdram_mode, tmp_dunit_control_low);
1417                         } else {        /* clk sync. bypassed   */
1418
1419                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1420                                         tmp_dunit_control_low = 0x2C1107F2;
1421                                 else
1422                                         tmp_dunit_control_low = 0x3C1107d2;
1423                                 debug
1424                                     ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1425                                      tmp_sdram_mode, tmp_dunit_control_low);
1426                         }
1427                         break;
1428                 case DDR_CL_2_5:
1429                         tmp_sdram_mode = 0x62;  /* CL=2.5 Burstlength = 4 */
1430                         if (tmp == 1) { /* clocks sync */
1431                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1432                                         tmp_dunit_control_low = 0x25110051;
1433                                 else
1434                                         tmp_dunit_control_low = 0x24110051;
1435                                 debug
1436                                     ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1437                                      tmp_sdram_mode, tmp_dunit_control_low);
1438                         } else {        /* clk sync. bypassed   */
1439
1440                                 if (info->registeredAddrAndControlInputs == 1) {        /* registerd DDR SDRAM? */
1441                                         printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
1442                                         printf ("Aborting!!!\n");
1443                                         hang ();
1444                                 } else
1445                                         tmp_dunit_control_low = 0x1B1107d2;
1446                                 debug
1447                                     ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1448                                      tmp_sdram_mode, tmp_dunit_control_low);
1449                         }
1450                         break;
1451                 case DDR_CL_2:
1452                         tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1453                         if (tmp == 1) { /* clocks sync */
1454                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1455                                         tmp_dunit_control_low = 0x04110051;
1456                                 else
1457                                         tmp_dunit_control_low = 0x03110051;
1458                                 debug
1459                                     ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1460                                      tmp_sdram_mode, tmp_dunit_control_low);
1461                         } else {        /* clk sync. bypassed   */
1462
1463                                 if (info->registeredAddrAndControlInputs == 1) {        /* registerd DDR SDRAM? */
1464                                         printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
1465                                         printf ("Aborting!!!\n");
1466                                         hang ();
1467                                 } else
1468                                         tmp_dunit_control_low = 0x3B1107d2;
1469                                 debug
1470                                     ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1471                                      tmp_sdram_mode, tmp_dunit_control_low);
1472                         }
1473                         break;
1474                 case DDR_CL_1_5:
1475                         tmp_sdram_mode = 0x52;  /* CL=1.5 Burstlength = 4 */
1476                         if (tmp == 1) { /* clocks sync */
1477                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1478                                         tmp_dunit_control_low = 0x24110051;
1479                                 else
1480                                         tmp_dunit_control_low = 0x23110051;
1481                                 debug
1482                                     ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1483                                      tmp_sdram_mode, tmp_dunit_control_low);
1484                         } else {        /* clk sync. bypassed   */
1485
1486                                 if (info->registeredAddrAndControlInputs == 1) {        /* registerd DDR SDRAM? */
1487                                         printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
1488                                         printf ("Aborting!!!\n");
1489                                         hang ();
1490                                 } else
1491                                         tmp_dunit_control_low = 0x1A1107d2;
1492                                 debug
1493                                     ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1494                                      tmp_sdram_mode, tmp_dunit_control_low);
1495                         }
1496                         break;
1497
1498                 default:
1499                         printf ("Max. CL is out of range %d\n",
1500                                 info->maxClSupported_DDR);
1501                         hang ();
1502                         break;
1503                 }               /* end DDR switch */
1504                 break;
1505         }                       /* end CL switch */
1506
1507         /* Write results of CL detection procedure */
1508         /* set SDRAM mode reg. 0x141c */
1509         GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1510
1511         /* set SDRAM mode SetCommand 0x1418 */
1512         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1513         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1514                 debug
1515                     ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1516         }
1517
1518         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1519         GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
1520
1521         /* set SDRAM mode SetCommand 0x1418 */
1522         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1523         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1524                 debug
1525                     ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
1526         }
1527
1528 /*------------------------------------------------------------------------------ */
1529
1530         /* bank parameters */
1531         /* SDRAM address decode register 0x1410 */
1532         /* program this with the default value */
1533         tmp = 0x02;             /* power-up default address select decoding value */
1534
1535         debug("drb_size (n*64Mbit): %d\n", info->drb_size);
1536 /* figure out the DRAM chip size */
1537         sdram_chip_size =
1538                 (1 << (info->numOfRowAddresses + info->numOfColAddresses));
1539         sdram_chip_size *= info->sdramWidth;
1540         sdram_chip_size *= 4;
1541         debug("computed sdram chip size is %#lx\n", sdram_chip_size);
1542         /* divide sdram chip size by 64 Mbits */
1543         sdram_chip_size = sdram_chip_size / 0x4000000;
1544         switch (sdram_chip_size) {
1545         case 1:         /* 64 Mbit */
1546         case 2:         /* 128 Mbit */
1547                 debug("RAM-Device_size 64Mbit or 128Mbit)\n");
1548                 tmp |= (0x00 << 4);
1549                 break;
1550         case 4:         /* 256 Mbit */
1551         case 8:         /* 512 Mbit */
1552                 debug("RAM-Device_size 256Mbit or 512Mbit)\n");
1553                 tmp |= (0x01 << 4);
1554                 break;
1555         case 16:                /* 1 Gbit */
1556         case 32:                /* 2 Gbit */
1557                 debug("RAM-Device_size 1Gbit or 2Gbit)\n");
1558                 tmp |= (0x02 << 4);
1559                 break;
1560         default:
1561                 printf ("Error in dram size calculation\n");
1562                 printf ("RAM-Device_size is unsupported\n");
1563                 hang ();
1564         }
1565
1566         /* SDRAM address control */
1567         GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1568         debug
1569             ("setting up sdram address control (0x1410) with: %08lx \n",
1570              tmp);
1571
1572 /* ------------------------------------------------------------------------------ */
1573 /* same settings for registerd & non-registerd DDR SDRAM */
1574         debug
1575             ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
1576              0x11511220);
1577         GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1578
1579
1580 /* ------------------------------------------------------------------------------ */
1581
1582         /* SDRAM configuration */
1583         tmp = GTREGREAD (SDRAM_CONFIG);
1584
1585         if (info->registeredAddrAndControlInputs
1586             || info->registeredDQMBinputs) {
1587                 tmp |= (1 << 17);
1588                 debug
1589                     ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1590                      info->registeredAddrAndControlInputs,
1591                      info->registeredDQMBinputs);
1592         }
1593
1594         /* Use buffer 1 to return read data to the CPU
1595          * Page 426 MV64360 */
1596         tmp |= (1 << 26);
1597         debug
1598             ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
1599              GTREGREAD (SDRAM_CONFIG));
1600         debug
1601             ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
1602              GTREGREAD (SDRAM_CONFIG));
1603
1604         /* SDRAM timing To_do: */
1605 /* ------------------------------------------------------------------------------ */
1606
1607         debug
1608             ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
1609              0x9);
1610         GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
1611
1612         debug
1613             ("setting up sdram address pads control (0x14c0) with: %08x \n",
1614              0x7d5014a);
1615         GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
1616
1617         debug
1618   ("setting up sdram data pads control (0x14c4) with: %08x \n",
1619              0x7d5014a);
1620         GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
1621
1622 /* ------------------------------------------------------------------------------ */
1623
1624         /* set the SDRAM configuration for each bank */
1625
1626 /*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1627         {
1628                 i = info->slot;
1629                 debug
1630                     ("\n*** Running a MRS cycle for bank %d ***\n", i);
1631
1632                 /* map the bank */
1633                 memory_map_bank (i, 0, GB / 4);
1634
1635                 /* set SDRAM mode */ /* To_do check it */
1636                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1637                 check = GTREGREAD (SDRAM_OPERATION);
1638                 debug
1639                     ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1640                      check);
1641
1642
1643                 /* switch back to normal operation mode */
1644                 GT_REG_WRITE (SDRAM_OPERATION, 0);
1645                 check = GTREGREAD (SDRAM_OPERATION);
1646                 debug
1647                     ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1648                      check);
1649
1650                 /* unmap the bank */
1651                 memory_map_bank (i, 0, 0);
1652         }
1653
1654         return 0;
1655
1656 }
1657
1658 /*
1659  * Check memory range for valid RAM. A simple memory test determines
1660  * the actually available RAM size between addresses `base' and
1661  * `base + maxsize'. Some (not all) hardware errors are detected:
1662  * - short between address lines
1663  * - short between data lines
1664  */
1665 long int dram_size (long int *base, long int maxsize)
1666 {
1667         volatile long int *addr, *b = base;
1668         long int cnt, val, save1, save2;
1669
1670 #define STARTVAL (1<<20)        /* start test at 1M */
1671         for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
1672              cnt <<= 1) {
1673                 addr = base + cnt;      /* pointer arith! */
1674
1675                 save1 = *addr;  /* save contents of addr */
1676                 save2 = *b;     /* save contents of base */
1677
1678                 *addr = cnt;    /* write cnt to addr */
1679                 *b = 0;         /* put null at base */
1680
1681                 /* check at base address */
1682                 if ((*b) != 0) {
1683                         *addr = save1;  /* restore *addr */
1684                         *b = save2;     /* restore *b */
1685                         return (0);
1686                 }
1687                 val = *addr;    /* read *addr */
1688                 val = *addr;    /* read *addr */
1689
1690                 *addr = save1;
1691                 *b = save2;
1692
1693                 if (val != cnt) {
1694                         debug
1695                             ("Found %08x  at Address %08x (failure)\n",
1696                              (unsigned int) val, (unsigned int) addr);
1697                         /* fix boundary condition.. STARTVAL means zero */
1698                         if (cnt == STARTVAL / sizeof (long))
1699                                 cnt = 0;
1700                         return (cnt * sizeof (long));
1701                 }
1702         }
1703         return maxsize;
1704 }
1705
1706 /* ------------------------------------------------------------------------- */
1707
1708 /* ppcboot interface function to SDRAM init - this is where all the
1709  * controlling logic happens */
1710 phys_size_t initdram (int board_type)
1711 {
1712         int checkbank[4] = {[0 ... 3] = 0 };
1713         ulong realsize, total;
1714         AUX_MEM_DIMM_INFO dimmInfo1;
1715         AUX_MEM_DIMM_INFO dimmInfo2;
1716         int nhr, bank_no;
1717         ulong dest, memSpaceAttr;
1718
1719         /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1720
1721         /* check the NHR bit and skip mem init if it's already done */
1722         nhr = get_hid0 () & (1 << 16);
1723
1724         if (nhr) {
1725                 printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1726         } else {
1727                 /* DIMM0 */
1728                 check_dimm (0, &dimmInfo1);
1729
1730                 /* DIMM1 */
1731                 check_dimm (1, &dimmInfo2);
1732
1733                 memory_map_bank (0, 0, 0);
1734                 memory_map_bank (1, 0, 0);
1735                 memory_map_bank (2, 0, 0);
1736                 memory_map_bank (3, 0, 0);
1737
1738                 /* ronen check correct set of DIMMS */
1739                 if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
1740                         if (dimmInfo1.errorCheckType !=
1741                             dimmInfo2.errorCheckType)
1742                                 printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
1743                         if (dimmInfo1.maxClSupported_DDR !=
1744                             dimmInfo2.maxClSupported_DDR)
1745                                 printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
1746                         if (dimmInfo1.registeredAddrAndControlInputs !=
1747                             dimmInfo2.registeredAddrAndControlInputs)
1748                                 printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
1749                 }
1750
1751                 if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
1752                         printf ("Setup for DIMM1 failed.\n");
1753                 }
1754
1755                 if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
1756                         printf ("Setup for DIMM2 failed.\n");
1757                 }
1758
1759                 /* set the NHR bit */
1760                 set_hid0 (get_hid0 () | (1 << 16));
1761         }
1762         /* next, size the SDRAM banks */
1763
1764         realsize = total = 0;
1765         if (dimmInfo1.numOfModuleBanks > 0) {
1766                 checkbank[0] = 1;
1767         }
1768         if (dimmInfo1.numOfModuleBanks > 1) {
1769                 checkbank[1] = 1;
1770         }
1771         if (dimmInfo1.numOfModuleBanks > 2)
1772                 printf ("Error, SPD claims DIMM1 has >2 banks\n");
1773
1774         printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
1775
1776         if (dimmInfo2.numOfModuleBanks > 0) {
1777                 checkbank[2] = 1;
1778         }
1779         if (dimmInfo2.numOfModuleBanks > 1) {
1780                 checkbank[3] = 1;
1781         }
1782         if (dimmInfo2.numOfModuleBanks > 2)
1783                 printf ("Error, SPD claims DIMM2 has >2 banks\n");
1784
1785         printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
1786
1787         for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1788                 /* skip over banks that are not populated */
1789                 if (!checkbank[bank_no])
1790                         continue;
1791
1792                 /* ronen - realsize = dram_size((long int *)total, check); */
1793                 if (bank_no == 0 || bank_no == 1) {
1794                         if (checkbank[1] == 1)
1795                                 realsize = dimmInfo1.size / 2;
1796                         else
1797                                 realsize = dimmInfo1.size;
1798                 }
1799                 if (bank_no == 2 || bank_no == 3) {
1800                         if (checkbank[3] == 1)
1801                                 realsize = dimmInfo2.size / 2;
1802                         else
1803                                 realsize = dimmInfo2.size;
1804                 }
1805                 memory_map_bank (bank_no, total, realsize);
1806
1807                 /* ronen - initialize the DRAM for ECC */
1808 #ifdef CONFIG_MV64360_ECC
1809                 if ((dimmInfo1.errorCheckType != 0) &&
1810                     ((dimmInfo2.errorCheckType != 0)
1811                      || (dimmInfo2.numOfModuleBanks == 0))) {
1812                         printf ("ECC Initialization of Bank %d:", bank_no);
1813                         memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1814                         mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
1815                                              realsize);
1816                         for (dest = total; dest < total + realsize;
1817                              dest += _8M) {
1818                                 mvDmaTransfer (0, total, dest, _8M,
1819                                                BIT8 /*DMA_DTL_128BYTES */  |
1820                                                BIT3 /*DMA_HOLD_SOURCE_ADDR */
1821                                                |
1822                                                BIT11
1823                                                /*DMA_BLOCK_TRANSFER_MODE */ );
1824                                 while (mvDmaIsChannelActive (0));
1825                         }
1826                         printf (" PASS\n");
1827                 }
1828 #endif
1829
1830                 total += realsize;
1831         }
1832
1833         /* ronen- add DRAM conf prints */
1834         switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
1835         case 0x2:
1836                 printf ("CAS Latency = 2");
1837                 break;
1838         case 0x3:
1839                 printf ("CAS Latency = 3");
1840                 break;
1841         case 0x5:
1842                 printf ("CAS Latency = 1.5");
1843                 break;
1844         case 0x6:
1845                 printf ("CAS Latency = 2.5");
1846                 break;
1847         }
1848         printf (" tRP = %d tRAS = %d tRCD=%d\n",
1849                 ((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
1850                 ((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
1851                 ((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
1852
1853 /*      Setup Ethernet DMA Adress window to DRAM Area */
1854         if (total > _256M)
1855                 printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
1856         else
1857                 printf ("Total SDRAM memory is ");
1858         /* (cause all the 4 BATS are taken) */
1859         return (total);
1860 }
1861
1862
1863 /* ronen- add Idma functions for usage of the ecc dram init. */
1864 /*******************************************************************************
1865 * mvDmaIsChannelActive - Checks if a engine is busy.
1866 ********************************************************************************/
1867 int mvDmaIsChannelActive (int engine)
1868 {
1869         ulong data;
1870
1871         data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
1872         if (data & BIT14 /*activity status */ ) {
1873                 return 1;
1874         }
1875         return 0;
1876 }
1877
1878 /*******************************************************************************
1879 * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
1880 *                       map.
1881 *******************************************************************************/
1882 int mvDmaSetMemorySpace (ulong memSpace,
1883                          ulong memSpaceTarget,
1884                          ulong memSpaceAttr, ulong baseAddress, ulong size)
1885 {
1886         ulong temp;
1887
1888         /* The base address must be aligned to the size.  */
1889         if (baseAddress % size != 0) {
1890                 return 0;
1891         }
1892         if (size >= 0x10000 /*64K */ ) {
1893                 size &= 0xffff0000;
1894                 baseAddress = (baseAddress & 0xffff0000);
1895                 /* Set the new attributes */
1896                 GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8,
1897                               (baseAddress | memSpaceTarget | memSpaceAttr));
1898                 GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8),
1899                               (size - 1) & 0xffff0000);
1900                 temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG);
1901                 GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
1902                               (temp & ~(BIT0 << memSpace)));
1903                 return 1;
1904         }
1905         return 0;
1906 }
1907
1908
1909 /*******************************************************************************
1910 * mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
1911 *                 DMA channels.
1912 ********************************************************************************/
1913 int mvDmaTransfer (int engine, ulong sourceAddr,
1914                    ulong destAddr, ulong numOfBytes, ulong command)
1915 {
1916         ulong engOffReg = 0;    /* Engine Offset Register */
1917
1918         if (numOfBytes > 0xffff) {
1919                 command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
1920         }
1921         command = command | ((command >> 6) & 0x7);
1922         engOffReg = engine * 4;
1923         GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
1924                       numOfBytes);
1925         GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
1926                       sourceAddr);
1927         GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
1928                       destAddr);
1929         command =
1930                 command | BIT12 /*DMA_CHANNEL_ENABLE */  | BIT9
1931                 /*DMA_NON_CHAIN_MODE */ ;
1932         /* Activate DMA engine By writting to mvDmaControlRegister */
1933         GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command);
1934         return 1;
1935 }
1936
1937 /****************************************************************************************
1938  *                              SDRAM INIT                                              *
1939  *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb        *
1940  *                This procedure fits only the Atlantis                                 *
1941  *                                                                                      *
1942  ***************************************************************************************/
1943
1944
1945 /****************************************************************************************
1946  *                              DFCDL initialize MV643xx Design Considerations          *
1947  *                                                                                      *
1948  ***************************************************************************************/
1949 int set_dfcdlInit (void)
1950 {
1951         int i;
1952         unsigned int dfcdl_word = 0x391;        /*   0x14f;  ronen new dfcdl */
1953
1954         for (i = 0; i < 64; i++) {
1955                 GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1956 /*      dfcdl_word += 0x41;  - ronen new dfcdl */
1957         }
1958         GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);       /* enable dynamic delay line updating */
1959
1960         return (0);
1961 }