board/atmel/at91sam9260ek/at91sam9260ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91sam9260_matrix.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_pmc.h>
  15 #include <asm/arch/gpio.h>
  16 #include <atmel_mci.h>
  17
  18 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  19 # include <net.h>
  20 #endif
  21 #include <netdev.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /* ------------------------------------------------------------------------- */
  26 /*
  27  * Miscelaneous platform dependent initialisations
  28  */
  29
  30 #ifdef CONFIG_CMD_NAND
  31 static void at91sam9260ek_nand_hw_init(void)
  32 {
  33         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  34         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  35         unsigned long csa;
  36
  37         /* Assign CS3 to NAND/SmartMedia Interface */
  38         csa = readl(&matrix->ebicsa);
  39         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  40         writel(csa, &matrix->ebicsa);
  41
  42         /* Configure SMC CS3 for NAND/SmartMedia */
  43         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  44                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  45                 &smc->cs[3].setup);
  46         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  47                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  48                 &smc->cs[3].pulse);
  49         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  50                 &smc->cs[3].cycle);
  51         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  52                 AT91_SMC_MODE_EXNW_DISABLE |
  53 #ifdef CONFIG_SYS_NAND_DBW_16
  54                 AT91_SMC_MODE_DBW_16 |
  55 #else /* CONFIG_SYS_NAND_DBW_8 */
  56                 AT91_SMC_MODE_DBW_8 |
  57 #endif
  58                 AT91_SMC_MODE_TDF_CYCLE(2),
  59                 &smc->cs[3].mode);
  60
  61         /* Configure RDY/BSY */
  62         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  63
  64         /* Enable NandFlash */
  65         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  66
  67 }
  68 #endif
  69
  70 #ifdef CONFIG_MACB
  71 static void at91sam9260ek_macb_hw_init(void)
  72 {
  73         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  74         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  75
  76         /* Enable EMAC clock */
  77         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  78
  79         /*
  80          * Disable pull-up on:
  81          *      RXDV (PA17) => PHY normal mode (not Test mode)
  82          *      ERX0 (PA14) => PHY ADDR0
  83          *      ERX1 (PA15) => PHY ADDR1
  84          *      ERX2 (PA25) => PHY ADDR2
  85          *      ERX3 (PA26) => PHY ADDR3
  86          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
  87          *
  88          * PHY has internal pull-down
  89          */
  90         writel(pin_to_mask(AT91_PIN_PA14) |
  91                 pin_to_mask(AT91_PIN_PA15) |
  92                 pin_to_mask(AT91_PIN_PA17) |
  93                 pin_to_mask(AT91_PIN_PA25) |
  94                 pin_to_mask(AT91_PIN_PA26) |
  95                 pin_to_mask(AT91_PIN_PA28),
  96                 &pioa->pudr);
  97
  98         at91_phy_reset();
  99
 100         /* Re-enable pull-up */
 101         writel(pin_to_mask(AT91_PIN_PA14) |
 102                 pin_to_mask(AT91_PIN_PA15) |
 103                 pin_to_mask(AT91_PIN_PA17) |
 104                 pin_to_mask(AT91_PIN_PA25) |
 105                 pin_to_mask(AT91_PIN_PA26) |
 106                 pin_to_mask(AT91_PIN_PA28),
 107                 &pioa->puer);
 108
 109         /* Initialize EMAC=MACB hardware */
 110         at91_macb_hw_init();
 111 }
 112 #endif
 113
 114 #ifdef CONFIG_GENERIC_ATMEL_MCI
 115 int board_mmc_init(bd_t *bd)
 116 {
 117         at91_mci_hw_init();
 118
 119         return atmel_mci_init((void *)ATMEL_BASE_MCI);
 120 }
 121 #endif
 122
 123 int board_early_init_f(void)
 124 {
 125         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 126
 127         /* Enable clocks for all PIOs */
 128         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 129                 (1 << ATMEL_ID_PIOC),
 130                 &pmc->pcer);
 131
 132         return 0;
 133 }
 134
 135 int board_init(void)
 136 {
 137         /* adress of boot parameters */
 138         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 139
 140         at91_seriald_hw_init();
 141 #ifdef CONFIG_CMD_NAND
 142         at91sam9260ek_nand_hw_init();
 143 #endif
 144 #ifdef CONFIG_HAS_DATAFLASH
 145         at91_spi0_hw_init((1 << 0) | (1 << 1));
 146 #endif
 147 #ifdef CONFIG_MACB
 148         at91sam9260ek_macb_hw_init();
 149 #endif
 150
 151         return 0;
 152 }
 153
 154 int dram_init(void)
 155 {
 156         gd->ram_size = get_ram_size(
 157                 (void *)CONFIG_SYS_SDRAM_BASE,
 158                 CONFIG_SYS_SDRAM_SIZE);
 159         return 0;
 160 }
 161
 162 #ifdef CONFIG_RESET_PHY_R
 163 void reset_phy(void)
 164 {
 165 }
 166 #endif
 167
 168 int board_eth_init(bd_t *bis)
 169 {
 170         int rc = 0;
 171 #ifdef CONFIG_MACB
 172         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 173 #endif
 174         return rc;
 175 }