board/atmel/at91sam9261ek/at91sam9261ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/at91sam9261.h>
  28 #include <asm/arch/at91sam9261_matrix.h>
  29 #include <asm/arch/at91sam9_smc.h>
  30 #include <asm/arch/at91_common.h>
  31 #include <asm/arch/at91_pmc.h>
  32 #include <asm/arch/at91_rstc.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/gpio.h>
  35 #include <lcd.h>
  36 #include <atmel_lcdc.h>
  37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  38 #include <net.h>
  39 #include <netdev.h>
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 /* ------------------------------------------------------------------------- */
  45 /*
  46  * Miscelaneous platform dependent initialisations
  47  */
  48
  49 #ifdef CONFIG_CMD_NAND
  50 static void at91sam9261ek_nand_hw_init(void)
  51 {
  52         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  53         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  54         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  55         unsigned long csa;
  56
  57         /* Enable CS3 */
  58         csa = readl(&matrix->ebicsa);
  59         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  60
  61         writel(csa, &matrix->ebicsa);
  62
  63         /* Configure SMC CS3 for NAND/SmartMedia */
  64 #ifdef CONFIG_AT91SAM9G10EK
  65         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  66                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  67                 &smc->cs[3].setup);
  68         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
  69                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
  70                 &smc->cs[3].pulse);
  71         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  72                 &smc->cs[3].cycle);
  73 #else
  74         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  75                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  76                 &smc->cs[3].setup);
  77         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  78                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  79                 &smc->cs[3].pulse);
  80         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  81                 &smc->cs[3].cycle);
  82 #endif
  83         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  84                        AT91_SMC_MODE_EXNW_DISABLE |
  85 #ifdef CONFIG_SYS_NAND_DBW_16
  86                        AT91_SMC_MODE_DBW_16 |
  87 #else /* CONFIG_SYS_NAND_DBW_8 */
  88                        AT91_SMC_MODE_DBW_8 |
  89 #endif
  90                        AT91_SMC_MODE_TDF_CYCLE(2),
  91                        &smc->cs[3].mode);
  92
  93         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  94
  95         /* Configure RDY/BSY */
  96         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  97
  98         /* Enable NandFlash */
  99         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 100
 101         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
 102         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
 103 }
 104 #endif
 105
 106 #ifdef CONFIG_DRIVER_DM9000
 107 static void at91sam9261ek_dm9000_hw_init(void)
 108 {
 109         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 110
 111         /* Configure SMC CS2 for DM9000 */
 112 #ifdef CONFIG_AT91SAM9G10EK
 113         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
 114                 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
 115                 &smc->cs[2].setup);
 116         writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
 117                 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
 118                 &smc->cs[2].pulse);
 119         writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
 120                 &smc->cs[2].cycle);
 121         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 122                        AT91_SMC_MODE_EXNW_DISABLE |
 123                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 124                        AT91_SMC_MODE_TDF_CYCLE(1),
 125                        &smc->cs[2].mode);
 126 #else
 127         writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
 128                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
 129                 &smc->cs[2].setup);
 130         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
 131                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
 132                 &smc->cs[2].pulse);
 133         writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
 134                 &smc->cs[2].cycle);
 135         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 136                        AT91_SMC_MODE_EXNW_DISABLE |
 137                        AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 138                        AT91_SMC_MODE_TDF_CYCLE(1),
 139                        &smc->cs[2].mode);
 140 #endif
 141
 142         /* Configure Reset signal as output */
 143         at91_set_gpio_output(AT91_PIN_PC10, 0);
 144
 145         /* Configure Interrupt pin as input, no pull-up */
 146         at91_set_gpio_input(AT91_PIN_PC11, 0);
 147 }
 148 #endif
 149
 150 #ifdef CONFIG_LCD
 151 vidinfo_t panel_info = {
 152         vl_col:         240,
 153         vl_row:         320,
 154         vl_clk:         4965000,
 155         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 156                         ATMEL_LCDC_INVFRAME_INVERTED,
 157         vl_bpix:        3,
 158         vl_tft:         1,
 159         vl_hsync_len:   5,
 160         vl_left_margin: 1,
 161         vl_right_margin:33,
 162         vl_vsync_len:   1,
 163         vl_upper_margin:1,
 164         vl_lower_margin:0,
 165         mmio:           ATMEL_BASE_LCDC,
 166 };
 167
 168 void lcd_enable(void)
 169 {
 170         at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
 171 }
 172
 173 void lcd_disable(void)
 174 {
 175         at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
 176 }
 177
 178 static void at91sam9261ek_lcd_hw_init(void)
 179 {
 180         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 181
 182         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
 183         at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
 184         at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
 185         at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
 186         at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
 187         at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
 188         at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
 189         at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
 190         at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
 191         at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
 192         at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
 193         at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
 194         at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
 195         at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
 196         at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
 197         at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
 198         at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
 199         at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
 200         at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
 201         at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
 202         at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
 203         at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
 204
 205         writel(AT91_PMC_HCK1, &pmc->scer);
 206
 207         /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
 208 #ifdef CONFIG_AT91SAM9261EK
 209         gd->fb_base = ATMEL_BASE_SRAM;
 210 #endif
 211 }
 212
 213 #ifdef CONFIG_LCD_INFO
 214 #include <nand.h>
 215 #include <version.h>
 216
 217 void lcd_show_board_info(void)
 218 {
 219         ulong dram_size, nand_size;
 220         int i;
 221         char temp[32];
 222
 223         lcd_printf ("%s\n", U_BOOT_VERSION);
 224         lcd_printf ("(C) 2008 ATMEL Corp\n");
 225         lcd_printf ("at91support@atmel.com\n");
 226         lcd_printf ("%s CPU at %s MHz\n",
 227                 ATMEL_CPU_NAME,
 228                 strmhz(temp, get_cpu_clk_rate()));
 229
 230         dram_size = 0;
 231         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 232                 dram_size += gd->bd->bi_dram[i].size;
 233         nand_size = 0;
 234         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 235                 nand_size += nand_info[i].size;
 236         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 237                 dram_size >> 20,
 238                 nand_size >> 20 );
 239 }
 240 #endif /* CONFIG_LCD_INFO */
 241 #endif
 242
 243 int board_init(void)
 244 {
 245         /* Enable Ctrlc */
 246         console_init_f();
 247
 248 #ifdef CONFIG_AT91SAM9G10EK
 249         /* arch number of AT91SAM9G10EK-Board */
 250         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
 251 #else
 252         /* arch number of AT91SAM9261EK-Board */
 253         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 254 #endif
 255         /* adress of boot parameters */
 256         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 257
 258         at91_seriald_hw_init();
 259 #ifdef CONFIG_CMD_NAND
 260         at91sam9261ek_nand_hw_init();
 261 #endif
 262 #ifdef CONFIG_HAS_DATAFLASH
 263         at91_spi0_hw_init(1 << 0);
 264 #endif
 265 #ifdef CONFIG_DRIVER_DM9000
 266         at91sam9261ek_dm9000_hw_init();
 267 #endif
 268 #ifdef CONFIG_LCD
 269         at91sam9261ek_lcd_hw_init();
 270 #endif
 271         return 0;
 272 }
 273
 274 #ifdef CONFIG_DRIVER_DM9000
 275 int board_eth_init(bd_t *bis)
 276 {
 277         return dm9000_initialize(bis);
 278 }
 279 #endif
 280
 281 int dram_init(void)
 282 {
 283         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 284                 CONFIG_SYS_SDRAM_SIZE);
 285
 286         return 0;
 287 }
 288
 289 #ifdef CONFIG_RESET_PHY_R
 290 void reset_phy(void)
 291 {
 292 #ifdef CONFIG_DRIVER_DM9000
 293         /*
 294          * Initialize ethernet HW addr prior to starting Linux,
 295          * needed for nfsroot
 296          */
 297         eth_init(gd->bd);
 298 #endif
 299 }
 300 #endif