board/atmel/at91sam9263ek/at91sam9263ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9263.h>
  27 #include <asm/arch/at91sam9263_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_pmc.h>
  30 #include <asm/arch/at91_rstc.h>
  31 #include <asm/arch/gpio.h>
  32 #include <asm/arch/io.h>
  33 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  34 #include <net.h>
  35 #endif
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 /* ------------------------------------------------------------------------- */
  40 /*
  41  * Miscelaneous platform dependent initialisations
  42  */
  43
  44 static void at91sam9263ek_serial_hw_init(void)
  45 {
  46 #ifdef CONFIG_USART0
  47         at91_set_A_periph(AT91_PIN_PA26, 1);            /* TXD0 */
  48         at91_set_A_periph(AT91_PIN_PA27, 0);            /* RXD0 */
  49         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
  50 #endif
  51
  52 #ifdef CONFIG_USART1
  53         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
  54         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
  55         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
  56 #endif
  57
  58 #ifdef CONFIG_USART2
  59         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
  60         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
  61         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
  62 #endif
  63
  64 #ifdef CONFIG_USART3    /* DBGU */
  65         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
  66         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
  67         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  68 #endif
  69 }
  70
  71 #ifdef CONFIG_CMD_NAND
  72 static void at91sam9263ek_nand_hw_init(void)
  73 {
  74         unsigned long csa;
  75
  76         /* Enable CS3 */
  77         csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
  78         at91_sys_write(AT91_MATRIX_EBI0CSA,
  79                        csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
  80
  81         /* Configure SMC CS3 for NAND/SmartMedia */
  82         at91_sys_write(AT91_SMC_SETUP(3),
  83                        AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
  84                        AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  85         at91_sys_write(AT91_SMC_PULSE(3),
  86                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  87                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  88         at91_sys_write(AT91_SMC_CYCLE(3),
  89                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  90         at91_sys_write(AT91_SMC_MODE(3),
  91                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  92                        AT91_SMC_EXNWMODE_DISABLE |
  93 #ifdef CFG_NAND_DBW_16
  94                        AT91_SMC_DBW_16 |
  95 #else /* CFG_NAND_DBW_8 */
  96                        AT91_SMC_DBW_8 |
  97 #endif
  98                        AT91_SMC_TDF_(2));
  99
 100         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
 101                                       1 << AT91SAM9263_ID_PIOCDE);
 102
 103         /* Configure RDY/BSY */
 104         at91_set_gpio_input(AT91_PIN_PA22, 1);
 105
 106         /* Enable NandFlash */
 107         at91_set_gpio_output(AT91_PIN_PD15, 1);
 108 }
 109 #endif
 110
 111 #ifdef CONFIG_HAS_DATAFLASH
 112 static void at91sam9263ek_spi_hw_init(void)
 113 {
 114         at91_set_B_periph(AT91_PIN_PA5, 0);     /* SPI0_NPCS0 */
 115
 116         at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 117         at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 118         at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 119
 120         /* Enable clock */
 121         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
 122 }
 123 #endif
 124
 125 #ifdef CONFIG_MACB
 126 static void at91sam9263ek_macb_hw_init(void)
 127 {
 128         /* Enable clock */
 129         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
 130
 131         /*
 132          * Disable pull-up on:
 133          *      RXDV (PC25) => PHY normal mode (not Test mode)
 134          *      ERX0 (PE25) => PHY ADDR0
 135          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
 136          *
 137          * PHY has internal pull-down
 138          */
 139         writel(pin_to_mask(AT91_PIN_PC25),
 140                pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
 141         writel(pin_to_mask(AT91_PIN_PE25) |
 142                pin_to_mask(AT91_PIN_PE26),
 143                pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
 144
 145         /* Need to reset PHY -> 500ms reset */
 146         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 147                                      AT91_RSTC_ERSTL | (0x0D << 8) |
 148                                      AT91_RSTC_URSTEN);
 149
 150         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 151
 152         /* Wait for end hardware reset */
 153         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 154
 155         /* Re-enable pull-up */
 156         writel(pin_to_mask(AT91_PIN_PC25),
 157                pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
 158         writel(pin_to_mask(AT91_PIN_PE25) |
 159                pin_to_mask(AT91_PIN_PE26),
 160                pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
 161
 162         at91_set_A_periph(AT91_PIN_PE21, 0);    /* ETXCK_EREFCK */
 163         at91_set_B_periph(AT91_PIN_PC25, 0);    /* ERXDV */
 164         at91_set_A_periph(AT91_PIN_PE25, 0);    /* ERX0 */
 165         at91_set_A_periph(AT91_PIN_PE26, 0);    /* ERX1 */
 166         at91_set_A_periph(AT91_PIN_PE27, 0);    /* ERXER */
 167         at91_set_A_periph(AT91_PIN_PE28, 0);    /* ETXEN */
 168         at91_set_A_periph(AT91_PIN_PE23, 0);    /* ETX0 */
 169         at91_set_A_periph(AT91_PIN_PE24, 0);    /* ETX1 */
 170         at91_set_A_periph(AT91_PIN_PE30, 0);    /* EMDIO */
 171         at91_set_A_periph(AT91_PIN_PE29, 0);    /* EMDC */
 172
 173 #ifndef CONFIG_RMII
 174         at91_set_A_periph(AT91_PIN_PE22, 0);    /* ECRS */
 175         at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
 176         at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
 177         at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
 178         at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
 179         at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
 180         at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
 181         at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
 182 #endif
 183
 184 }
 185 #endif
 186
 187 #ifdef CONFIG_USB_OHCI_NEW
 188 static void at91sam9263ek_uhp_hw_init(void)
 189 {
 190         /* Enable VBus on UHP ports */
 191         at91_set_gpio_output(AT91_PIN_PA21, 0);
 192         at91_set_gpio_output(AT91_PIN_PA24, 0);
 193 }
 194 #endif
 195
 196 int board_init(void)
 197 {
 198         /* Enable Ctrlc */
 199         console_init_f();
 200
 201         /* arch number of AT91SAM9263EK-Board */
 202         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 203         /* adress of boot parameters */
 204         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 205
 206         at91sam9263ek_serial_hw_init();
 207 #ifdef CONFIG_CMD_NAND
 208         at91sam9263ek_nand_hw_init();
 209 #endif
 210 #ifdef CONFIG_HAS_DATAFLASH
 211         at91sam9263ek_spi_hw_init();
 212 #endif
 213 #ifdef CONFIG_MACB
 214         at91sam9263ek_macb_hw_init();
 215 #endif
 216 #ifdef CONFIG_USB_OHCI_NEW
 217         at91sam9263ek_uhp_hw_init();
 218 #endif
 219         return 0;
 220 }
 221
 222 int dram_init(void)
 223 {
 224         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 225         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 226         return 0;
 227 }
 228
 229 #ifdef CONFIG_RESET_PHY_R
 230 void reset_phy(void)
 231 {
 232 #ifdef CONFIG_MACB
 233         /*
 234          * Initialize ethernet HW addr prior to starting Linux,
 235          * needed for nfsroot
 236          */
 237         eth_init(gd->bd);
 238 #endif
 239 }
 240 #endif