board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/sizes.h>
  27 #include <asm/arch/at91sam9g45.h>
  28 #include <asm/arch/at91sam9_matrix.h>
  29 #include <asm/arch/at91sam9_smc.h>
  30 #include <asm/arch/at91_common.h>
  31 #include <asm/arch/at91_pmc.h>
  32 #include <asm/arch/at91_rstc.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/gpio.h>
  35 #include <asm/arch/io.h>
  36 #include <asm/arch/hardware.h>
  37 #include <lcd.h>
  38 #include <atmel_lcdc.h>
  39 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  40 #include <net.h>
  41 #endif
  42 #include <netdev.h>
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* ------------------------------------------------------------------------- */
  47 /*
  48  * Miscelaneous platform dependent initialisations
  49  */
  50
  51 #ifdef CONFIG_CMD_NAND
  52 static void at91sam9m10g45ek_nand_hw_init(void)
  53 {
  54         unsigned long csa;
  55
  56         /* Enable CS3 */
  57         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  58         at91_sys_write(AT91_MATRIX_EBICSA,
  59                        csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
  60
  61         /* Configure SMC CS3 for NAND/SmartMedia */
  62         at91_sys_write(AT91_SMC_SETUP(3),
  63                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  64                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  65         at91_sys_write(AT91_SMC_PULSE(3),
  66                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
  67                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
  68         at91_sys_write(AT91_SMC_CYCLE(3),
  69                        AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
  70         at91_sys_write(AT91_SMC_MODE(3),
  71                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  72                        AT91_SMC_EXNWMODE_DISABLE |
  73 #ifdef CONFIG_SYS_NAND_DBW_16
  74                        AT91_SMC_DBW_16 |
  75 #else /* CONFIG_SYS_NAND_DBW_8 */
  76                        AT91_SMC_DBW_8 |
  77 #endif
  78                        AT91_SMC_TDF_(3));
  79
  80         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
  81
  82         /* Configure RDY/BSY */
  83         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  84
  85         /* Enable NandFlash */
  86         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  87 }
  88 #endif
  89
  90 #ifdef CONFIG_CMD_USB
  91 static void at91sam9m10g45ek_usb_hw_init(void)
  92 {
  93         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
  94
  95         at91_set_gpio_output(AT91_PIN_PD1, 0);
  96         at91_set_gpio_output(AT91_PIN_PD3, 0);
  97 }
  98 #endif
  99
 100 #ifdef CONFIG_MACB
 101 static void at91sam9m10g45ek_macb_hw_init(void)
 102 {
 103         unsigned long rstc;
 104
 105         /* Enable clock */
 106         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
 107
 108         /*
 109          * Disable pull-up on:
 110          *      RXDV (PA15) => PHY normal mode (not Test mode)
 111          *      ERX0 (PA12) => PHY ADDR0
 112          *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
 113          *
 114          * PHY has internal pull-down
 115          */
 116         writel(pin_to_mask(AT91_PIN_PA15) |
 117                pin_to_mask(AT91_PIN_PA12) |
 118                pin_to_mask(AT91_PIN_PA13),
 119                pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 120
 121         rstc = at91_sys_read(AT91_RSTC_MR);
 122
 123         /* Need to reset PHY -> 500ms reset */
 124         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 125                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
 126                                      AT91_RSTC_URSTEN);
 127
 128         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 129
 130         /* Wait for end hardware reset */
 131         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 132
 133         /* Restore NRST value */
 134         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 135                                      (rstc) |
 136                                      AT91_RSTC_URSTEN);
 137
 138         /* Re-enable pull-up */
 139         writel(pin_to_mask(AT91_PIN_PA15) |
 140                pin_to_mask(AT91_PIN_PA12) |
 141                pin_to_mask(AT91_PIN_PA13),
 142                pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 143
 144         at91_macb_hw_init();
 145 }
 146 #endif
 147
 148 #ifdef CONFIG_LCD
 149
 150 vidinfo_t panel_info = {
 151         vl_col:         480,
 152         vl_row:         272,
 153         vl_clk:         9000000,
 154         vl_sync:        ATMEL_LCDC_INVLINE_NORMAL |
 155                         ATMEL_LCDC_INVFRAME_NORMAL,
 156         vl_bpix:        3,
 157         vl_tft:         1,
 158         vl_hsync_len:   45,
 159         vl_left_margin: 1,
 160         vl_right_margin:1,
 161         vl_vsync_len:   1,
 162         vl_upper_margin:40,
 163         vl_lower_margin:1,
 164         mmio:           AT91SAM9G45_LCDC_BASE,
 165 };
 166
 167
 168 void lcd_enable(void)
 169 {
 170         at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 171 }
 172
 173 void lcd_disable(void)
 174 {
 175         at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 176 }
 177
 178 static void at91sam9m10g45ek_lcd_hw_init(void)
 179 {
 180         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 181         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 182         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 183         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 184         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 185
 186         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 187         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 188         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 189         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 190         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 191         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 192         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 193         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 194         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 195         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 196         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 197         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 198         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 199         at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 200         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 201         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 202         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 203         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 204         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 205         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 206         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 207         at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 208         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 209         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 210
 211         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
 212
 213         gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 214 }
 215
 216 #ifdef CONFIG_LCD_INFO
 217 #include <nand.h>
 218 #include <version.h>
 219
 220 void lcd_show_board_info(void)
 221 {
 222         ulong dram_size, nand_size;
 223         int i;
 224         char temp[32];
 225
 226         lcd_printf ("%s\n", U_BOOT_VERSION);
 227         lcd_printf ("(C) 2008 ATMEL Corp\n");
 228         lcd_printf ("at91support@atmel.com\n");
 229         lcd_printf ("%s CPU at %s MHz\n",
 230                 CONFIG_SYS_AT91_CPU_NAME,
 231                 strmhz(temp, get_cpu_clk_rate()));
 232
 233         dram_size = 0;
 234         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 235                 dram_size += gd->bd->bi_dram[i].size;
 236         nand_size = 0;
 237         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 238                 nand_size += nand_info[i].size;
 239         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 240                 dram_size >> 20,
 241                 nand_size >> 20 );
 242 }
 243 #endif /* CONFIG_LCD_INFO */
 244 #endif
 245
 246 int board_init(void)
 247 {
 248         /* Enable Ctrlc */
 249         console_init_f();
 250
 251         /* arch number of AT91SAM9M10G45EK-Board */
 252 #ifdef CONFIG_AT91SAM9M10G45EK
 253         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
 254 #elif defined CONFIG_AT91SAM9G45EKES
 255         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
 256 #endif
 257         /* adress of boot parameters */
 258         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 259
 260         at91_serial_hw_init();
 261 #ifdef CONFIG_CMD_NAND
 262         at91sam9m10g45ek_nand_hw_init();
 263 #endif
 264 #ifdef CONFIG_CMD_USB
 265         at91sam9m10g45ek_usb_hw_init();
 266 #endif
 267 #ifdef CONFIG_HAS_DATAFLASH
 268         at91_spi0_hw_init(1 << 0);
 269 #endif
 270 #ifdef CONFIG_ATMEL_SPI
 271         at91_spi0_hw_init(1 << 4);
 272 #endif
 273
 274 #ifdef CONFIG_MACB
 275         at91sam9m10g45ek_macb_hw_init();
 276 #endif
 277
 278 #ifdef CONFIG_LCD
 279         at91sam9m10g45ek_lcd_hw_init();
 280 #endif
 281         return 0;
 282 }
 283
 284 int dram_init(void)
 285 {
 286         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 287         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 288         return 0;
 289 }
 290
 291 #ifdef CONFIG_RESET_PHY_R
 292 void reset_phy(void)
 293 {
 294 }
 295 #endif
 296
 297 int board_eth_init(bd_t *bis)
 298 {
 299         int rc = 0;
 300 #ifdef CONFIG_MACB
 301         rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
 302 #endif
 303         return rc;
 304 }
 305
 306 /* SPI chip select control */
 307 #ifdef CONFIG_ATMEL_SPI
 308 #include <spi.h>
 309
 310 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 311 {
 312         return bus == 0 && cs < 2;
 313 }
 314
 315 void spi_cs_activate(struct spi_slave *slave)
 316 {
 317         switch(slave->cs) {
 318                 case 1:
 319                         at91_set_gpio_output(AT91_PIN_PB18, 0);
 320                         break;
 321                 case 0:
 322                 default:
 323                         at91_set_gpio_output(AT91_PIN_PB3, 0);
 324                         break;
 325         }
 326 }
 327
 328 void spi_cs_deactivate(struct spi_slave *slave)
 329 {
 330         switch(slave->cs) {
 331                 case 1:
 332                         at91_set_gpio_output(AT91_PIN_PB18, 1);
 333                         break;
 334                 case 0:
 335                 default:
 336                         at91_set_gpio_output(AT91_PIN_PB3, 1);
 337                 break;
 338         }
 339 }
 340 #endif /* CONFIG_ATMEL_SPI */