board/atmel/at91sam9rlek/at91sam9rlek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/at91sam9rl.h>
  28 #include <asm/arch/at91sam9rl_matrix.h>
  29 #include <asm/arch/at91sam9_smc.h>
  30 #include <asm/arch/at91_common.h>
  31 #include <asm/arch/at91_pmc.h>
  32 #include <asm/arch/at91_rstc.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/gpio.h>
  35
  36 #include <lcd.h>
  37 #include <atmel_lcdc.h>
  38 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  39 #include <net.h>
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 /* ------------------------------------------------------------------------- */
  45 /*
  46  * Miscelaneous platform dependent initialisations
  47  */
  48
  49 #ifdef CONFIG_CMD_NAND
  50 static void at91sam9rlek_nand_hw_init(void)
  51 {
  52         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  53         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  54         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  55         unsigned long csa;
  56
  57         /* Enable CS3 */
  58         csa = readl(&matrix->ebicsa);
  59         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  60
  61         writel(csa, &matrix->ebicsa);
  62
  63         /* Configure SMC CS3 for NAND/SmartMedia */
  64         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  65                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  66                 &smc->cs[3].setup);
  67         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  68                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  69                 &smc->cs[3].pulse);
  70         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  71                 &smc->cs[3].cycle);
  72         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  73                 AT91_SMC_MODE_EXNW_DISABLE |
  74 #ifdef CONFIG_SYS_NAND_DBW_16
  75                 AT91_SMC_MODE_DBW_16 |
  76 #else /* CONFIG_SYS_NAND_DBW_8 */
  77                 AT91_SMC_MODE_DBW_8 |
  78 #endif
  79                 AT91_SMC_MODE_TDF_CYCLE(2),
  80                 &smc->cs[3].mode);
  81
  82         writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
  83
  84         /* Configure RDY/BSY */
  85         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  86
  87         /* Enable NandFlash */
  88         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  89
  90         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
  91         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
  92 }
  93 #endif
  94
  95 #ifdef CONFIG_LCD
  96 vidinfo_t panel_info = {
  97         vl_col:         240,
  98         vl_row:         320,
  99         vl_clk:         4965000,
 100         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 101                         ATMEL_LCDC_INVFRAME_INVERTED,
 102         vl_bpix:        3,
 103         vl_tft:         1,
 104         vl_hsync_len:   5,
 105         vl_left_margin: 1,
 106         vl_right_margin:33,
 107         vl_vsync_len:   1,
 108         vl_upper_margin:1,
 109         vl_lower_margin:0,
 110         mmio:           ATMEL_BASE_LCDC,
 111 };
 112
 113 void lcd_enable(void)
 114 {
 115         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
 116 }
 117
 118 void lcd_disable(void)
 119 {
 120         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
 121 }
 122 static void at91sam9rlek_lcd_hw_init(void)
 123 {
 124         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 125
 126         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 127         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 128         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 129         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 130         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 131         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 132         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 133         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 134         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 135         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 136         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 137         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 138         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 139         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 140         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 141         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 142         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 143         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 144         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 145         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 146         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 147
 148         writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 149 }
 150
 151 #ifdef CONFIG_LCD_INFO
 152 #include <nand.h>
 153 #include <version.h>
 154
 155 void lcd_show_board_info(void)
 156 {
 157         ulong dram_size, nand_size;
 158         int i;
 159         char temp[32];
 160
 161         lcd_printf ("%s\n", U_BOOT_VERSION);
 162         lcd_printf ("(C) 2008 ATMEL Corp\n");
 163         lcd_printf ("at91support@atmel.com\n");
 164         lcd_printf ("%s CPU at %s MHz\n",
 165                 ATMEL_CPU_NAME,
 166                 strmhz(temp, get_cpu_clk_rate()));
 167
 168         dram_size = 0;
 169         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 170                 dram_size += gd->bd->bi_dram[i].size;
 171         nand_size = 0;
 172         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 173                 nand_size += nand_info[i].size;
 174         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 175                 dram_size >> 20,
 176                 nand_size >> 20 );
 177 }
 178 #endif /* CONFIG_LCD_INFO */
 179 #endif
 180
 181 int board_early_init_f(void)
 182 {
 183         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 184
 185         /* Enable clocks for all PIOs */
 186         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 187                 (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
 188                 &pmc->pcer);
 189
 190         return 0;
 191 }
 192
 193 int board_init(void)
 194 {
 195         /* Enable Ctrlc */
 196         console_init_f();
 197
 198         /* arch number of AT91SAM9RLEK-Board */
 199         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 200         /* adress of boot parameters */
 201         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 202
 203         at91_seriald_hw_init();
 204 #ifdef CONFIG_CMD_NAND
 205         at91sam9rlek_nand_hw_init();
 206 #endif
 207 #ifdef CONFIG_HAS_DATAFLASH
 208         at91_spi0_hw_init(1 << 0);
 209 #endif
 210 #ifdef CONFIG_LCD
 211         at91sam9rlek_lcd_hw_init();
 212 #endif
 213         return 0;
 214 }
 215
 216 int dram_init(void)
 217 {
 218         gd->ram_size = get_ram_size(
 219                 (void *)CONFIG_SYS_SDRAM_BASE,
 220                 CONFIG_SYS_SDRAM_SIZE);
 221         return 0;
 222 }