ot1200: add sata support
[karo-tx-uboot.git] / board / bachmann / ot1200 / ot1200.c
1 /*
2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3  * Copyright (C) 2014, Bachmann electronic GmbH
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <malloc.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/imx-common/iomux-v3.h>
15 #include <asm/imx-common/sata.h>
16 #include <asm/imx-common/mxc_i2c.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/arch/crm_regs.h>
19 #include <mmc.h>
20 #include <fsl_esdhc.h>
21 #include <netdev.h>
22 #include <i2c.h>
23 #include <pca953x.h>
24 #include <asm/gpio.h>
25 #include <phy.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 #define OUTPUT_40OHM    (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
30
31 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP |                  \
32         OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33
34 #define USDHC_PAD_CTRL  (PAD_CTL_PUS_47K_UP |                   \
35         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
36         PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38 #define ENET_PAD_CTRL   (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
39         PAD_CTL_HYS)
40
41 #define SPI_PAD_CTRL    (PAD_CTL_HYS | OUTPUT_40OHM |           \
42         PAD_CTL_SRE_FAST)
43
44 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
45         PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
46
47 int dram_init(void)
48 {
49         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
50
51         return 0;
52 }
53
54 static iomux_v3_cfg_t const uart1_pads[] = {
55         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
57 };
58
59 static void setup_iomux_uart(void)
60 {
61         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
62 }
63
64 static iomux_v3_cfg_t const enet_pads[] = {
65         MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
66         MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
67         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
68         MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
69         MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
70         MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
71         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73         MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74         MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
76         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
77         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79         MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80         MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81         MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 };
83
84 static void setup_iomux_enet(void)
85 {
86         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
87 }
88
89 static iomux_v3_cfg_t const ecspi1_pads[] = {
90         MX6_PAD_DISP0_DAT3__ECSPI3_SS0  | MUX_PAD_CTRL(SPI_PAD_CTRL),
91         MX6_PAD_DISP0_DAT4__ECSPI3_SS1  | MUX_PAD_CTRL(SPI_PAD_CTRL),
92         MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
93         MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
94         MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
95 };
96
97 static void setup_iomux_spi(void)
98 {
99         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
100 }
101
102 int board_spi_cs_gpio(unsigned bus, unsigned cs)
103 {
104         return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
105 }
106
107 int board_early_init_f(void)
108 {
109         setup_iomux_uart();
110         setup_iomux_spi();
111
112         return 0;
113 }
114
115 static iomux_v3_cfg_t const usdhc3_pads[] = {
116         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 };
128
129 int board_mmc_getcd(struct mmc *mmc)
130 {
131         return 1;
132 }
133
134 struct fsl_esdhc_cfg usdhc_cfg[] = {
135         {USDHC3_BASE_ADDR},
136 };
137
138 int board_mmc_init(bd_t *bis)
139 {
140         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
141         usdhc_cfg[0].max_bus_width = 8;
142
143         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
144
145         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
146 }
147
148 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
149
150 /* I2C3 - IO expander  */
151 static struct i2c_pads_info i2c_pad_info2 = {
152         .scl = {
153                 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
154                 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
155                 .gp = IMX_GPIO_NR(3, 17)
156         },
157         .sda = {
158                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
159                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
160                 .gp = IMX_GPIO_NR(3, 18)
161         }
162 };
163
164 static iomux_v3_cfg_t const pwm_pad[] = {
165         MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
166 };
167
168 static void leds_on(void)
169 {
170         /* turn on all possible leds connected via GPIO expander */
171         i2c_set_bus_num(2);
172         pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
173         pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
174 }
175
176 static void backlight_lcd_off(void)
177 {
178         unsigned gpio = IMX_GPIO_NR(2, 0);
179         gpio_direction_output(gpio, 0);
180
181         gpio = IMX_GPIO_NR(2, 3);
182         gpio_direction_output(gpio, 0);
183 }
184
185 int board_eth_init(bd_t *bis)
186 {
187         uint32_t base = IMX_FEC_BASE;
188         struct mii_dev *bus = NULL;
189         struct phy_device *phydev = NULL;
190         int ret;
191
192         setup_iomux_enet();
193
194         bus = fec_get_miibus(base, -1);
195         if (!bus)
196                 return 0;
197
198         /* scan phy 0 and 5 */
199         phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
200         if (!phydev) {
201                 free(bus);
202                 return 0;
203         }
204
205         /* depending on the phy address we can detect our board version */
206         if (phydev->addr == 0)
207                 setenv("boardver", "");
208         else
209                 setenv("boardver", "mr");
210
211         printf("using phy at %d\n", phydev->addr);
212         ret = fec_probe(bis, -1, base, bus, phydev);
213         if (ret) {
214                 printf("FEC MXC: %s:failed\n", __func__);
215                 free(phydev);
216                 free(bus);
217         }
218         return 0;
219 }
220
221 int board_init(void)
222 {
223         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
224
225         backlight_lcd_off();
226
227         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
228
229         leds_on();
230
231         /* enable ecspi3 clocks */
232         enable_cspi_clock(1, 2);
233
234 #ifdef CONFIG_CMD_SATA
235         setup_sata();
236 #endif
237
238         return 0;
239 }
240
241 int checkboard(void)
242 {
243         puts("Board: "CONFIG_SYS_BOARD"\n");
244         return 0;
245 }
246
247 #ifdef CONFIG_CMD_BMODE
248 static const struct boot_mode board_boot_modes[] = {
249         /* 4 bit bus width */
250         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
251         {NULL,          0},
252 };
253 #endif
254
255 int misc_init_r(void)
256 {
257 #ifdef CONFIG_CMD_BMODE
258         add_board_boot_modes(board_boot_modes);
259 #endif
260         return 0;
261 }