board/balloon3/balloon3.c

   1 /*
   2  * Balloon3 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/pxa.h>
  12 #include <serial.h>
  13 #include <asm/io.h>
  14 #include <spartan3.h>
  15 #include <command.h>
  16 #include <usb.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 void balloon3_init_fpga(void);
  21
  22 /*
  23  * Miscelaneous platform dependent initialisations
  24  */
  25
  26 int board_init(void)
  27 {
  28         /* We have RAM, disable cache */
  29         dcache_disable();
  30         icache_disable();
  31
  32         /* arch number of vpac270 */
  33         gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
  34
  35         /* adress of boot parameters */
  36         gd->bd->bi_boot_params = 0xa0000100;
  37
  38         /* Init the FPGA */
  39         balloon3_init_fpga();
  40
  41         return 0;
  42 }
  43
  44 int dram_init(void)
  45 {
  46         pxa2xx_dram_init();
  47         gd->ram_size = PHYS_SDRAM_1_SIZE;
  48         return 0;
  49 }
  50
  51 void dram_init_banksize(void)
  52 {
  53         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  54         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  55         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
  56
  57         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  58         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  59         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  60 }
  61
  62 #ifdef  CONFIG_CMD_USB
  63 int board_usb_init(int index, enum usb_init_type init)
  64 {
  65         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  66                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  67                 UHCHR);
  68
  69         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  70
  71         while (readl(UHCHR) & UHCHR_FSBIR)
  72                 ;
  73
  74         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  75         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  76
  77         /* Clear any OTG Pin Hold */
  78         if (readl(PSSR) & PSSR_OTGPH)
  79                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  80
  81         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  82         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  83
  84         /* Set port power control mask bits, only 3 ports. */
  85         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  86
  87         /* enable port 2 */
  88         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  89                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  90
  91         return 0;
  92 }
  93
  94 int board_usb_cleanup(int index, enum usb_init_type init)
  95 {
  96         return 0;
  97 }
  98
  99 void usb_board_stop(void)
 100 {
 101         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 102         udelay(11);
 103         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 104
 105         writel(readl(UHCCOMS) | 1, UHCCOMS);
 106         udelay(10);
 107
 108         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 109
 110         return;
 111 }
 112 #endif
 113
 114 #if defined(CONFIG_FPGA)
 115 /* Toggle GPIO103 and GPIO104 --  PROGB and RDnWR */
 116 int fpga_pgm_fn(int nassert, int nflush, int cookie)
 117 {
 118         if (nassert)
 119                 writel(0x80, GPCR3);
 120         else
 121                 writel(0x80, GPSR3);
 122         if (nflush)
 123                 writel(0x100, GPCR3);
 124         else
 125                 writel(0x100, GPSR3);
 126         return nassert;
 127 }
 128
 129 /* Check GPIO83 -- INITB */
 130 int fpga_init_fn(int cookie)
 131 {
 132         return !(readl(GPLR2) & 0x80000);
 133 }
 134
 135 /* Check GPIO84 -- BUSY */
 136 int fpga_busy_fn(int cookie)
 137 {
 138         return !(readl(GPLR2) & 0x100000);
 139 }
 140
 141 /* Check GPIO111 -- DONE */
 142 int fpga_done_fn(int cookie)
 143 {
 144         return readl(GPLR3) & 0x8000;
 145 }
 146
 147 /* Configure GPIO104 as GPIO and deassert it */
 148 int fpga_pre_config_fn(int cookie)
 149 {
 150         writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
 151         writel(0x100, GPCR3);
 152         return 0;
 153 }
 154
 155 /* Configure GPIO104 as nSKTSEL */
 156 int fpga_post_config_fn(int cookie)
 157 {
 158         writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
 159         return 0;
 160 }
 161
 162 /* Toggle RDnWR */
 163 int fpga_wr_fn(int nassert_write, int flush, int cookie)
 164 {
 165         udelay(1000);
 166
 167         if (nassert_write)
 168                 writel(0x100, GPCR3);
 169         else
 170                 writel(0x100, GPSR3);
 171
 172         return nassert_write;
 173 }
 174
 175 /* Write program to the FPGA */
 176 int fpga_wdata_fn(uchar data, int flush, int cookie)
 177 {
 178         writeb(data, 0x10f00000);
 179         return 0;
 180 }
 181
 182 /* Toggle Clock pin -- NO-OP */
 183 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 184 {
 185         return assert_clk;
 186 }
 187
 188 /* Toggle ChipSelect pin -- NO-OP */
 189 int fpga_cs_fn(int assert_clk, int flush, int cookie)
 190 {
 191         return assert_clk;
 192 }
 193
 194 xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
 195         fpga_pre_config_fn,
 196         fpga_pgm_fn,
 197         fpga_init_fn,
 198         NULL,   /* err */
 199         fpga_done_fn,
 200         fpga_clk_fn,
 201         fpga_cs_fn,
 202         fpga_wr_fn,
 203         NULL,   /* rdata */
 204         fpga_wdata_fn,
 205         fpga_busy_fn,
 206         NULL,   /* abort */
 207         fpga_post_config_fn,
 208 };
 209
 210 xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
 211                         (void *)&balloon3_fpga_fns, 0);
 212
 213 /* Initialize the FPGA */
 214 void balloon3_init_fpga(void)
 215 {
 216         fpga_init();
 217         fpga_add(fpga_xilinx, &fpga);
 218 }
 219 #else
 220 void balloon3_init_fpga(void) {}
 221 #endif /* CONFIG_FPGA */