board/bluewater/snapper9260/snapper9260.c

   1 /*
   2  * Bluewater Systems Snapper 9260/9G20 modules
   3  *
   4  * (C) Copyright 2011 Bluewater Systems
   5  *   Author: Andre Renaud <andre@bluewatersys.com>
   6  *   Author: Ryan Mallon <ryan@bluewatersys.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/at91sam9260_matrix.h>
  14 #include <asm/arch/at91sam9_smc.h>
  15 #include <asm/arch/at91_common.h>
  16 #include <asm/arch/at91_pmc.h>
  17 #include <asm/arch/gpio.h>
  18 #include <net.h>
  19 #include <netdev.h>
  20 #include <i2c.h>
  21 #include <pca953x.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /* IO Expander pins */
  26 #define IO_EXP_ETH_RESET        (0 << 1)
  27 #define IO_EXP_ETH_POWER        (1 << 1)
  28
  29 static void macb_hw_init(void)
  30 {
  31         struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
  32         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  33
  34         /* Enable clock */
  35         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  36
  37         /* Disable pull-ups to prevent PHY going into test mode */
  38         writel(pin_to_mask(AT91_PIN_PA14) |
  39                pin_to_mask(AT91_PIN_PA15) |
  40                pin_to_mask(AT91_PIN_PA18),
  41                &pioa->pudr);
  42
  43         /* Power down ethernet */
  44         pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
  45         pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
  46
  47         /* Hold ethernet in reset */
  48         pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
  49         pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
  50
  51         /* Enable ethernet power */
  52         pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
  53
  54         at91_phy_reset();
  55
  56         /* Bring the ethernet out of reset */
  57         pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
  58
  59         /* The phy internal reset take 21ms */
  60         udelay(21 * 1000);
  61
  62         /* Re-enable pull-up */
  63         writel(pin_to_mask(AT91_PIN_PA14) |
  64                pin_to_mask(AT91_PIN_PA15) |
  65                pin_to_mask(AT91_PIN_PA18),
  66                &pioa->puer);
  67
  68         at91_macb_hw_init();
  69 }
  70
  71 static void nand_hw_init(void)
  72 {
  73         struct at91_smc *smc       = (struct at91_smc    *)ATMEL_BASE_SMC;
  74         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  75         unsigned long csa;
  76
  77         /* Enable CS3 as NAND/SmartMedia */
  78         csa = readl(&matrix->ebicsa);
  79         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  80         writel(csa, &matrix->ebicsa);
  81
  82         /* Configure SMC CS3 for NAND/SmartMedia */
  83         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  84                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  85                &smc->cs[3].setup);
  86         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
  87                AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  88                &smc->cs[3].pulse);
  89         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  90                &smc->cs[3].cycle);
  91         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  92                AT91_SMC_MODE_EXNW_DISABLE |
  93                AT91_SMC_MODE_DBW_8 |
  94                AT91_SMC_MODE_TDF_CYCLE(3),
  95                &smc->cs[3].mode);
  96
  97         /* Configure RDY/BSY */
  98         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  99
 100         /* Enable NandFlash */
 101         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 102 }
 103
 104 int board_init(void)
 105 {
 106         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 107
 108         /* Enable PIO clocks */
 109         writel((1 << ATMEL_ID_PIOA) |
 110                (1 << ATMEL_ID_PIOB) |
 111                (1 << ATMEL_ID_PIOC), &pmc->pcer);
 112
 113         /* The mach-type is the same for both Snapper 9260 and 9G20 */
 114         gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
 115
 116         /* Address of boot parameters */
 117         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 118
 119         /* Initialise peripherals */
 120         at91_seriald_hw_init();
 121         i2c_set_bus_num(0);
 122         nand_hw_init();
 123         macb_hw_init();
 124
 125         return 0;
 126 }
 127
 128 int board_eth_init(bd_t *bis)
 129 {
 130         return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
 131 }
 132
 133 int dram_init(void)
 134 {
 135         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 136                                     CONFIG_SYS_SDRAM_SIZE);
 137         return 0;
 138 }
 139
 140 void reset_phy(void)
 141 {
 142 }