board/boundary/nitrogen6x/nitrogen6x.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/iomux.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <malloc.h>
  31 #include <asm/arch/mx6-pins.h>
  32 #include <asm/errno.h>
  33 #include <asm/gpio.h>
  34 #include <asm/imx-common/iomux-v3.h>
  35 #include <asm/imx-common/mxc_i2c.h>
  36 #include <asm/imx-common/boot_mode.h>
  37 #include <mmc.h>
  38 #include <fsl_esdhc.h>
  39 #include <micrel.h>
  40 #include <miiphy.h>
  41 #include <netdev.h>
  42 #include <linux/fb.h>
  43 #include <ipu_pixfmt.h>
  44 #include <asm/arch/crm_regs.h>
  45 #include <asm/arch/mxc_hdmi.h>
  46 #include <i2c.h>
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  52         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  55         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  56         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  57
  58 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  60
  61 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  62         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  63
  64 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  65         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  66
  67 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  68         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  69         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  70
  71 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  72         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  73         PAD_CTL_SRE_SLOW)
  74
  75 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  76         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  77         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  78
  79 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  80
  81 int dram_init(void)
  82 {
  83         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  84
  85         return 0;
  86 }
  87
  88 iomux_v3_cfg_t const uart1_pads[] = {
  89         MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  90         MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  91 };
  92
  93 iomux_v3_cfg_t const uart2_pads[] = {
  94         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  95         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  96 };
  97
  98 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  99
 100 /* I2C1, SGTL5000 */
 101 struct i2c_pads_info i2c_pad_info0 = {
 102         .scl = {
 103                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
 104                 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
 105                 .gp = IMX_GPIO_NR(3, 21)
 106         },
 107         .sda = {
 108                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
 109                 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
 110                 .gp = IMX_GPIO_NR(3, 28)
 111         }
 112 };
 113
 114 /* I2C2 Camera, MIPI */
 115 struct i2c_pads_info i2c_pad_info1 = {
 116         .scl = {
 117                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 118                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
 119                 .gp = IMX_GPIO_NR(4, 12)
 120         },
 121         .sda = {
 122                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 123                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
 124                 .gp = IMX_GPIO_NR(4, 13)
 125         }
 126 };
 127
 128 /* I2C3, J15 - RGB connector */
 129 struct i2c_pads_info i2c_pad_info2 = {
 130         .scl = {
 131                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 132                 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
 133                 .gp = IMX_GPIO_NR(1, 5)
 134         },
 135         .sda = {
 136                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 137                 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
 138                 .gp = IMX_GPIO_NR(7, 11)
 139         }
 140 };
 141
 142 iomux_v3_cfg_t const usdhc3_pads[] = {
 143         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 150 };
 151
 152 iomux_v3_cfg_t const usdhc4_pads[] = {
 153         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159         MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 160 };
 161
 162 iomux_v3_cfg_t const enet_pads1[] = {
 163         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172         /* pin 35 - 1 (PHY_AD2) on reset */
 173         MX6_PAD_RGMII_RXC__GPIO_6_30            | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         /* pin 32 - 1 - (MODE0) all */
 175         MX6_PAD_RGMII_RD0__GPIO_6_25            | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         /* pin 31 - 1 - (MODE1) all */
 177         MX6_PAD_RGMII_RD1__GPIO_6_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 178         /* pin 28 - 1 - (MODE2) all */
 179         MX6_PAD_RGMII_RD2__GPIO_6_28            | MUX_PAD_CTRL(NO_PAD_CTRL),
 180         /* pin 27 - 1 - (MODE3) all */
 181         MX6_PAD_RGMII_RD3__GPIO_6_29            | MUX_PAD_CTRL(NO_PAD_CTRL),
 182         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 183         MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
 184         /* pin 42 PHY nRST */
 185         MX6_PAD_EIM_D23__GPIO_3_23              | MUX_PAD_CTRL(NO_PAD_CTRL),
 186         MX6_PAD_ENET_RXD0__GPIO_1_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 187 };
 188
 189 iomux_v3_cfg_t const enet_pads2[] = {
 190         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 191         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 192         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 193         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 194         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 195         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 196 };
 197
 198 /* wl1271 pads on nitrogen6x */
 199 iomux_v3_cfg_t const wl12xx_pads[] = {
 200         (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
 201                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 202         (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
 203                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 204         (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
 205                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 206 };
 207 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 208 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 209 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 210
 211 /* Button assignments for J14 */
 212 static iomux_v3_cfg_t const button_pads[] = {
 213         /* Menu */
 214         MX6_PAD_NANDF_D1__GPIO_2_1      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 215         /* Back */
 216         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 217         /* Labelled Search (mapped to Power under Android) */
 218         MX6_PAD_NANDF_D3__GPIO_2_3      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 219         /* Home */
 220         MX6_PAD_NANDF_D4__GPIO_2_4      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 221         /* Volume Down */
 222         MX6_PAD_GPIO_19__GPIO_4_5       | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 223         /* Volume Up */
 224         MX6_PAD_GPIO_18__GPIO_7_13      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 225 };
 226
 227 static void setup_iomux_enet(void)
 228 {
 229         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 230         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 231         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 232         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 233         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 234         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 235         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 236         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 237         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 238
 239         /* Need delay 10ms according to KSZ9021 spec */
 240         udelay(1000 * 10);
 241         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 242         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 243
 244         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 245 }
 246
 247 iomux_v3_cfg_t const usb_pads[] = {
 248         MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 249 };
 250
 251 static void setup_iomux_uart(void)
 252 {
 253         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 254         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 255 }
 256
 257 #ifdef CONFIG_USB_EHCI_MX6
 258 int board_ehci_hcd_init(int port)
 259 {
 260         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 261
 262         /* Reset USB hub */
 263         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 264         mdelay(2);
 265         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 266
 267         return 0;
 268 }
 269 #endif
 270
 271 #ifdef CONFIG_FSL_ESDHC
 272 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 273         {USDHC3_BASE_ADDR},
 274         {USDHC4_BASE_ADDR},
 275 };
 276
 277 int board_mmc_getcd(struct mmc *mmc)
 278 {
 279         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 280         int ret;
 281
 282         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 283                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 284                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 285         } else {
 286                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 287                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 288         }
 289
 290         return ret;
 291 }
 292
 293 int board_mmc_init(bd_t *bis)
 294 {
 295         s32 status = 0;
 296         u32 index = 0;
 297
 298         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 299         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 300
 301         usdhc_cfg[0].max_bus_width = 4;
 302         usdhc_cfg[1].max_bus_width = 4;
 303
 304         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 305                 switch (index) {
 306                 case 0:
 307                         imx_iomux_v3_setup_multiple_pads(
 308                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 309                         break;
 310                 case 1:
 311                        imx_iomux_v3_setup_multiple_pads(
 312                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 313                        break;
 314                 default:
 315                        printf("Warning: you configured more USDHC controllers"
 316                                "(%d) then supported by the board (%d)\n",
 317                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 318                        return status;
 319                 }
 320
 321                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 322         }
 323
 324         return status;
 325 }
 326 #endif
 327
 328 #ifdef CONFIG_MXC_SPI
 329 iomux_v3_cfg_t const ecspi1_pads[] = {
 330         /* SS1 */
 331         MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 332         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 333         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 334         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 335 };
 336
 337 void setup_spi(void)
 338 {
 339         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 340         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 341                                          ARRAY_SIZE(ecspi1_pads));
 342 }
 343 #endif
 344
 345 int board_phy_config(struct phy_device *phydev)
 346 {
 347         /* min rx data delay */
 348         ksz9021_phy_extended_write(phydev,
 349                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 350         /* min tx data delay */
 351         ksz9021_phy_extended_write(phydev,
 352                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 353         /* max rx/tx clock delay, min rx/tx control */
 354         ksz9021_phy_extended_write(phydev,
 355                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 356         if (phydev->drv->config)
 357                 phydev->drv->config(phydev);
 358
 359         return 0;
 360 }
 361
 362 int board_eth_init(bd_t *bis)
 363 {
 364         uint32_t base = IMX_FEC_BASE;
 365         struct mii_dev *bus = NULL;
 366         struct phy_device *phydev = NULL;
 367         int ret;
 368
 369         setup_iomux_enet();
 370
 371 #ifdef CONFIG_FEC_MXC
 372         bus = fec_get_miibus(base, -1);
 373         if (!bus)
 374                 return 0;
 375         /* scan phy 4,5,6,7 */
 376         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 377         if (!phydev) {
 378                 free(bus);
 379                 return 0;
 380         }
 381         printf("using phy at %d\n", phydev->addr);
 382         ret  = fec_probe(bis, -1, base, bus, phydev);
 383         if (ret) {
 384                 printf("FEC MXC: %s:failed\n", __func__);
 385                 free(phydev);
 386                 free(bus);
 387         }
 388 #endif
 389         return 0;
 390 }
 391
 392 static void setup_buttons(void)
 393 {
 394         imx_iomux_v3_setup_multiple_pads(button_pads,
 395                                          ARRAY_SIZE(button_pads));
 396 }
 397
 398 #ifdef CONFIG_CMD_SATA
 399
 400 int setup_sata(void)
 401 {
 402         struct iomuxc_base_regs *const iomuxc_regs
 403                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 404         int ret = enable_sata_clock();
 405         if (ret)
 406                 return ret;
 407
 408         clrsetbits_le32(&iomuxc_regs->gpr[13],
 409                         IOMUXC_GPR13_SATA_MASK,
 410                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 411                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 412                         |IOMUXC_GPR13_SATA_SPEED_3G
 413                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 414                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 415                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 416                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 417                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 418                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 419
 420         return 0;
 421 }
 422 #endif
 423
 424 #if defined(CONFIG_VIDEO_IPUV3)
 425
 426 static iomux_v3_cfg_t const backlight_pads[] = {
 427         /* Backlight on RGB connector: J15 */
 428         MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 429 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 430
 431         /* Backlight on LVDS connector: J6 */
 432         MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 433 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 434 };
 435
 436 static iomux_v3_cfg_t const rgb_pads[] = {
 437         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 438         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 439         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 440         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 441         MX6_PAD_DI0_PIN4__GPIO_4_20,
 442         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 443         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 444         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 445         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 446         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 447         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 448         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 449         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 450         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 451         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 452         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 453         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 454         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 455         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 456         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 457         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 458         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 459         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 460         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 461         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 462         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 463         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 464         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 465         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 466 };
 467
 468 struct display_info_t {
 469         int     bus;
 470         int     addr;
 471         int     pixfmt;
 472         int     (*detect)(struct display_info_t const *dev);
 473         void    (*enable)(struct display_info_t const *dev);
 474         struct  fb_videomode mode;
 475 };
 476
 477
 478 static int detect_hdmi(struct display_info_t const *dev)
 479 {
 480         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 481         return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
 482 }
 483
 484 static void enable_hdmi(struct display_info_t const *dev)
 485 {
 486         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 487         u8 reg;
 488         printf("%s: setup HDMI monitor\n", __func__);
 489         reg = readb(&hdmi->phy_conf0);
 490         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 491         writeb(reg, &hdmi->phy_conf0);
 492
 493         udelay(3000);
 494         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 495         writeb(reg, &hdmi->phy_conf0);
 496         udelay(3000);
 497         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 498         writeb(reg, &hdmi->phy_conf0);
 499         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 500 }
 501
 502 static int detect_i2c(struct display_info_t const *dev)
 503 {
 504         return ((0 == i2c_set_bus_num(dev->bus))
 505                 &&
 506                 (0 == i2c_probe(dev->addr)));
 507 }
 508
 509 static void enable_lvds(struct display_info_t const *dev)
 510 {
 511         struct iomuxc *iomux = (struct iomuxc *)
 512                                 IOMUXC_BASE_ADDR;
 513         u32 reg = readl(&iomux->gpr[2]);
 514         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 515         writel(reg, &iomux->gpr[2]);
 516         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 517 }
 518
 519 static void enable_rgb(struct display_info_t const *dev)
 520 {
 521         imx_iomux_v3_setup_multiple_pads(
 522                 rgb_pads,
 523                  ARRAY_SIZE(rgb_pads));
 524         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 525 }
 526
 527 static struct display_info_t const displays[] = {{
 528         .bus    = -1,
 529         .addr   = 0,
 530         .pixfmt = IPU_PIX_FMT_RGB24,
 531         .detect = detect_hdmi,
 532         .enable = enable_hdmi,
 533         .mode   = {
 534                 .name           = "HDMI",
 535                 .refresh        = 60,
 536                 .xres           = 1024,
 537                 .yres           = 768,
 538                 .pixclock       = 15385,
 539                 .left_margin    = 220,
 540                 .right_margin   = 40,
 541                 .upper_margin   = 21,
 542                 .lower_margin   = 7,
 543                 .hsync_len      = 60,
 544                 .vsync_len      = 10,
 545                 .sync           = FB_SYNC_EXT,
 546                 .vmode          = FB_VMODE_NONINTERLACED
 547 } }, {
 548         .bus    = 2,
 549         .addr   = 0x4,
 550         .pixfmt = IPU_PIX_FMT_LVDS666,
 551         .detect = detect_i2c,
 552         .enable = enable_lvds,
 553         .mode   = {
 554                 .name           = "Hannstar-XGA",
 555                 .refresh        = 60,
 556                 .xres           = 1024,
 557                 .yres           = 768,
 558                 .pixclock       = 15385,
 559                 .left_margin    = 220,
 560                 .right_margin   = 40,
 561                 .upper_margin   = 21,
 562                 .lower_margin   = 7,
 563                 .hsync_len      = 60,
 564                 .vsync_len      = 10,
 565                 .sync           = FB_SYNC_EXT,
 566                 .vmode          = FB_VMODE_NONINTERLACED
 567 } }, {
 568         .bus    = 2,
 569         .addr   = 0x38,
 570         .pixfmt = IPU_PIX_FMT_LVDS666,
 571         .detect = detect_i2c,
 572         .enable = enable_lvds,
 573         .mode   = {
 574                 .name           = "wsvga-lvds",
 575                 .refresh        = 60,
 576                 .xres           = 1024,
 577                 .yres           = 600,
 578                 .pixclock       = 15385,
 579                 .left_margin    = 220,
 580                 .right_margin   = 40,
 581                 .upper_margin   = 21,
 582                 .lower_margin   = 7,
 583                 .hsync_len      = 60,
 584                 .vsync_len      = 10,
 585                 .sync           = FB_SYNC_EXT,
 586                 .vmode          = FB_VMODE_NONINTERLACED
 587 } }, {
 588         .bus    = 2,
 589         .addr   = 0x48,
 590         .pixfmt = IPU_PIX_FMT_RGB666,
 591         .detect = detect_i2c,
 592         .enable = enable_rgb,
 593         .mode   = {
 594                 .name           = "wvga-rgb",
 595                 .refresh        = 57,
 596                 .xres           = 800,
 597                 .yres           = 480,
 598                 .pixclock       = 37037,
 599                 .left_margin    = 40,
 600                 .right_margin   = 60,
 601                 .upper_margin   = 10,
 602                 .lower_margin   = 10,
 603                 .hsync_len      = 20,
 604                 .vsync_len      = 10,
 605                 .sync           = 0,
 606                 .vmode          = FB_VMODE_NONINTERLACED
 607 } } };
 608
 609 int board_video_skip(void)
 610 {
 611         int i;
 612         int ret;
 613         char const *panel = getenv("panel");
 614         if (!panel) {
 615                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 616                         struct display_info_t const *dev = displays+i;
 617                         if (dev->detect(dev)) {
 618                                 panel = dev->mode.name;
 619                                 printf("auto-detected panel %s\n", panel);
 620                                 break;
 621                         }
 622                 }
 623                 if (!panel) {
 624                         panel = displays[0].mode.name;
 625                         printf("No panel detected: default to %s\n", panel);
 626                 }
 627         } else {
 628                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 629                         if (!strcmp(panel, displays[i].mode.name))
 630                                 break;
 631                 }
 632         }
 633         if (i < ARRAY_SIZE(displays)) {
 634                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 635                                     displays[i].pixfmt);
 636                 if (!ret) {
 637                         displays[i].enable(displays+i);
 638                         printf("Display: %s (%ux%u)\n",
 639                                displays[i].mode.name,
 640                                displays[i].mode.xres,
 641                                displays[i].mode.yres);
 642                 } else
 643                         printf("LCD %s cannot be configured: %d\n",
 644                                displays[i].mode.name, ret);
 645         } else {
 646                 printf("unsupported panel %s\n", panel);
 647                 ret = -EINVAL;
 648         }
 649         return (0 != ret);
 650 }
 651
 652 static void setup_display(void)
 653 {
 654         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 655         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 656         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 657         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 658
 659         int reg;
 660
 661         /* Turn on LDB0,IPU,IPU DI0 clocks */
 662         reg = __raw_readl(&mxc_ccm->CCGR3);
 663         reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
 664                 |MXC_CCM_CCGR3_LDB_DI0_MASK;
 665         writel(reg, &mxc_ccm->CCGR3);
 666
 667         /* Turn on HDMI PHY clock */
 668         reg = __raw_readl(&mxc_ccm->CCGR2);
 669         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
 670                |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 671         writel(reg, &mxc_ccm->CCGR2);
 672
 673         /* clear HDMI PHY reset */
 674         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 675
 676         /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 677         writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 678         writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
 679
 680         /* set LDB0, LDB1 clk select to 011/011 */
 681         reg = readl(&mxc_ccm->cs2cdr);
 682         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 683                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 684         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 685               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 686         writel(reg, &mxc_ccm->cs2cdr);
 687
 688         reg = readl(&mxc_ccm->cscmr2);
 689         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 690         writel(reg, &mxc_ccm->cscmr2);
 691
 692         reg = readl(&mxc_ccm->chsccdr);
 693         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
 694                 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
 695                 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 696         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 697                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 698               |(CHSCCDR_PODF_DIVIDE_BY_3
 699                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 700               |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 701                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 702         writel(reg, &mxc_ccm->chsccdr);
 703
 704         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 705              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 706              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 707              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 708              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 709              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 710              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 711              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 712              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 713         writel(reg, &iomux->gpr[2]);
 714
 715         reg = readl(&iomux->gpr[3]);
 716         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 717             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 718                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 719         writel(reg, &iomux->gpr[3]);
 720
 721         /* backlights off until needed */
 722         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 723                                          ARRAY_SIZE(backlight_pads));
 724         gpio_direction_input(LVDS_BACKLIGHT_GP);
 725         gpio_direction_input(RGB_BACKLIGHT_GP);
 726 }
 727 #endif
 728
 729 int board_early_init_f(void)
 730 {
 731         setup_iomux_uart();
 732
 733         /* Disable wl1271 For Nitrogen6w */
 734         gpio_direction_input(WL12XX_WL_IRQ_GP);
 735         gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
 736         gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
 737
 738         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 739         setup_buttons();
 740
 741 #if defined(CONFIG_VIDEO_IPUV3)
 742         setup_display();
 743 #endif
 744         return 0;
 745 }
 746
 747 /*
 748  * Do not overwrite the console
 749  * Use always serial for U-Boot console
 750  */
 751 int overwrite_console(void)
 752 {
 753         return 1;
 754 }
 755
 756 int board_init(void)
 757 {
 758         /* address of boot parameters */
 759         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 760
 761 #ifdef CONFIG_MXC_SPI
 762         setup_spi();
 763 #endif
 764         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 765         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 766         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 767
 768 #ifdef CONFIG_CMD_SATA
 769         setup_sata();
 770 #endif
 771
 772         return 0;
 773 }
 774
 775 int checkboard(void)
 776 {
 777         if (gpio_get_value(WL12XX_WL_IRQ_GP))
 778                 puts("Board: Nitrogen6X\n");
 779         else
 780                 puts("Board: SABRE Lite\n");
 781
 782         return 0;
 783 }
 784
 785 struct button_key {
 786         char const      *name;
 787         unsigned        gpnum;
 788         char            ident;
 789 };
 790
 791 static struct button_key const buttons[] = {
 792         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 793         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 794         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 795         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 796         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 797         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 798 };
 799
 800 /*
 801  * generate a null-terminated string containing the buttons pressed
 802  * returns number of keys pressed
 803  */
 804 static int read_keys(char *buf)
 805 {
 806         int i, numpressed = 0;
 807         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 808                 if (!gpio_get_value(buttons[i].gpnum))
 809                         buf[numpressed++] = buttons[i].ident;
 810         }
 811         buf[numpressed] = '\0';
 812         return numpressed;
 813 }
 814
 815 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 816 {
 817         char envvalue[ARRAY_SIZE(buttons)+1];
 818         int numpressed = read_keys(envvalue);
 819         setenv("keybd", envvalue);
 820         return numpressed == 0;
 821 }
 822
 823 U_BOOT_CMD(
 824         kbd, 1, 1, do_kbd,
 825         "Tests for keypresses, sets 'keybd' environment variable",
 826         "Returns 0 (true) to shell if key is pressed."
 827 );
 828
 829 #ifdef CONFIG_PREBOOT
 830 static char const kbd_magic_prefix[] = "key_magic";
 831 static char const kbd_command_prefix[] = "key_cmd";
 832
 833 static void preboot_keys(void)
 834 {
 835         int numpressed;
 836         char keypress[ARRAY_SIZE(buttons)+1];
 837         numpressed = read_keys(keypress);
 838         if (numpressed) {
 839                 char *kbd_magic_keys = getenv("magic_keys");
 840                 char *suffix;
 841                 /*
 842                  * loop over all magic keys
 843                  */
 844                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 845                         char *keys;
 846                         char magic[sizeof(kbd_magic_prefix) + 1];
 847                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 848                         keys = getenv(magic);
 849                         if (keys) {
 850                                 if (!strcmp(keys, keypress))
 851                                         break;
 852                         }
 853                 }
 854                 if (*suffix) {
 855                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 856                         char *cmd;
 857                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 858                         cmd = getenv(cmd_name);
 859                         if (cmd) {
 860                                 setenv("preboot", cmd);
 861                                 return;
 862                         }
 863                 }
 864         }
 865 }
 866 #endif
 867
 868 #ifdef CONFIG_CMD_BMODE
 869 static const struct boot_mode board_boot_modes[] = {
 870         /* 4 bit bus width */
 871         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 872         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 873         {NULL,          0},
 874 };
 875 #endif
 876
 877 int misc_init_r(void)
 878 {
 879 #ifdef CONFIG_PREBOOT
 880         preboot_keys();
 881 #endif
 882
 883 #ifdef CONFIG_CMD_BMODE
 884         add_board_boot_modes(board_boot_modes);
 885 #endif
 886         return 0;
 887 }