board/boundary/nitrogen6x/nitrogen6x.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <malloc.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/imx-common/boot_mode.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <micrel.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <linux/fb.h>
  27 #include <ipu_pixfmt.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/mxc_hdmi.h>
  30 #include <i2c.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  40         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  45
  46 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  47         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  48
  49 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  58         PAD_CTL_SRE_SLOW)
  59
  60 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  62         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  63
  64 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  65
  66 int dram_init(void)
  67 {
  68         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  69
  70         return 0;
  71 }
  72
  73 iomux_v3_cfg_t const uart1_pads[] = {
  74         MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  75         MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  76 };
  77
  78 iomux_v3_cfg_t const uart2_pads[] = {
  79         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  80         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  81 };
  82
  83 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  84
  85 /* I2C1, SGTL5000 */
  86 struct i2c_pads_info i2c_pad_info0 = {
  87         .scl = {
  88                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  89                 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
  90                 .gp = IMX_GPIO_NR(3, 21)
  91         },
  92         .sda = {
  93                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  94                 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
  95                 .gp = IMX_GPIO_NR(3, 28)
  96         }
  97 };
  98
  99 /* I2C2 Camera, MIPI */
 100 struct i2c_pads_info i2c_pad_info1 = {
 101         .scl = {
 102                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 103                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
 104                 .gp = IMX_GPIO_NR(4, 12)
 105         },
 106         .sda = {
 107                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 108                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
 109                 .gp = IMX_GPIO_NR(4, 13)
 110         }
 111 };
 112
 113 /* I2C3, J15 - RGB connector */
 114 struct i2c_pads_info i2c_pad_info2 = {
 115         .scl = {
 116                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 117                 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
 118                 .gp = IMX_GPIO_NR(1, 5)
 119         },
 120         .sda = {
 121                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 122                 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
 123                 .gp = IMX_GPIO_NR(7, 11)
 124         }
 125 };
 126
 127 iomux_v3_cfg_t const usdhc3_pads[] = {
 128         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 135 };
 136
 137 iomux_v3_cfg_t const usdhc4_pads[] = {
 138         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 145 };
 146
 147 iomux_v3_cfg_t const enet_pads1[] = {
 148         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 149         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 150         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 151         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 152         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 153         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 154         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 155         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 157         /* pin 35 - 1 (PHY_AD2) on reset */
 158         MX6_PAD_RGMII_RXC__GPIO_6_30            | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         /* pin 32 - 1 - (MODE0) all */
 160         MX6_PAD_RGMII_RD0__GPIO_6_25            | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         /* pin 31 - 1 - (MODE1) all */
 162         MX6_PAD_RGMII_RD1__GPIO_6_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 163         /* pin 28 - 1 - (MODE2) all */
 164         MX6_PAD_RGMII_RD2__GPIO_6_28            | MUX_PAD_CTRL(NO_PAD_CTRL),
 165         /* pin 27 - 1 - (MODE3) all */
 166         MX6_PAD_RGMII_RD3__GPIO_6_29            | MUX_PAD_CTRL(NO_PAD_CTRL),
 167         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 168         MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
 169         /* pin 42 PHY nRST */
 170         MX6_PAD_EIM_D23__GPIO_3_23              | MUX_PAD_CTRL(NO_PAD_CTRL),
 171         MX6_PAD_ENET_RXD0__GPIO_1_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 172 };
 173
 174 iomux_v3_cfg_t const enet_pads2[] = {
 175         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 176         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 177         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 179         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 180         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 181 };
 182
 183 static iomux_v3_cfg_t const misc_pads[] = {
 184         MX6_PAD_GPIO_1__USB_OTG_ID              | MUX_PAD_CTRL(WEAK_PULLUP),
 185         MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC      | MUX_PAD_CTRL(WEAK_PULLUP),
 186         MX6_PAD_EIM_D30__USBOH3_USBH1_OC        | MUX_PAD_CTRL(WEAK_PULLUP),
 187         /* OTG Power enable */
 188         MX6_PAD_EIM_D22__GPIO_3_22              | MUX_PAD_CTRL(OUTPUT_40OHM),
 189 };
 190
 191 /* wl1271 pads on nitrogen6x */
 192 iomux_v3_cfg_t const wl12xx_pads[] = {
 193         (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
 194                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 195         (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
 196                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 197         (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
 198                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 199 };
 200 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 201 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 202 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 203
 204 /* Button assignments for J14 */
 205 static iomux_v3_cfg_t const button_pads[] = {
 206         /* Menu */
 207         MX6_PAD_NANDF_D1__GPIO_2_1      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 208         /* Back */
 209         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 210         /* Labelled Search (mapped to Power under Android) */
 211         MX6_PAD_NANDF_D3__GPIO_2_3      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 212         /* Home */
 213         MX6_PAD_NANDF_D4__GPIO_2_4      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 214         /* Volume Down */
 215         MX6_PAD_GPIO_19__GPIO_4_5       | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 216         /* Volume Up */
 217         MX6_PAD_GPIO_18__GPIO_7_13      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 218 };
 219
 220 static void setup_iomux_enet(void)
 221 {
 222         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 223         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 224         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 225         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 226         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 227         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 228         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 229         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 230         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 231
 232         /* Need delay 10ms according to KSZ9021 spec */
 233         udelay(1000 * 10);
 234         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 235         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 236
 237         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 238 }
 239
 240 iomux_v3_cfg_t const usb_pads[] = {
 241         MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 242 };
 243
 244 static void setup_iomux_uart(void)
 245 {
 246         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 247         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 248 }
 249
 250 #ifdef CONFIG_USB_EHCI_MX6
 251 int board_ehci_hcd_init(int port)
 252 {
 253         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 254
 255         /* Reset USB hub */
 256         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 257         mdelay(2);
 258         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 259
 260         return 0;
 261 }
 262
 263 int board_ehci_power(int port, int on)
 264 {
 265         if (port)
 266                 return 0;
 267         gpio_set_value(GP_USB_OTG_PWR, on);
 268         return 0;
 269 }
 270
 271 #endif
 272
 273 #ifdef CONFIG_FSL_ESDHC
 274 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 275         {USDHC3_BASE_ADDR},
 276         {USDHC4_BASE_ADDR},
 277 };
 278
 279 int board_mmc_getcd(struct mmc *mmc)
 280 {
 281         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 282         int ret;
 283
 284         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 285                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 286                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 287         } else {
 288                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 289                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 290         }
 291
 292         return ret;
 293 }
 294
 295 int board_mmc_init(bd_t *bis)
 296 {
 297         s32 status = 0;
 298         u32 index = 0;
 299
 300         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 301         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 302
 303         usdhc_cfg[0].max_bus_width = 4;
 304         usdhc_cfg[1].max_bus_width = 4;
 305
 306         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 307                 switch (index) {
 308                 case 0:
 309                         imx_iomux_v3_setup_multiple_pads(
 310                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 311                         break;
 312                 case 1:
 313                        imx_iomux_v3_setup_multiple_pads(
 314                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 315                        break;
 316                 default:
 317                        printf("Warning: you configured more USDHC controllers"
 318                                "(%d) then supported by the board (%d)\n",
 319                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 320                        return status;
 321                 }
 322
 323                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 324         }
 325
 326         return status;
 327 }
 328 #endif
 329
 330 #ifdef CONFIG_MXC_SPI
 331 iomux_v3_cfg_t const ecspi1_pads[] = {
 332         /* SS1 */
 333         MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 334         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 335         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 336         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 337 };
 338
 339 void setup_spi(void)
 340 {
 341         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 342                                          ARRAY_SIZE(ecspi1_pads));
 343 }
 344 #endif
 345
 346 int board_phy_config(struct phy_device *phydev)
 347 {
 348         /* min rx data delay */
 349         ksz9021_phy_extended_write(phydev,
 350                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 351         /* min tx data delay */
 352         ksz9021_phy_extended_write(phydev,
 353                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 354         /* max rx/tx clock delay, min rx/tx control */
 355         ksz9021_phy_extended_write(phydev,
 356                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 357         if (phydev->drv->config)
 358                 phydev->drv->config(phydev);
 359
 360         return 0;
 361 }
 362
 363 int board_eth_init(bd_t *bis)
 364 {
 365         uint32_t base = IMX_FEC_BASE;
 366         struct mii_dev *bus = NULL;
 367         struct phy_device *phydev = NULL;
 368         int ret;
 369
 370         setup_iomux_enet();
 371
 372 #ifdef CONFIG_FEC_MXC
 373         bus = fec_get_miibus(base, -1);
 374         if (!bus)
 375                 return 0;
 376         /* scan phy 4,5,6,7 */
 377         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 378         if (!phydev) {
 379                 free(bus);
 380                 return 0;
 381         }
 382         printf("using phy at %d\n", phydev->addr);
 383         ret  = fec_probe(bis, -1, base, bus, phydev);
 384         if (ret) {
 385                 printf("FEC MXC: %s:failed\n", __func__);
 386                 free(phydev);
 387                 free(bus);
 388         }
 389 #endif
 390
 391 #ifdef CONFIG_MV_UDC
 392         /* For otg ethernet*/
 393         usb_eth_initialize(bis);
 394 #endif
 395         return 0;
 396 }
 397
 398 static void setup_buttons(void)
 399 {
 400         imx_iomux_v3_setup_multiple_pads(button_pads,
 401                                          ARRAY_SIZE(button_pads));
 402 }
 403
 404 #ifdef CONFIG_CMD_SATA
 405
 406 int setup_sata(void)
 407 {
 408         struct iomuxc_base_regs *const iomuxc_regs
 409                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 410         int ret = enable_sata_clock();
 411         if (ret)
 412                 return ret;
 413
 414         clrsetbits_le32(&iomuxc_regs->gpr[13],
 415                         IOMUXC_GPR13_SATA_MASK,
 416                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 417                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 418                         |IOMUXC_GPR13_SATA_SPEED_3G
 419                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 420                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 421                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 422                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 423                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 424                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 425
 426         return 0;
 427 }
 428 #endif
 429
 430 #if defined(CONFIG_VIDEO_IPUV3)
 431
 432 static iomux_v3_cfg_t const backlight_pads[] = {
 433         /* Backlight on RGB connector: J15 */
 434         MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 435 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 436
 437         /* Backlight on LVDS connector: J6 */
 438         MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 439 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 440 };
 441
 442 static iomux_v3_cfg_t const rgb_pads[] = {
 443         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 444         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 445         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 446         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 447         MX6_PAD_DI0_PIN4__GPIO_4_20,
 448         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 449         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 450         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 451         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 452         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 453         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 454         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 455         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 456         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 457         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 458         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 459         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 460         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 461         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 462         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 463         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 464         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 465         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 466         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 467         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 468         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 469         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 470         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 471         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 472 };
 473
 474 struct display_info_t {
 475         int     bus;
 476         int     addr;
 477         int     pixfmt;
 478         int     (*detect)(struct display_info_t const *dev);
 479         void    (*enable)(struct display_info_t const *dev);
 480         struct  fb_videomode mode;
 481 };
 482
 483
 484 static int detect_hdmi(struct display_info_t const *dev)
 485 {
 486         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 487         return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
 488 }
 489
 490 static void do_enable_hdmi(struct display_info_t const *dev)
 491 {
 492         imx_enable_hdmi_phy();
 493 }
 494
 495 static int detect_i2c(struct display_info_t const *dev)
 496 {
 497         return ((0 == i2c_set_bus_num(dev->bus))
 498                 &&
 499                 (0 == i2c_probe(dev->addr)));
 500 }
 501
 502 static void enable_lvds(struct display_info_t const *dev)
 503 {
 504         struct iomuxc *iomux = (struct iomuxc *)
 505                                 IOMUXC_BASE_ADDR;
 506         u32 reg = readl(&iomux->gpr[2]);
 507         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 508         writel(reg, &iomux->gpr[2]);
 509         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 510 }
 511
 512 static void enable_rgb(struct display_info_t const *dev)
 513 {
 514         imx_iomux_v3_setup_multiple_pads(
 515                 rgb_pads,
 516                  ARRAY_SIZE(rgb_pads));
 517         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 518 }
 519
 520 static struct display_info_t const displays[] = {{
 521         .bus    = -1,
 522         .addr   = 0,
 523         .pixfmt = IPU_PIX_FMT_RGB24,
 524         .detect = detect_hdmi,
 525         .enable = do_enable_hdmi,
 526         .mode   = {
 527                 .name           = "HDMI",
 528                 .refresh        = 60,
 529                 .xres           = 1024,
 530                 .yres           = 768,
 531                 .pixclock       = 15385,
 532                 .left_margin    = 220,
 533                 .right_margin   = 40,
 534                 .upper_margin   = 21,
 535                 .lower_margin   = 7,
 536                 .hsync_len      = 60,
 537                 .vsync_len      = 10,
 538                 .sync           = FB_SYNC_EXT,
 539                 .vmode          = FB_VMODE_NONINTERLACED
 540 } }, {
 541         .bus    = 2,
 542         .addr   = 0x4,
 543         .pixfmt = IPU_PIX_FMT_LVDS666,
 544         .detect = detect_i2c,
 545         .enable = enable_lvds,
 546         .mode   = {
 547                 .name           = "Hannstar-XGA",
 548                 .refresh        = 60,
 549                 .xres           = 1024,
 550                 .yres           = 768,
 551                 .pixclock       = 15385,
 552                 .left_margin    = 220,
 553                 .right_margin   = 40,
 554                 .upper_margin   = 21,
 555                 .lower_margin   = 7,
 556                 .hsync_len      = 60,
 557                 .vsync_len      = 10,
 558                 .sync           = FB_SYNC_EXT,
 559                 .vmode          = FB_VMODE_NONINTERLACED
 560 } }, {
 561         .bus    = 2,
 562         .addr   = 0x38,
 563         .pixfmt = IPU_PIX_FMT_LVDS666,
 564         .detect = detect_i2c,
 565         .enable = enable_lvds,
 566         .mode   = {
 567                 .name           = "wsvga-lvds",
 568                 .refresh        = 60,
 569                 .xres           = 1024,
 570                 .yres           = 600,
 571                 .pixclock       = 15385,
 572                 .left_margin    = 220,
 573                 .right_margin   = 40,
 574                 .upper_margin   = 21,
 575                 .lower_margin   = 7,
 576                 .hsync_len      = 60,
 577                 .vsync_len      = 10,
 578                 .sync           = FB_SYNC_EXT,
 579                 .vmode          = FB_VMODE_NONINTERLACED
 580 } }, {
 581         .bus    = 2,
 582         .addr   = 0x48,
 583         .pixfmt = IPU_PIX_FMT_RGB666,
 584         .detect = detect_i2c,
 585         .enable = enable_rgb,
 586         .mode   = {
 587                 .name           = "wvga-rgb",
 588                 .refresh        = 57,
 589                 .xres           = 800,
 590                 .yres           = 480,
 591                 .pixclock       = 37037,
 592                 .left_margin    = 40,
 593                 .right_margin   = 60,
 594                 .upper_margin   = 10,
 595                 .lower_margin   = 10,
 596                 .hsync_len      = 20,
 597                 .vsync_len      = 10,
 598                 .sync           = 0,
 599                 .vmode          = FB_VMODE_NONINTERLACED
 600 } } };
 601
 602 int board_video_skip(void)
 603 {
 604         int i;
 605         int ret;
 606         char const *panel = getenv("panel");
 607         if (!panel) {
 608                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 609                         struct display_info_t const *dev = displays+i;
 610                         if (dev->detect(dev)) {
 611                                 panel = dev->mode.name;
 612                                 printf("auto-detected panel %s\n", panel);
 613                                 break;
 614                         }
 615                 }
 616                 if (!panel) {
 617                         panel = displays[0].mode.name;
 618                         printf("No panel detected: default to %s\n", panel);
 619                         i = 0;
 620                 }
 621         } else {
 622                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 623                         if (!strcmp(panel, displays[i].mode.name))
 624                                 break;
 625                 }
 626         }
 627         if (i < ARRAY_SIZE(displays)) {
 628                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 629                                     displays[i].pixfmt);
 630                 if (!ret) {
 631                         displays[i].enable(displays+i);
 632                         printf("Display: %s (%ux%u)\n",
 633                                displays[i].mode.name,
 634                                displays[i].mode.xres,
 635                                displays[i].mode.yres);
 636                 } else {
 637                         printf("LCD %s cannot be configured: %d\n",
 638                                displays[i].mode.name, ret);
 639                 }
 640         } else {
 641                 printf("unsupported panel %s\n", panel);
 642                 ret = -EINVAL;
 643         }
 644         return (0 != ret);
 645 }
 646
 647 static void setup_display(void)
 648 {
 649         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 650         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 651         int reg;
 652
 653         enable_ipu_clock();
 654         imx_setup_hdmi();
 655         /* Turn on LDB0,IPU,IPU DI0 clocks */
 656         reg = __raw_readl(&mxc_ccm->CCGR3);
 657         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 658         writel(reg, &mxc_ccm->CCGR3);
 659
 660         /* set LDB0, LDB1 clk select to 011/011 */
 661         reg = readl(&mxc_ccm->cs2cdr);
 662         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 663                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 664         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 665               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 666         writel(reg, &mxc_ccm->cs2cdr);
 667
 668         reg = readl(&mxc_ccm->cscmr2);
 669         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 670         writel(reg, &mxc_ccm->cscmr2);
 671
 672         reg = readl(&mxc_ccm->chsccdr);
 673         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 674                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 675         writel(reg, &mxc_ccm->chsccdr);
 676
 677         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 678              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 679              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 680              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 681              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 682              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 683              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 684              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 685              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 686         writel(reg, &iomux->gpr[2]);
 687
 688         reg = readl(&iomux->gpr[3]);
 689         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 690                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 691             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 692                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 693         writel(reg, &iomux->gpr[3]);
 694
 695         /* backlights off until needed */
 696         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 697                                          ARRAY_SIZE(backlight_pads));
 698         gpio_direction_input(LVDS_BACKLIGHT_GP);
 699         gpio_direction_input(RGB_BACKLIGHT_GP);
 700 }
 701 #endif
 702
 703 int board_early_init_f(void)
 704 {
 705         setup_iomux_uart();
 706
 707         /* Disable wl1271 For Nitrogen6w */
 708         gpio_direction_input(WL12XX_WL_IRQ_GP);
 709         gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
 710         gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
 711         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
 712
 713         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 714         setup_buttons();
 715
 716 #if defined(CONFIG_VIDEO_IPUV3)
 717         setup_display();
 718 #endif
 719         return 0;
 720 }
 721
 722 /*
 723  * Do not overwrite the console
 724  * Use always serial for U-Boot console
 725  */
 726 int overwrite_console(void)
 727 {
 728         return 1;
 729 }
 730
 731 int board_init(void)
 732 {
 733         struct iomuxc_base_regs *const iomuxc_regs
 734                 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
 735
 736         clrsetbits_le32(&iomuxc_regs->gpr[1],
 737                         IOMUXC_GPR1_OTG_ID_MASK,
 738                         IOMUXC_GPR1_OTG_ID_GPIO1);
 739
 740         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 741
 742         /* address of boot parameters */
 743         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 744
 745 #ifdef CONFIG_MXC_SPI
 746         setup_spi();
 747 #endif
 748         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 749         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 750         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 751
 752 #ifdef CONFIG_CMD_SATA
 753         setup_sata();
 754 #endif
 755
 756         return 0;
 757 }
 758
 759 int checkboard(void)
 760 {
 761         if (gpio_get_value(WL12XX_WL_IRQ_GP))
 762                 puts("Board: Nitrogen6X\n");
 763         else
 764                 puts("Board: SABRE Lite\n");
 765
 766         return 0;
 767 }
 768
 769 struct button_key {
 770         char const      *name;
 771         unsigned        gpnum;
 772         char            ident;
 773 };
 774
 775 static struct button_key const buttons[] = {
 776         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 777         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 778         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 779         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 780         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 781         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 782 };
 783
 784 /*
 785  * generate a null-terminated string containing the buttons pressed
 786  * returns number of keys pressed
 787  */
 788 static int read_keys(char *buf)
 789 {
 790         int i, numpressed = 0;
 791         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 792                 if (!gpio_get_value(buttons[i].gpnum))
 793                         buf[numpressed++] = buttons[i].ident;
 794         }
 795         buf[numpressed] = '\0';
 796         return numpressed;
 797 }
 798
 799 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 800 {
 801         char envvalue[ARRAY_SIZE(buttons)+1];
 802         int numpressed = read_keys(envvalue);
 803         setenv("keybd", envvalue);
 804         return numpressed == 0;
 805 }
 806
 807 U_BOOT_CMD(
 808         kbd, 1, 1, do_kbd,
 809         "Tests for keypresses, sets 'keybd' environment variable",
 810         "Returns 0 (true) to shell if key is pressed."
 811 );
 812
 813 #ifdef CONFIG_PREBOOT
 814 static char const kbd_magic_prefix[] = "key_magic";
 815 static char const kbd_command_prefix[] = "key_cmd";
 816
 817 static void preboot_keys(void)
 818 {
 819         int numpressed;
 820         char keypress[ARRAY_SIZE(buttons)+1];
 821         numpressed = read_keys(keypress);
 822         if (numpressed) {
 823                 char *kbd_magic_keys = getenv("magic_keys");
 824                 char *suffix;
 825                 /*
 826                  * loop over all magic keys
 827                  */
 828                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 829                         char *keys;
 830                         char magic[sizeof(kbd_magic_prefix) + 1];
 831                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 832                         keys = getenv(magic);
 833                         if (keys) {
 834                                 if (!strcmp(keys, keypress))
 835                                         break;
 836                         }
 837                 }
 838                 if (*suffix) {
 839                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 840                         char *cmd;
 841                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 842                         cmd = getenv(cmd_name);
 843                         if (cmd) {
 844                                 setenv("preboot", cmd);
 845                                 return;
 846                         }
 847                 }
 848         }
 849 }
 850 #endif
 851
 852 #ifdef CONFIG_CMD_BMODE
 853 static const struct boot_mode board_boot_modes[] = {
 854         /* 4 bit bus width */
 855         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 856         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 857         {NULL,          0},
 858 };
 859 #endif
 860
 861 int misc_init_r(void)
 862 {
 863 #ifdef CONFIG_PREBOOT
 864         preboot_keys();
 865 #endif
 866
 867 #ifdef CONFIG_CMD_BMODE
 868         add_board_boot_modes(board_boot_modes);
 869 #endif
 870         return 0;
 871 }