board/boundary/nitrogen6x/nitrogen6x.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <malloc.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/imx-common/boot_mode.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <micrel.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <linux/fb.h>
  27 #include <ipu_pixfmt.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/mxc_hdmi.h>
  30 #include <i2c.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  35         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  39         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  44
  45 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  46         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  47
  48 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50
  51 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54
  55 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_SRE_SLOW)
  58
  59 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  61         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  62
  63 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  64
  65 int dram_init(void)
  66 {
  67         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  68
  69         return 0;
  70 }
  71
  72 iomux_v3_cfg_t const uart1_pads[] = {
  73         MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  75 };
  76
  77 iomux_v3_cfg_t const uart2_pads[] = {
  78         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  80 };
  81
  82 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  83
  84 /* I2C1, SGTL5000 */
  85 struct i2c_pads_info i2c_pad_info0 = {
  86         .scl = {
  87                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  88                 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
  89                 .gp = IMX_GPIO_NR(3, 21)
  90         },
  91         .sda = {
  92                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  93                 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
  94                 .gp = IMX_GPIO_NR(3, 28)
  95         }
  96 };
  97
  98 /* I2C2 Camera, MIPI */
  99 struct i2c_pads_info i2c_pad_info1 = {
 100         .scl = {
 101                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 102                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
 103                 .gp = IMX_GPIO_NR(4, 12)
 104         },
 105         .sda = {
 106                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 107                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
 108                 .gp = IMX_GPIO_NR(4, 13)
 109         }
 110 };
 111
 112 /* I2C3, J15 - RGB connector */
 113 struct i2c_pads_info i2c_pad_info2 = {
 114         .scl = {
 115                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 116                 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
 117                 .gp = IMX_GPIO_NR(1, 5)
 118         },
 119         .sda = {
 120                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 121                 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
 122                 .gp = IMX_GPIO_NR(7, 11)
 123         }
 124 };
 125
 126 iomux_v3_cfg_t const usdhc3_pads[] = {
 127         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 134 };
 135
 136 iomux_v3_cfg_t const usdhc4_pads[] = {
 137         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 144 };
 145
 146 iomux_v3_cfg_t const enet_pads1[] = {
 147         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 148         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 149         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 150         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 151         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 152         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 153         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 154         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 155         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         /* pin 35 - 1 (PHY_AD2) on reset */
 157         MX6_PAD_RGMII_RXC__GPIO_6_30            | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         /* pin 32 - 1 - (MODE0) all */
 159         MX6_PAD_RGMII_RD0__GPIO_6_25            | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         /* pin 31 - 1 - (MODE1) all */
 161         MX6_PAD_RGMII_RD1__GPIO_6_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         /* pin 28 - 1 - (MODE2) all */
 163         MX6_PAD_RGMII_RD2__GPIO_6_28            | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         /* pin 27 - 1 - (MODE3) all */
 165         MX6_PAD_RGMII_RD3__GPIO_6_29            | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 167         MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         /* pin 42 PHY nRST */
 169         MX6_PAD_EIM_D23__GPIO_3_23              | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         MX6_PAD_ENET_RXD0__GPIO_1_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 171 };
 172
 173 iomux_v3_cfg_t const enet_pads2[] = {
 174         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 175         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 176         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 177         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 179         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 180 };
 181
 182 /* wl1271 pads on nitrogen6x */
 183 iomux_v3_cfg_t const wl12xx_pads[] = {
 184         (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
 185                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 186         (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
 187                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 188         (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
 189                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 190 };
 191 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 192 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 193 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 194
 195 /* Button assignments for J14 */
 196 static iomux_v3_cfg_t const button_pads[] = {
 197         /* Menu */
 198         MX6_PAD_NANDF_D1__GPIO_2_1      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 199         /* Back */
 200         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 201         /* Labelled Search (mapped to Power under Android) */
 202         MX6_PAD_NANDF_D3__GPIO_2_3      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 203         /* Home */
 204         MX6_PAD_NANDF_D4__GPIO_2_4      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 205         /* Volume Down */
 206         MX6_PAD_GPIO_19__GPIO_4_5       | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 207         /* Volume Up */
 208         MX6_PAD_GPIO_18__GPIO_7_13      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 209 };
 210
 211 static void setup_iomux_enet(void)
 212 {
 213         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 214         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 215         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 216         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 217         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 218         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 219         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 220         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 221         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 222
 223         /* Need delay 10ms according to KSZ9021 spec */
 224         udelay(1000 * 10);
 225         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 226         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 227
 228         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 229 }
 230
 231 iomux_v3_cfg_t const usb_pads[] = {
 232         MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 233 };
 234
 235 static void setup_iomux_uart(void)
 236 {
 237         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 238         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 239 }
 240
 241 #ifdef CONFIG_USB_EHCI_MX6
 242 int board_ehci_hcd_init(int port)
 243 {
 244         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 245
 246         /* Reset USB hub */
 247         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 248         mdelay(2);
 249         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 250
 251         return 0;
 252 }
 253 #endif
 254
 255 #ifdef CONFIG_FSL_ESDHC
 256 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 257         {USDHC3_BASE_ADDR},
 258         {USDHC4_BASE_ADDR},
 259 };
 260
 261 int board_mmc_getcd(struct mmc *mmc)
 262 {
 263         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 264         int ret;
 265
 266         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 267                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 268                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 269         } else {
 270                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 271                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 272         }
 273
 274         return ret;
 275 }
 276
 277 int board_mmc_init(bd_t *bis)
 278 {
 279         s32 status = 0;
 280         u32 index = 0;
 281
 282         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 283         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 284
 285         usdhc_cfg[0].max_bus_width = 4;
 286         usdhc_cfg[1].max_bus_width = 4;
 287
 288         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 289                 switch (index) {
 290                 case 0:
 291                         imx_iomux_v3_setup_multiple_pads(
 292                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 293                         break;
 294                 case 1:
 295                        imx_iomux_v3_setup_multiple_pads(
 296                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 297                        break;
 298                 default:
 299                        printf("Warning: you configured more USDHC controllers"
 300                                "(%d) then supported by the board (%d)\n",
 301                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 302                        return status;
 303                 }
 304
 305                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 306         }
 307
 308         return status;
 309 }
 310 #endif
 311
 312 #ifdef CONFIG_MXC_SPI
 313 iomux_v3_cfg_t const ecspi1_pads[] = {
 314         /* SS1 */
 315         MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 316         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 317         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 318         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 319 };
 320
 321 void setup_spi(void)
 322 {
 323         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 324                                          ARRAY_SIZE(ecspi1_pads));
 325 }
 326 #endif
 327
 328 int board_phy_config(struct phy_device *phydev)
 329 {
 330         /* min rx data delay */
 331         ksz9021_phy_extended_write(phydev,
 332                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 333         /* min tx data delay */
 334         ksz9021_phy_extended_write(phydev,
 335                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 336         /* max rx/tx clock delay, min rx/tx control */
 337         ksz9021_phy_extended_write(phydev,
 338                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 339         if (phydev->drv->config)
 340                 phydev->drv->config(phydev);
 341
 342         return 0;
 343 }
 344
 345 int board_eth_init(bd_t *bis)
 346 {
 347         uint32_t base = IMX_FEC_BASE;
 348         struct mii_dev *bus = NULL;
 349         struct phy_device *phydev = NULL;
 350         int ret;
 351
 352         setup_iomux_enet();
 353
 354 #ifdef CONFIG_FEC_MXC
 355         bus = fec_get_miibus(base, -1);
 356         if (!bus)
 357                 return 0;
 358         /* scan phy 4,5,6,7 */
 359         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 360         if (!phydev) {
 361                 free(bus);
 362                 return 0;
 363         }
 364         printf("using phy at %d\n", phydev->addr);
 365         ret  = fec_probe(bis, -1, base, bus, phydev);
 366         if (ret) {
 367                 printf("FEC MXC: %s:failed\n", __func__);
 368                 free(phydev);
 369                 free(bus);
 370         }
 371 #endif
 372         return 0;
 373 }
 374
 375 static void setup_buttons(void)
 376 {
 377         imx_iomux_v3_setup_multiple_pads(button_pads,
 378                                          ARRAY_SIZE(button_pads));
 379 }
 380
 381 #ifdef CONFIG_CMD_SATA
 382
 383 int setup_sata(void)
 384 {
 385         struct iomuxc_base_regs *const iomuxc_regs
 386                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 387         int ret = enable_sata_clock();
 388         if (ret)
 389                 return ret;
 390
 391         clrsetbits_le32(&iomuxc_regs->gpr[13],
 392                         IOMUXC_GPR13_SATA_MASK,
 393                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 394                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 395                         |IOMUXC_GPR13_SATA_SPEED_3G
 396                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 397                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 398                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 399                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 400                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 401                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 402
 403         return 0;
 404 }
 405 #endif
 406
 407 #if defined(CONFIG_VIDEO_IPUV3)
 408
 409 static iomux_v3_cfg_t const backlight_pads[] = {
 410         /* Backlight on RGB connector: J15 */
 411         MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 412 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 413
 414         /* Backlight on LVDS connector: J6 */
 415         MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 416 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 417 };
 418
 419 static iomux_v3_cfg_t const rgb_pads[] = {
 420         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 421         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 422         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 423         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 424         MX6_PAD_DI0_PIN4__GPIO_4_20,
 425         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 426         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 427         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 428         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 429         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 430         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 431         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 432         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 433         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 434         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 435         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 436         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 437         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 438         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 439         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 440         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 441         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 442         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 443         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 444         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 445         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 446         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 447         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 448         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 449 };
 450
 451 struct display_info_t {
 452         int     bus;
 453         int     addr;
 454         int     pixfmt;
 455         int     (*detect)(struct display_info_t const *dev);
 456         void    (*enable)(struct display_info_t const *dev);
 457         struct  fb_videomode mode;
 458 };
 459
 460
 461 static int detect_hdmi(struct display_info_t const *dev)
 462 {
 463         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 464         return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
 465 }
 466
 467 static void enable_hdmi(struct display_info_t const *dev)
 468 {
 469         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 470         u8 reg;
 471         printf("%s: setup HDMI monitor\n", __func__);
 472         reg = readb(&hdmi->phy_conf0);
 473         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 474         writeb(reg, &hdmi->phy_conf0);
 475
 476         udelay(3000);
 477         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 478         writeb(reg, &hdmi->phy_conf0);
 479         udelay(3000);
 480         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 481         writeb(reg, &hdmi->phy_conf0);
 482         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 483 }
 484
 485 static int detect_i2c(struct display_info_t const *dev)
 486 {
 487         return ((0 == i2c_set_bus_num(dev->bus))
 488                 &&
 489                 (0 == i2c_probe(dev->addr)));
 490 }
 491
 492 static void enable_lvds(struct display_info_t const *dev)
 493 {
 494         struct iomuxc *iomux = (struct iomuxc *)
 495                                 IOMUXC_BASE_ADDR;
 496         u32 reg = readl(&iomux->gpr[2]);
 497         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 498         writel(reg, &iomux->gpr[2]);
 499         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 500 }
 501
 502 static void enable_rgb(struct display_info_t const *dev)
 503 {
 504         imx_iomux_v3_setup_multiple_pads(
 505                 rgb_pads,
 506                  ARRAY_SIZE(rgb_pads));
 507         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 508 }
 509
 510 static struct display_info_t const displays[] = {{
 511         .bus    = -1,
 512         .addr   = 0,
 513         .pixfmt = IPU_PIX_FMT_RGB24,
 514         .detect = detect_hdmi,
 515         .enable = enable_hdmi,
 516         .mode   = {
 517                 .name           = "HDMI",
 518                 .refresh        = 60,
 519                 .xres           = 1024,
 520                 .yres           = 768,
 521                 .pixclock       = 15385,
 522                 .left_margin    = 220,
 523                 .right_margin   = 40,
 524                 .upper_margin   = 21,
 525                 .lower_margin   = 7,
 526                 .hsync_len      = 60,
 527                 .vsync_len      = 10,
 528                 .sync           = FB_SYNC_EXT,
 529                 .vmode          = FB_VMODE_NONINTERLACED
 530 } }, {
 531         .bus    = 2,
 532         .addr   = 0x4,
 533         .pixfmt = IPU_PIX_FMT_LVDS666,
 534         .detect = detect_i2c,
 535         .enable = enable_lvds,
 536         .mode   = {
 537                 .name           = "Hannstar-XGA",
 538                 .refresh        = 60,
 539                 .xres           = 1024,
 540                 .yres           = 768,
 541                 .pixclock       = 15385,
 542                 .left_margin    = 220,
 543                 .right_margin   = 40,
 544                 .upper_margin   = 21,
 545                 .lower_margin   = 7,
 546                 .hsync_len      = 60,
 547                 .vsync_len      = 10,
 548                 .sync           = FB_SYNC_EXT,
 549                 .vmode          = FB_VMODE_NONINTERLACED
 550 } }, {
 551         .bus    = 2,
 552         .addr   = 0x38,
 553         .pixfmt = IPU_PIX_FMT_LVDS666,
 554         .detect = detect_i2c,
 555         .enable = enable_lvds,
 556         .mode   = {
 557                 .name           = "wsvga-lvds",
 558                 .refresh        = 60,
 559                 .xres           = 1024,
 560                 .yres           = 600,
 561                 .pixclock       = 15385,
 562                 .left_margin    = 220,
 563                 .right_margin   = 40,
 564                 .upper_margin   = 21,
 565                 .lower_margin   = 7,
 566                 .hsync_len      = 60,
 567                 .vsync_len      = 10,
 568                 .sync           = FB_SYNC_EXT,
 569                 .vmode          = FB_VMODE_NONINTERLACED
 570 } }, {
 571         .bus    = 2,
 572         .addr   = 0x48,
 573         .pixfmt = IPU_PIX_FMT_RGB666,
 574         .detect = detect_i2c,
 575         .enable = enable_rgb,
 576         .mode   = {
 577                 .name           = "wvga-rgb",
 578                 .refresh        = 57,
 579                 .xres           = 800,
 580                 .yres           = 480,
 581                 .pixclock       = 37037,
 582                 .left_margin    = 40,
 583                 .right_margin   = 60,
 584                 .upper_margin   = 10,
 585                 .lower_margin   = 10,
 586                 .hsync_len      = 20,
 587                 .vsync_len      = 10,
 588                 .sync           = 0,
 589                 .vmode          = FB_VMODE_NONINTERLACED
 590 } } };
 591
 592 int board_video_skip(void)
 593 {
 594         int i;
 595         int ret;
 596         char const *panel = getenv("panel");
 597         if (!panel) {
 598                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 599                         struct display_info_t const *dev = displays+i;
 600                         if (dev->detect(dev)) {
 601                                 panel = dev->mode.name;
 602                                 printf("auto-detected panel %s\n", panel);
 603                                 break;
 604                         }
 605                 }
 606                 if (!panel) {
 607                         panel = displays[0].mode.name;
 608                         printf("No panel detected: default to %s\n", panel);
 609                 }
 610         } else {
 611                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 612                         if (!strcmp(panel, displays[i].mode.name))
 613                                 break;
 614                 }
 615         }
 616         if (i < ARRAY_SIZE(displays)) {
 617                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 618                                     displays[i].pixfmt);
 619                 if (!ret) {
 620                         displays[i].enable(displays+i);
 621                         printf("Display: %s (%ux%u)\n",
 622                                displays[i].mode.name,
 623                                displays[i].mode.xres,
 624                                displays[i].mode.yres);
 625                 } else
 626                         printf("LCD %s cannot be configured: %d\n",
 627                                displays[i].mode.name, ret);
 628         } else {
 629                 printf("unsupported panel %s\n", panel);
 630                 ret = -EINVAL;
 631         }
 632         return (0 != ret);
 633 }
 634
 635 static void setup_display(void)
 636 {
 637         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 638         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 639         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 640         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 641
 642         int reg;
 643
 644         /* Turn on LDB0,IPU,IPU DI0 clocks */
 645         reg = __raw_readl(&mxc_ccm->CCGR3);
 646         reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
 647                 |MXC_CCM_CCGR3_LDB_DI0_MASK;
 648         writel(reg, &mxc_ccm->CCGR3);
 649
 650         /* Turn on HDMI PHY clock */
 651         reg = __raw_readl(&mxc_ccm->CCGR2);
 652         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
 653                |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 654         writel(reg, &mxc_ccm->CCGR2);
 655
 656         /* clear HDMI PHY reset */
 657         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 658
 659         /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 660         writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 661         writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
 662
 663         /* set LDB0, LDB1 clk select to 011/011 */
 664         reg = readl(&mxc_ccm->cs2cdr);
 665         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 666                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 667         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 668               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 669         writel(reg, &mxc_ccm->cs2cdr);
 670
 671         reg = readl(&mxc_ccm->cscmr2);
 672         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 673         writel(reg, &mxc_ccm->cscmr2);
 674
 675         reg = readl(&mxc_ccm->chsccdr);
 676         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
 677                 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
 678                 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 679         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 680                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 681               |(CHSCCDR_PODF_DIVIDE_BY_3
 682                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 683               |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 684                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 685         writel(reg, &mxc_ccm->chsccdr);
 686
 687         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 688              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 689              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 690              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 691              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 692              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 693              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 694              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 695              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 696         writel(reg, &iomux->gpr[2]);
 697
 698         reg = readl(&iomux->gpr[3]);
 699         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 700             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 701                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 702         writel(reg, &iomux->gpr[3]);
 703
 704         /* backlights off until needed */
 705         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 706                                          ARRAY_SIZE(backlight_pads));
 707         gpio_direction_input(LVDS_BACKLIGHT_GP);
 708         gpio_direction_input(RGB_BACKLIGHT_GP);
 709 }
 710 #endif
 711
 712 int board_early_init_f(void)
 713 {
 714         setup_iomux_uart();
 715
 716         /* Disable wl1271 For Nitrogen6w */
 717         gpio_direction_input(WL12XX_WL_IRQ_GP);
 718         gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
 719         gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
 720
 721         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 722         setup_buttons();
 723
 724 #if defined(CONFIG_VIDEO_IPUV3)
 725         setup_display();
 726 #endif
 727         return 0;
 728 }
 729
 730 /*
 731  * Do not overwrite the console
 732  * Use always serial for U-Boot console
 733  */
 734 int overwrite_console(void)
 735 {
 736         return 1;
 737 }
 738
 739 int board_init(void)
 740 {
 741         /* address of boot parameters */
 742         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 743
 744 #ifdef CONFIG_MXC_SPI
 745         setup_spi();
 746 #endif
 747         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 748         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 749         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 750
 751 #ifdef CONFIG_CMD_SATA
 752         setup_sata();
 753 #endif
 754
 755         return 0;
 756 }
 757
 758 int checkboard(void)
 759 {
 760         if (gpio_get_value(WL12XX_WL_IRQ_GP))
 761                 puts("Board: Nitrogen6X\n");
 762         else
 763                 puts("Board: SABRE Lite\n");
 764
 765         return 0;
 766 }
 767
 768 struct button_key {
 769         char const      *name;
 770         unsigned        gpnum;
 771         char            ident;
 772 };
 773
 774 static struct button_key const buttons[] = {
 775         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 776         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 777         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 778         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 779         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 780         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 781 };
 782
 783 /*
 784  * generate a null-terminated string containing the buttons pressed
 785  * returns number of keys pressed
 786  */
 787 static int read_keys(char *buf)
 788 {
 789         int i, numpressed = 0;
 790         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 791                 if (!gpio_get_value(buttons[i].gpnum))
 792                         buf[numpressed++] = buttons[i].ident;
 793         }
 794         buf[numpressed] = '\0';
 795         return numpressed;
 796 }
 797
 798 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 799 {
 800         char envvalue[ARRAY_SIZE(buttons)+1];
 801         int numpressed = read_keys(envvalue);
 802         setenv("keybd", envvalue);
 803         return numpressed == 0;
 804 }
 805
 806 U_BOOT_CMD(
 807         kbd, 1, 1, do_kbd,
 808         "Tests for keypresses, sets 'keybd' environment variable",
 809         "Returns 0 (true) to shell if key is pressed."
 810 );
 811
 812 #ifdef CONFIG_PREBOOT
 813 static char const kbd_magic_prefix[] = "key_magic";
 814 static char const kbd_command_prefix[] = "key_cmd";
 815
 816 static void preboot_keys(void)
 817 {
 818         int numpressed;
 819         char keypress[ARRAY_SIZE(buttons)+1];
 820         numpressed = read_keys(keypress);
 821         if (numpressed) {
 822                 char *kbd_magic_keys = getenv("magic_keys");
 823                 char *suffix;
 824                 /*
 825                  * loop over all magic keys
 826                  */
 827                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 828                         char *keys;
 829                         char magic[sizeof(kbd_magic_prefix) + 1];
 830                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 831                         keys = getenv(magic);
 832                         if (keys) {
 833                                 if (!strcmp(keys, keypress))
 834                                         break;
 835                         }
 836                 }
 837                 if (*suffix) {
 838                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 839                         char *cmd;
 840                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 841                         cmd = getenv(cmd_name);
 842                         if (cmd) {
 843                                 setenv("preboot", cmd);
 844                                 return;
 845                         }
 846                 }
 847         }
 848 }
 849 #endif
 850
 851 #ifdef CONFIG_CMD_BMODE
 852 static const struct boot_mode board_boot_modes[] = {
 853         /* 4 bit bus width */
 854         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 855         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 856         {NULL,          0},
 857 };
 858 #endif
 859
 860 int misc_init_r(void)
 861 {
 862 #ifdef CONFIG_PREBOOT
 863         preboot_keys();
 864 #endif
 865
 866 #ifdef CONFIG_CMD_BMODE
 867         add_board_boot_modes(board_boot_modes);
 868 #endif
 869         return 0;
 870 }