board/boundary/nitrogen6x/nitrogen6x.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <malloc.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/imx-common/sata.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/video.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <micrel.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/mxc_hdmi.h>
  30 #include <i2c.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  40         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  45
  46 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  47         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  48
  49 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  58         PAD_CTL_SRE_SLOW)
  59
  60 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  62         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  63
  64 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  65
  66 int dram_init(void)
  67 {
  68         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  69
  70         return 0;
  71 }
  72
  73 iomux_v3_cfg_t const uart1_pads[] = {
  74         MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  75         MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  76 };
  77
  78 iomux_v3_cfg_t const uart2_pads[] = {
  79         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81 };
  82
  83 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  84
  85 /* I2C1, SGTL5000 */
  86 struct i2c_pads_info i2c_pad_info0 = {
  87         .scl = {
  88                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  89                 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  90                 .gp = IMX_GPIO_NR(3, 21)
  91         },
  92         .sda = {
  93                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  94                 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  95                 .gp = IMX_GPIO_NR(3, 28)
  96         }
  97 };
  98
  99 /* I2C2 Camera, MIPI */
 100 struct i2c_pads_info i2c_pad_info1 = {
 101         .scl = {
 102                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 103                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 104                 .gp = IMX_GPIO_NR(4, 12)
 105         },
 106         .sda = {
 107                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 108                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 109                 .gp = IMX_GPIO_NR(4, 13)
 110         }
 111 };
 112
 113 /* I2C3, J15 - RGB connector */
 114 struct i2c_pads_info i2c_pad_info2 = {
 115         .scl = {
 116                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 117                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
 118                 .gp = IMX_GPIO_NR(1, 5)
 119         },
 120         .sda = {
 121                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 122                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
 123                 .gp = IMX_GPIO_NR(7, 11)
 124         }
 125 };
 126
 127 static iomux_v3_cfg_t const usdhc2_pads[] = {
 128         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134 };
 135
 136 iomux_v3_cfg_t const usdhc3_pads[] = {
 137         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 144 };
 145
 146 iomux_v3_cfg_t const usdhc4_pads[] = {
 147         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 154 };
 155
 156 iomux_v3_cfg_t const enet_pads1[] = {
 157         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 158         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         /* pin 35 - 1 (PHY_AD2) on reset */
 167         MX6_PAD_RGMII_RXC__GPIO6_IO30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         /* pin 32 - 1 - (MODE0) all */
 169         MX6_PAD_RGMII_RD0__GPIO6_IO25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         /* pin 31 - 1 - (MODE1) all */
 171         MX6_PAD_RGMII_RD1__GPIO6_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         /* pin 28 - 1 - (MODE2) all */
 173         MX6_PAD_RGMII_RD2__GPIO6_IO28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         /* pin 27 - 1 - (MODE3) all */
 175         MX6_PAD_RGMII_RD3__GPIO6_IO29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 177         MX6_PAD_RGMII_RX_CTL__GPIO6_IO24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 178         /* pin 42 PHY nRST */
 179         MX6_PAD_EIM_D23__GPIO3_IO23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 180         MX6_PAD_ENET_RXD0__GPIO1_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 181 };
 182
 183 iomux_v3_cfg_t const enet_pads2[] = {
 184         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 185         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 186         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 187         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 188         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 189         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 190 };
 191
 192 static iomux_v3_cfg_t const misc_pads[] = {
 193         MX6_PAD_GPIO_1__USB_OTG_ID              | MUX_PAD_CTRL(WEAK_PULLUP),
 194         MX6_PAD_KEY_COL4__USB_OTG_OC            | MUX_PAD_CTRL(WEAK_PULLUP),
 195         MX6_PAD_EIM_D30__USB_H1_OC              | MUX_PAD_CTRL(WEAK_PULLUP),
 196         /* OTG Power enable */
 197         MX6_PAD_EIM_D22__GPIO3_IO22             | MUX_PAD_CTRL(OUTPUT_40OHM),
 198 };
 199
 200 /* wl1271 pads on nitrogen6x */
 201 iomux_v3_cfg_t const wl12xx_pads[] = {
 202         (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
 203                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 204         (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
 205                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 206         (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
 207                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 208 };
 209 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 210 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 211 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 212
 213 /* Button assignments for J14 */
 214 static iomux_v3_cfg_t const button_pads[] = {
 215         /* Menu */
 216         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 217         /* Back */
 218         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 219         /* Labelled Search (mapped to Power under Android) */
 220         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 221         /* Home */
 222         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 223         /* Volume Down */
 224         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 225         /* Volume Up */
 226         MX6_PAD_GPIO_18__GPIO7_IO13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 227 };
 228
 229 static void setup_iomux_enet(void)
 230 {
 231         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 232         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 233         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 234         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 235         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 236         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 237         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 238         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 239         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 240
 241         /* Need delay 10ms according to KSZ9021 spec */
 242         udelay(1000 * 10);
 243         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 244         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 245
 246         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 247 }
 248
 249 iomux_v3_cfg_t const usb_pads[] = {
 250         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 251 };
 252
 253 static void setup_iomux_uart(void)
 254 {
 255         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 256         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 257 }
 258
 259 #ifdef CONFIG_USB_EHCI_MX6
 260 int board_ehci_hcd_init(int port)
 261 {
 262         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 263
 264         /* Reset USB hub */
 265         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 266         mdelay(2);
 267         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 268
 269         return 0;
 270 }
 271
 272 int board_ehci_power(int port, int on)
 273 {
 274         if (port)
 275                 return 0;
 276         gpio_set_value(GP_USB_OTG_PWR, on);
 277         return 0;
 278 }
 279
 280 #endif
 281
 282 #ifdef CONFIG_FSL_ESDHC
 283 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 284         {USDHC3_BASE_ADDR},
 285         {USDHC4_BASE_ADDR},
 286 };
 287
 288 int board_mmc_getcd(struct mmc *mmc)
 289 {
 290         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 291         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 292                         IMX_GPIO_NR(2, 6);
 293
 294         gpio_direction_input(gp_cd);
 295         return !gpio_get_value(gp_cd);
 296 }
 297
 298 int board_mmc_init(bd_t *bis)
 299 {
 300         s32 status = 0;
 301         u32 index = 0;
 302
 303         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 304         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 305
 306         usdhc_cfg[0].max_bus_width = 4;
 307         usdhc_cfg[1].max_bus_width = 4;
 308
 309         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 310                 switch (index) {
 311                 case 0:
 312                         imx_iomux_v3_setup_multiple_pads(
 313                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 314                         break;
 315                 case 1:
 316                        imx_iomux_v3_setup_multiple_pads(
 317                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 318                        break;
 319                 default:
 320                        printf("Warning: you configured more USDHC controllers"
 321                                "(%d) then supported by the board (%d)\n",
 322                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 323                        return status;
 324                 }
 325
 326                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 327         }
 328
 329         return status;
 330 }
 331 #endif
 332
 333 #ifdef CONFIG_MXC_SPI
 334 iomux_v3_cfg_t const ecspi1_pads[] = {
 335         /* SS1 */
 336         MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
 337         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 338         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 339         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 340 };
 341
 342 void setup_spi(void)
 343 {
 344         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 345                                          ARRAY_SIZE(ecspi1_pads));
 346 }
 347 #endif
 348
 349 int board_phy_config(struct phy_device *phydev)
 350 {
 351         /* min rx data delay */
 352         ksz9021_phy_extended_write(phydev,
 353                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 354         /* min tx data delay */
 355         ksz9021_phy_extended_write(phydev,
 356                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 357         /* max rx/tx clock delay, min rx/tx control */
 358         ksz9021_phy_extended_write(phydev,
 359                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 360         if (phydev->drv->config)
 361                 phydev->drv->config(phydev);
 362
 363         return 0;
 364 }
 365
 366 int board_eth_init(bd_t *bis)
 367 {
 368         uint32_t base = IMX_FEC_BASE;
 369         struct mii_dev *bus = NULL;
 370         struct phy_device *phydev = NULL;
 371         int ret;
 372
 373         setup_iomux_enet();
 374
 375 #ifdef CONFIG_FEC_MXC
 376         bus = fec_get_miibus(base, -1);
 377         if (!bus)
 378                 return 0;
 379         /* scan phy 4,5,6,7 */
 380         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 381         if (!phydev) {
 382                 free(bus);
 383                 return 0;
 384         }
 385         printf("using phy at %d\n", phydev->addr);
 386         ret  = fec_probe(bis, -1, base, bus, phydev);
 387         if (ret) {
 388                 printf("FEC MXC: %s:failed\n", __func__);
 389                 free(phydev);
 390                 free(bus);
 391         }
 392 #endif
 393
 394 #ifdef CONFIG_CI_UDC
 395         /* For otg ethernet*/
 396         usb_eth_initialize(bis);
 397 #endif
 398         return 0;
 399 }
 400
 401 static void setup_buttons(void)
 402 {
 403         imx_iomux_v3_setup_multiple_pads(button_pads,
 404                                          ARRAY_SIZE(button_pads));
 405 }
 406
 407 #if defined(CONFIG_VIDEO_IPUV3)
 408
 409 static iomux_v3_cfg_t const backlight_pads[] = {
 410         /* Backlight on RGB connector: J15 */
 411         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 412 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 413
 414         /* Backlight on LVDS connector: J6 */
 415         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 416 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 417 };
 418
 419 static iomux_v3_cfg_t const rgb_pads[] = {
 420         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 421         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 422         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 423         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 424         MX6_PAD_DI0_PIN4__GPIO4_IO20,
 425         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 426         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 427         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 428         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 429         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 430         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 431         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 432         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 433         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 434         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 435         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 436         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 437         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 438         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 439         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 440         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 441         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 442         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 443         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 444         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 445         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 446         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 447         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 448         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 449 };
 450
 451 static void do_enable_hdmi(struct display_info_t const *dev)
 452 {
 453         imx_enable_hdmi_phy();
 454 }
 455
 456 static int detect_i2c(struct display_info_t const *dev)
 457 {
 458         return ((0 == i2c_set_bus_num(dev->bus))
 459                 &&
 460                 (0 == i2c_probe(dev->addr)));
 461 }
 462
 463 static void enable_lvds(struct display_info_t const *dev)
 464 {
 465         struct iomuxc *iomux = (struct iomuxc *)
 466                                 IOMUXC_BASE_ADDR;
 467         u32 reg = readl(&iomux->gpr[2]);
 468         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 469         writel(reg, &iomux->gpr[2]);
 470         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 471 }
 472
 473 static void enable_rgb(struct display_info_t const *dev)
 474 {
 475         imx_iomux_v3_setup_multiple_pads(
 476                 rgb_pads,
 477                  ARRAY_SIZE(rgb_pads));
 478         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 479 }
 480
 481 struct display_info_t const displays[] = {{
 482         .bus    = -1,
 483         .addr   = 0,
 484         .pixfmt = IPU_PIX_FMT_RGB24,
 485         .detect = detect_hdmi,
 486         .enable = do_enable_hdmi,
 487         .mode   = {
 488                 .name           = "HDMI",
 489                 .refresh        = 60,
 490                 .xres           = 1024,
 491                 .yres           = 768,
 492                 .pixclock       = 15385,
 493                 .left_margin    = 220,
 494                 .right_margin   = 40,
 495                 .upper_margin   = 21,
 496                 .lower_margin   = 7,
 497                 .hsync_len      = 60,
 498                 .vsync_len      = 10,
 499                 .sync           = FB_SYNC_EXT,
 500                 .vmode          = FB_VMODE_NONINTERLACED
 501 } }, {
 502         .bus    = 2,
 503         .addr   = 0x4,
 504         .pixfmt = IPU_PIX_FMT_LVDS666,
 505         .detect = detect_i2c,
 506         .enable = enable_lvds,
 507         .mode   = {
 508                 .name           = "Hannstar-XGA",
 509                 .refresh        = 60,
 510                 .xres           = 1024,
 511                 .yres           = 768,
 512                 .pixclock       = 15385,
 513                 .left_margin    = 220,
 514                 .right_margin   = 40,
 515                 .upper_margin   = 21,
 516                 .lower_margin   = 7,
 517                 .hsync_len      = 60,
 518                 .vsync_len      = 10,
 519                 .sync           = FB_SYNC_EXT,
 520                 .vmode          = FB_VMODE_NONINTERLACED
 521 } }, {
 522         .bus    = 2,
 523         .addr   = 0x38,
 524         .pixfmt = IPU_PIX_FMT_LVDS666,
 525         .detect = detect_i2c,
 526         .enable = enable_lvds,
 527         .mode   = {
 528                 .name           = "wsvga-lvds",
 529                 .refresh        = 60,
 530                 .xres           = 1024,
 531                 .yres           = 600,
 532                 .pixclock       = 15385,
 533                 .left_margin    = 220,
 534                 .right_margin   = 40,
 535                 .upper_margin   = 21,
 536                 .lower_margin   = 7,
 537                 .hsync_len      = 60,
 538                 .vsync_len      = 10,
 539                 .sync           = FB_SYNC_EXT,
 540                 .vmode          = FB_VMODE_NONINTERLACED
 541 } }, {
 542         .bus    = 2,
 543         .addr   = 0x48,
 544         .pixfmt = IPU_PIX_FMT_RGB666,
 545         .detect = detect_i2c,
 546         .enable = enable_rgb,
 547         .mode   = {
 548                 .name           = "wvga-rgb",
 549                 .refresh        = 57,
 550                 .xres           = 800,
 551                 .yres           = 480,
 552                 .pixclock       = 37037,
 553                 .left_margin    = 40,
 554                 .right_margin   = 60,
 555                 .upper_margin   = 10,
 556                 .lower_margin   = 10,
 557                 .hsync_len      = 20,
 558                 .vsync_len      = 10,
 559                 .sync           = 0,
 560                 .vmode          = FB_VMODE_NONINTERLACED
 561 } } };
 562 size_t display_count = ARRAY_SIZE(displays);
 563
 564 int board_cfb_skip(void)
 565 {
 566         return NULL != getenv("novideo");
 567 }
 568
 569 static void setup_display(void)
 570 {
 571         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 572         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 573         int reg;
 574
 575         enable_ipu_clock();
 576         imx_setup_hdmi();
 577         /* Turn on LDB0,IPU,IPU DI0 clocks */
 578         reg = __raw_readl(&mxc_ccm->CCGR3);
 579         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 580         writel(reg, &mxc_ccm->CCGR3);
 581
 582         /* set LDB0, LDB1 clk select to 011/011 */
 583         reg = readl(&mxc_ccm->cs2cdr);
 584         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 585                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 586         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 587               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 588         writel(reg, &mxc_ccm->cs2cdr);
 589
 590         reg = readl(&mxc_ccm->cscmr2);
 591         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 592         writel(reg, &mxc_ccm->cscmr2);
 593
 594         reg = readl(&mxc_ccm->chsccdr);
 595         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 596                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 597         writel(reg, &mxc_ccm->chsccdr);
 598
 599         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 600              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 601              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 602              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 603              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 604              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 605              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 606              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 607              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 608         writel(reg, &iomux->gpr[2]);
 609
 610         reg = readl(&iomux->gpr[3]);
 611         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 612                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 613             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 614                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 615         writel(reg, &iomux->gpr[3]);
 616
 617         /* backlights off until needed */
 618         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 619                                          ARRAY_SIZE(backlight_pads));
 620         gpio_direction_input(LVDS_BACKLIGHT_GP);
 621         gpio_direction_input(RGB_BACKLIGHT_GP);
 622 }
 623 #endif
 624
 625 /* wl1271 pads on nitrogen6x */
 626 static iomux_v3_cfg_t const init_pads[] = {
 627         /* WL12XX_WL_IRQ_GP */
 628         NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 629         /* WL12XX_WL_ENABLE_GP */
 630         NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 631         /* WL12XX_BT_ENABLE_GP */
 632         NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 633         /* USB otg power */
 634         NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 635         NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 636         NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 637         NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 638         NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 639 };
 640
 641 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 642
 643 static unsigned gpios_out_low[] = {
 644         /* Disable wl1271 */
 645         IMX_GPIO_NR(6, 15),     /* disable wireless */
 646         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 647         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 648         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 649         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 650 };
 651
 652 static unsigned gpios_out_high[] = {
 653         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 654         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 655 };
 656
 657 static void set_gpios(unsigned *p, int cnt, int val)
 658 {
 659         int i;
 660
 661         for (i = 0; i < cnt; i++)
 662                 gpio_direction_output(*p++, val);
 663 }
 664
 665 int board_early_init_f(void)
 666 {
 667         setup_iomux_uart();
 668
 669         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 670         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 671         gpio_direction_input(WL12XX_WL_IRQ_GP);
 672
 673         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 674         imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
 675         setup_buttons();
 676
 677 #if defined(CONFIG_VIDEO_IPUV3)
 678         setup_display();
 679 #endif
 680         return 0;
 681 }
 682
 683 /*
 684  * Do not overwrite the console
 685  * Use always serial for U-Boot console
 686  */
 687 int overwrite_console(void)
 688 {
 689         return 1;
 690 }
 691
 692 int board_init(void)
 693 {
 694         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 695
 696         clrsetbits_le32(&iomuxc_regs->gpr[1],
 697                         IOMUXC_GPR1_OTG_ID_MASK,
 698                         IOMUXC_GPR1_OTG_ID_GPIO1);
 699
 700         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 701
 702         /* address of boot parameters */
 703         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 704
 705 #ifdef CONFIG_MXC_SPI
 706         setup_spi();
 707 #endif
 708         imx_iomux_v3_setup_multiple_pads(
 709                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 710         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 711         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 712         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 713
 714 #ifdef CONFIG_CMD_SATA
 715         setup_sata();
 716 #endif
 717
 718         return 0;
 719 }
 720
 721 int checkboard(void)
 722 {
 723         if (gpio_get_value(WL12XX_WL_IRQ_GP))
 724                 puts("Board: Nitrogen6X\n");
 725         else
 726                 puts("Board: SABRE Lite\n");
 727
 728         return 0;
 729 }
 730
 731 struct button_key {
 732         char const      *name;
 733         unsigned        gpnum;
 734         char            ident;
 735 };
 736
 737 static struct button_key const buttons[] = {
 738         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 739         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 740         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 741         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 742         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 743         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 744 };
 745
 746 /*
 747  * generate a null-terminated string containing the buttons pressed
 748  * returns number of keys pressed
 749  */
 750 static int read_keys(char *buf)
 751 {
 752         int i, numpressed = 0;
 753         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 754                 if (!gpio_get_value(buttons[i].gpnum))
 755                         buf[numpressed++] = buttons[i].ident;
 756         }
 757         buf[numpressed] = '\0';
 758         return numpressed;
 759 }
 760
 761 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 762 {
 763         char envvalue[ARRAY_SIZE(buttons)+1];
 764         int numpressed = read_keys(envvalue);
 765         setenv("keybd", envvalue);
 766         return numpressed == 0;
 767 }
 768
 769 U_BOOT_CMD(
 770         kbd, 1, 1, do_kbd,
 771         "Tests for keypresses, sets 'keybd' environment variable",
 772         "Returns 0 (true) to shell if key is pressed."
 773 );
 774
 775 #ifdef CONFIG_PREBOOT
 776 static char const kbd_magic_prefix[] = "key_magic";
 777 static char const kbd_command_prefix[] = "key_cmd";
 778
 779 static void preboot_keys(void)
 780 {
 781         int numpressed;
 782         char keypress[ARRAY_SIZE(buttons)+1];
 783         numpressed = read_keys(keypress);
 784         if (numpressed) {
 785                 char *kbd_magic_keys = getenv("magic_keys");
 786                 char *suffix;
 787                 /*
 788                  * loop over all magic keys
 789                  */
 790                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 791                         char *keys;
 792                         char magic[sizeof(kbd_magic_prefix) + 1];
 793                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 794                         keys = getenv(magic);
 795                         if (keys) {
 796                                 if (!strcmp(keys, keypress))
 797                                         break;
 798                         }
 799                 }
 800                 if (*suffix) {
 801                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 802                         char *cmd;
 803                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 804                         cmd = getenv(cmd_name);
 805                         if (cmd) {
 806                                 setenv("preboot", cmd);
 807                                 return;
 808                         }
 809                 }
 810         }
 811 }
 812 #endif
 813
 814 #ifdef CONFIG_CMD_BMODE
 815 static const struct boot_mode board_boot_modes[] = {
 816         /* 4 bit bus width */
 817         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 818         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 819         {NULL,          0},
 820 };
 821 #endif
 822
 823 int misc_init_r(void)
 824 {
 825 #ifdef CONFIG_PREBOOT
 826         preboot_keys();
 827 #endif
 828
 829 #ifdef CONFIG_CMD_BMODE
 830         add_board_boot_modes(board_boot_modes);
 831 #endif
 832         return 0;
 833 }