2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/errno.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/sata.h>
21 #include <asm/imx-common/boot_mode.h>
22 #include <asm/imx-common/video.h>
24 #include <fsl_esdhc.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/mxc_hdmi.h>
34 DECLARE_GLOBAL_DATA_PTR;
35 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
54 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
56 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
58 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
59 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
62 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
64 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
66 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
70 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
75 static iomux_v3_cfg_t const uart1_pads[] = {
76 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 static iomux_v3_cfg_t const uart2_pads[] = {
81 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
88 static struct i2c_pads_info i2c_pad_info0 = {
90 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
91 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
92 .gp = IMX_GPIO_NR(3, 21)
95 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
96 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
97 .gp = IMX_GPIO_NR(3, 28)
101 /* I2C2 Camera, MIPI */
102 static struct i2c_pads_info i2c_pad_info1 = {
104 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
105 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
106 .gp = IMX_GPIO_NR(4, 12)
109 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
110 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
111 .gp = IMX_GPIO_NR(4, 13)
115 /* I2C3, J15 - RGB connector */
116 static struct i2c_pads_info i2c_pad_info2 = {
118 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
119 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
120 .gp = IMX_GPIO_NR(1, 5)
123 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
124 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
125 .gp = IMX_GPIO_NR(7, 11)
129 static iomux_v3_cfg_t const usdhc2_pads[] = {
130 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 static iomux_v3_cfg_t const usdhc3_pads[] = {
139 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
148 static iomux_v3_cfg_t const usdhc4_pads[] = {
149 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
158 static iomux_v3_cfg_t const enet_pads1[] = {
159 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
161 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
162 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
163 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
164 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 /* pin 35 - 1 (PHY_AD2) on reset */
169 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 /* pin 32 - 1 - (MODE0) all */
171 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 /* pin 31 - 1 - (MODE1) all */
173 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 /* pin 28 - 1 - (MODE2) all */
175 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 /* pin 27 - 1 - (MODE3) all */
177 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
178 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
179 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
180 /* pin 42 PHY nRST */
181 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
182 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
185 static iomux_v3_cfg_t const enet_pads2[] = {
186 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
187 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
188 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
189 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
190 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
191 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
194 static iomux_v3_cfg_t const misc_pads[] = {
195 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
196 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
197 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
198 /* OTG Power enable */
199 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
202 /* wl1271 pads on nitrogen6x */
203 static iomux_v3_cfg_t const wl12xx_pads[] = {
204 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
205 | MUX_PAD_CTRL(WEAK_PULLDOWN),
206 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
207 | MUX_PAD_CTRL(OUTPUT_40OHM),
208 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
209 | MUX_PAD_CTRL(OUTPUT_40OHM),
211 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
212 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
213 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
215 /* Button assignments for J14 */
216 static iomux_v3_cfg_t const button_pads[] = {
218 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
220 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
221 /* Labelled Search (mapped to Power under Android) */
222 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
224 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
226 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
228 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
231 static void setup_iomux_enet(void)
233 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
234 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
235 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
236 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
237 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
238 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
239 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
240 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
241 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
243 /* Need delay 10ms according to KSZ9021 spec */
245 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
246 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
248 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
249 udelay(100); /* Wait 100 us before using mii interface */
252 static iomux_v3_cfg_t const usb_pads[] = {
253 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
256 static void setup_iomux_uart(void)
258 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
259 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
262 #ifdef CONFIG_USB_EHCI_MX6
263 int board_ehci_hcd_init(int port)
265 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
268 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
270 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
275 int board_ehci_power(int port, int on)
279 gpio_set_value(GP_USB_OTG_PWR, on);
285 #ifdef CONFIG_FSL_ESDHC
286 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
291 int board_mmc_getcd(struct mmc *mmc)
293 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
294 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
297 gpio_direction_input(gp_cd);
298 return !gpio_get_value(gp_cd);
301 int board_mmc_init(bd_t *bis)
306 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
307 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
309 usdhc_cfg[0].max_bus_width = 4;
310 usdhc_cfg[1].max_bus_width = 4;
312 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
315 imx_iomux_v3_setup_multiple_pads(
316 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
319 imx_iomux_v3_setup_multiple_pads(
320 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
323 printf("Warning: you configured more USDHC controllers"
324 "(%d) then supported by the board (%d)\n",
325 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
329 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
336 #ifdef CONFIG_MXC_SPI
337 static iomux_v3_cfg_t const ecspi1_pads[] = {
339 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
340 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
341 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
342 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
345 static void setup_spi(void)
347 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
348 ARRAY_SIZE(ecspi1_pads));
352 int board_phy_config(struct phy_device *phydev)
354 /* min rx data delay */
355 ksz9021_phy_extended_write(phydev,
356 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
357 /* min tx data delay */
358 ksz9021_phy_extended_write(phydev,
359 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
360 /* max rx/tx clock delay, min rx/tx control */
361 ksz9021_phy_extended_write(phydev,
362 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
363 if (phydev->drv->config)
364 phydev->drv->config(phydev);
369 int board_eth_init(bd_t *bis)
371 uint32_t base = IMX_FEC_BASE;
372 struct mii_dev *bus = NULL;
373 struct phy_device *phydev = NULL;
378 #ifdef CONFIG_FEC_MXC
379 bus = fec_get_miibus(base, -1);
382 /* scan phy 4,5,6,7 */
383 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
388 printf("using phy at %d\n", phydev->addr);
389 ret = fec_probe(bis, -1, base, bus, phydev);
391 printf("FEC MXC: %s:failed\n", __func__);
398 /* For otg ethernet*/
399 usb_eth_initialize(bis);
404 static void setup_buttons(void)
406 imx_iomux_v3_setup_multiple_pads(button_pads,
407 ARRAY_SIZE(button_pads));
410 #if defined(CONFIG_VIDEO_IPUV3)
412 static iomux_v3_cfg_t const backlight_pads[] = {
413 /* Backlight on RGB connector: J15 */
414 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
415 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
417 /* Backlight on LVDS connector: J6 */
418 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
419 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
422 static iomux_v3_cfg_t const rgb_pads[] = {
423 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
424 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
425 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
426 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
427 MX6_PAD_DI0_PIN4__GPIO4_IO20,
428 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
429 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
430 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
431 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
432 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
433 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
434 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
435 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
436 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
437 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
438 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
439 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
440 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
441 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
442 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
443 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
444 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
445 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
446 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
447 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
448 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
449 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
450 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
451 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
454 static void do_enable_hdmi(struct display_info_t const *dev)
456 imx_enable_hdmi_phy();
459 static int detect_i2c(struct display_info_t const *dev)
461 return ((0 == i2c_set_bus_num(dev->bus))
463 (0 == i2c_probe(dev->addr)));
466 static void enable_lvds(struct display_info_t const *dev)
468 struct iomuxc *iomux = (struct iomuxc *)
470 u32 reg = readl(&iomux->gpr[2]);
471 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
472 writel(reg, &iomux->gpr[2]);
473 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
476 static void enable_rgb(struct display_info_t const *dev)
478 imx_iomux_v3_setup_multiple_pads(
480 ARRAY_SIZE(rgb_pads));
481 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
484 struct display_info_t const displays[] = {{
487 .pixfmt = IPU_PIX_FMT_RGB24,
488 .detect = detect_hdmi,
489 .enable = do_enable_hdmi,
503 .vmode = FB_VMODE_NONINTERLACED
507 .pixfmt = IPU_PIX_FMT_LVDS666,
508 .detect = detect_i2c,
509 .enable = enable_lvds,
511 .name = "Hannstar-XGA",
523 .vmode = FB_VMODE_NONINTERLACED
527 .pixfmt = IPU_PIX_FMT_LVDS666,
528 .detect = detect_i2c,
529 .enable = enable_lvds,
531 .name = "wsvga-lvds",
543 .vmode = FB_VMODE_NONINTERLACED
547 .pixfmt = IPU_PIX_FMT_RGB666,
548 .detect = detect_i2c,
549 .enable = enable_rgb,
563 .vmode = FB_VMODE_NONINTERLACED
565 size_t display_count = ARRAY_SIZE(displays);
567 int board_cfb_skip(void)
569 return NULL != getenv("novideo");
572 static void setup_display(void)
574 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
575 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
580 /* Turn on LDB0,IPU,IPU DI0 clocks */
581 reg = __raw_readl(&mxc_ccm->CCGR3);
582 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
583 writel(reg, &mxc_ccm->CCGR3);
585 /* set LDB0, LDB1 clk select to 011/011 */
586 reg = readl(&mxc_ccm->cs2cdr);
587 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
588 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
589 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
590 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
591 writel(reg, &mxc_ccm->cs2cdr);
593 reg = readl(&mxc_ccm->cscmr2);
594 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
595 writel(reg, &mxc_ccm->cscmr2);
597 reg = readl(&mxc_ccm->chsccdr);
598 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
599 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
600 writel(reg, &mxc_ccm->chsccdr);
602 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
603 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
604 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
605 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
606 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
607 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
608 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
609 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
610 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
611 writel(reg, &iomux->gpr[2]);
613 reg = readl(&iomux->gpr[3]);
614 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
615 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
616 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
617 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
618 writel(reg, &iomux->gpr[3]);
620 /* backlights off until needed */
621 imx_iomux_v3_setup_multiple_pads(backlight_pads,
622 ARRAY_SIZE(backlight_pads));
623 gpio_direction_input(LVDS_BACKLIGHT_GP);
624 gpio_direction_input(RGB_BACKLIGHT_GP);
628 static iomux_v3_cfg_t const init_pads[] = {
629 /* SGTL5000 sys_mclk */
630 NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
632 /* J5 - Camera MCLK */
633 NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
635 /* wl1271 pads on nitrogen6x */
636 /* WL12XX_WL_IRQ_GP */
637 NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
638 /* WL12XX_WL_ENABLE_GP */
639 NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
640 /* WL12XX_BT_ENABLE_GP */
641 NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
643 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
644 NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
645 NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
646 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
647 NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
650 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
652 static unsigned gpios_out_low[] = {
654 IMX_GPIO_NR(6, 15), /* disable wireless */
655 IMX_GPIO_NR(6, 16), /* disable bluetooth */
656 IMX_GPIO_NR(3, 22), /* disable USB otg power */
657 IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
658 IMX_GPIO_NR(1, 8), /* ov5642 reset */
661 static unsigned gpios_out_high[] = {
662 IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
663 IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
666 static void set_gpios(unsigned *p, int cnt, int val)
670 for (i = 0; i < cnt; i++)
671 gpio_direction_output(*p++, val);
674 int board_early_init_f(void)
678 set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
679 set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
680 gpio_direction_input(WL12XX_WL_IRQ_GP);
682 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
683 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
686 #if defined(CONFIG_VIDEO_IPUV3)
693 * Do not overwrite the console
694 * Use always serial for U-Boot console
696 int overwrite_console(void)
703 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
705 clrsetbits_le32(&iomuxc_regs->gpr[1],
706 IOMUXC_GPR1_OTG_ID_MASK,
707 IOMUXC_GPR1_OTG_ID_GPIO1);
709 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
711 /* address of boot parameters */
712 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
714 #ifdef CONFIG_MXC_SPI
717 imx_iomux_v3_setup_multiple_pads(
718 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
719 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
720 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
721 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
723 #ifdef CONFIG_CMD_SATA
732 if (gpio_get_value(WL12XX_WL_IRQ_GP))
733 puts("Board: Nitrogen6X\n");
735 puts("Board: SABRE Lite\n");
746 static struct button_key const buttons[] = {
747 {"back", IMX_GPIO_NR(2, 2), 'B'},
748 {"home", IMX_GPIO_NR(2, 4), 'H'},
749 {"menu", IMX_GPIO_NR(2, 1), 'M'},
750 {"search", IMX_GPIO_NR(2, 3), 'S'},
751 {"volup", IMX_GPIO_NR(7, 13), 'V'},
752 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
756 * generate a null-terminated string containing the buttons pressed
757 * returns number of keys pressed
759 static int read_keys(char *buf)
761 int i, numpressed = 0;
762 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
763 if (!gpio_get_value(buttons[i].gpnum))
764 buf[numpressed++] = buttons[i].ident;
766 buf[numpressed] = '\0';
770 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
772 char envvalue[ARRAY_SIZE(buttons)+1];
773 int numpressed = read_keys(envvalue);
774 setenv("keybd", envvalue);
775 return numpressed == 0;
780 "Tests for keypresses, sets 'keybd' environment variable",
781 "Returns 0 (true) to shell if key is pressed."
784 #ifdef CONFIG_PREBOOT
785 static char const kbd_magic_prefix[] = "key_magic";
786 static char const kbd_command_prefix[] = "key_cmd";
788 static void preboot_keys(void)
791 char keypress[ARRAY_SIZE(buttons)+1];
792 numpressed = read_keys(keypress);
794 char *kbd_magic_keys = getenv("magic_keys");
797 * loop over all magic keys
799 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
801 char magic[sizeof(kbd_magic_prefix) + 1];
802 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
803 keys = getenv(magic);
805 if (!strcmp(keys, keypress))
810 char cmd_name[sizeof(kbd_command_prefix) + 1];
812 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
813 cmd = getenv(cmd_name);
815 setenv("preboot", cmd);
823 #ifdef CONFIG_CMD_BMODE
824 static const struct boot_mode board_boot_modes[] = {
825 /* 4 bit bus width */
826 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
827 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
832 int misc_init_r(void)
834 #ifdef CONFIG_PREBOOT
838 #ifdef CONFIG_CMD_BMODE
839 add_board_boot_modes(board_boot_modes);