board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <fsl_esdhc.h>
  14 #include <miiphy.h>
  15 #include <netdev.h>
  16 #include <fdt_support.h>
  17 #include <sata.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/iomux.h>
  21 #include <asm/imx-common/mxc_i2c.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/io.h>
  24 #include <asm/gpio.h>
  25 #include <dm/platform_data/serial_mxc.h>
  26 #include "common.h"
  27 #include "../common/eeprom.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #ifdef CONFIG_DWC_AHSATA
  32 static int cm_fx6_issd_gpios[] = {
  33         /* The order of the GPIOs in the array is important! */
  34         CM_FX6_SATA_LDO_EN,
  35         CM_FX6_SATA_PHY_SLP,
  36         CM_FX6_SATA_NRSTDLY,
  37         CM_FX6_SATA_PWREN,
  38         CM_FX6_SATA_NSTANDBY1,
  39         CM_FX6_SATA_NSTANDBY2,
  40 };
  41
  42 static void cm_fx6_sata_power(int on)
  43 {
  44         int i;
  45
  46         if (!on) { /* tell the iSSD that the power will be removed */
  47                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
  48                 mdelay(10);
  49         }
  50
  51         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  52                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
  53                 udelay(100);
  54         }
  55
  56         if (!on) /* for compatibility lower the power loss interrupt */
  57                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  58 }
  59
  60 static iomux_v3_cfg_t const sata_pads[] = {
  61         /* SATA PWR */
  62         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  63         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  64         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  65         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  66         /* SATA CTRL */
  67         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  68         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  70         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  71         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  72 };
  73
  74 static int cm_fx6_setup_issd(void)
  75 {
  76         int ret, i;
  77
  78         SETUP_IOMUX_PADS(sata_pads);
  79
  80         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  81                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
  82                 if (ret)
  83                         return ret;
  84         }
  85
  86         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
  87         if (ret)
  88                 return ret;
  89
  90         return 0;
  91 }
  92
  93 #define CM_FX6_SATA_INIT_RETRIES        10
  94 int sata_initialize(void)
  95 {
  96         int err, i;
  97
  98         /* Make sure this gpio has logical 0 value */
  99         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 100         udelay(100);
 101         cm_fx6_sata_power(1);
 102
 103         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 104                 err = setup_sata();
 105                 if (err) {
 106                         printf("SATA setup failed: %d\n", err);
 107                         return err;
 108                 }
 109
 110                 udelay(100);
 111
 112                 err = __sata_initialize();
 113                 if (!err)
 114                         break;
 115
 116                 /* There is no device on the SATA port */
 117                 if (sata_port_status(0, 0) == 0)
 118                         break;
 119
 120                 /* There's a device, but link not established. Retry */
 121         }
 122
 123         return err;
 124 }
 125
 126 int sata_stop(void)
 127 {
 128         __sata_stop();
 129         cm_fx6_sata_power(0);
 130         mdelay(250);
 131
 132         return 0;
 133 }
 134 #else
 135 static int cm_fx6_setup_issd(void) { return 0; }
 136 #endif
 137
 138 #ifdef CONFIG_SYS_I2C_MXC
 139 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 140                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 141                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 142
 143 I2C_PADS(i2c0_pads,
 144          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 145          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 146          IMX_GPIO_NR(3, 21),
 147          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 148          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 149          IMX_GPIO_NR(3, 28));
 150
 151 I2C_PADS(i2c1_pads,
 152          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 153          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 154          IMX_GPIO_NR(4, 12),
 155          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 156          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 157          IMX_GPIO_NR(4, 13));
 158
 159 I2C_PADS(i2c2_pads,
 160          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 161          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 162          IMX_GPIO_NR(1, 3),
 163          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 164          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 165          IMX_GPIO_NR(1, 6));
 166
 167
 168 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 169 {
 170         int ret;
 171
 172         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 173         if (ret)
 174                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 175
 176         return ret;
 177 }
 178
 179 static int cm_fx6_setup_i2c(void)
 180 {
 181         int ret = 0, err;
 182
 183         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 184         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 185         if (err)
 186                 ret = err;
 187         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 188         if (err)
 189                 ret = err;
 190         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 191         if (err)
 192                 ret = err;
 193
 194         return ret;
 195 }
 196 #else
 197 static int cm_fx6_setup_i2c(void) { return 0; }
 198 #endif
 199
 200 #ifdef CONFIG_USB_EHCI_MX6
 201 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 202                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 203                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 204 #define MX6_USBNC_BASEADDR      0x2184800
 205 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 206
 207 static int cm_fx6_setup_usb_host(void)
 208 {
 209         int err;
 210
 211         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 212         if (err)
 213                 return err;
 214
 215         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 216         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 217
 218         return 0;
 219 }
 220
 221 static int cm_fx6_setup_usb_otg(void)
 222 {
 223         int err;
 224         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 225
 226         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 227         if (err) {
 228                 printf("USB OTG pwr gpio request failed: %d\n", err);
 229                 return err;
 230         }
 231
 232         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 233         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 234                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 235         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 236         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 237         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 238 }
 239
 240 int board_ehci_hcd_init(int port)
 241 {
 242         int ret;
 243         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 244
 245         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 246         if (port != 1)
 247                 return 0;
 248
 249         /* Set PWR polarity to match power switch's enable polarity */
 250         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 251         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 252         if (ret)
 253                 return ret;
 254
 255         udelay(10);
 256         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 257         if (ret)
 258                 return ret;
 259
 260         mdelay(1);
 261
 262         return 0;
 263 }
 264
 265 int board_ehci_power(int port, int on)
 266 {
 267         if (port == 0)
 268                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 269
 270         return 0;
 271 }
 272 #else
 273 static int cm_fx6_setup_usb_otg(void) { return 0; }
 274 static int cm_fx6_setup_usb_host(void) { return 0; }
 275 #endif
 276
 277 #ifdef CONFIG_FEC_MXC
 278 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 279                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 280
 281 static int mx6_rgmii_rework(struct phy_device *phydev)
 282 {
 283         unsigned short val;
 284
 285         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 286          * which cause ethernet link down/up issue, so disable SmartEEE
 287          */
 288         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 289         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 290         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 291         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 292         val &= ~(0x1 << 8);
 293         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 294
 295         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 296         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 297         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 298         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 299
 300         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 301         val &= 0xffe3;
 302         val |= 0x18;
 303         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 304
 305         /* introduce tx clock delay */
 306         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 307         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 308         val |= 0x0100;
 309         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 310
 311         return 0;
 312 }
 313
 314 int board_phy_config(struct phy_device *phydev)
 315 {
 316         mx6_rgmii_rework(phydev);
 317
 318         if (phydev->drv->config)
 319                 return phydev->drv->config(phydev);
 320
 321         return 0;
 322 }
 323
 324 static iomux_v3_cfg_t const enet_pads[] = {
 325         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 326         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 327         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 328         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 329         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 330         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 331         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 332         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 333         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 334         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 335         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 336         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 337         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 338         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 339         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 340         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 341                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 342         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 343                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 344         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 345                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 346 };
 347
 348 static int handle_mac_address(void)
 349 {
 350         unsigned char enetaddr[6];
 351         int rc;
 352
 353         rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 354         if (rc)
 355                 return 0;
 356
 357         rc = cl_eeprom_read_mac_addr(enetaddr);
 358         if (rc)
 359                 return rc;
 360
 361         if (!is_valid_ether_addr(enetaddr))
 362                 return -1;
 363
 364         return eth_setenv_enetaddr("ethaddr", enetaddr);
 365 }
 366
 367 int board_eth_init(bd_t *bis)
 368 {
 369         int err;
 370
 371         err = handle_mac_address();
 372         if (err)
 373                 puts("No MAC address found\n");
 374
 375         SETUP_IOMUX_PADS(enet_pads);
 376         /* phy reset */
 377         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 378         if (err)
 379                 printf("Etnernet NRST gpio request failed: %d\n", err);
 380         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 381         udelay(500);
 382         gpio_set_value(CM_FX6_ENET_NRST, 1);
 383         enable_enet_clk(1);
 384         return cpu_eth_init(bis);
 385 }
 386 #endif
 387
 388 #ifdef CONFIG_NAND_MXS
 389 static iomux_v3_cfg_t const nand_pads[] = {
 390         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 391         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 392         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 393         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 394         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 395         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 396         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 397         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 398         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 399         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 400         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 401         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 402         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 403         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 404 };
 405
 406 static void cm_fx6_setup_gpmi_nand(void)
 407 {
 408         SETUP_IOMUX_PADS(nand_pads);
 409         /* Enable clock roots */
 410         enable_usdhc_clk(1, 3);
 411         enable_usdhc_clk(1, 4);
 412
 413         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 414                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 415                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 416 }
 417 #else
 418 static void cm_fx6_setup_gpmi_nand(void) {}
 419 #endif
 420
 421 #ifdef CONFIG_FSL_ESDHC
 422 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 423         {USDHC1_BASE_ADDR},
 424         {USDHC2_BASE_ADDR},
 425         {USDHC3_BASE_ADDR},
 426 };
 427
 428 static enum mxc_clock usdhc_clk[3] = {
 429         MXC_ESDHC_CLK,
 430         MXC_ESDHC2_CLK,
 431         MXC_ESDHC3_CLK,
 432 };
 433
 434 int board_mmc_init(bd_t *bis)
 435 {
 436         int i;
 437
 438         cm_fx6_set_usdhc_iomux();
 439         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 440                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 441                 usdhc_cfg[i].max_bus_width = 4;
 442                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 443                 enable_usdhc_clk(1, i);
 444         }
 445
 446         return 0;
 447 }
 448 #endif
 449
 450 #ifdef CONFIG_MXC_SPI
 451 int cm_fx6_setup_ecspi(void)
 452 {
 453         cm_fx6_set_ecspi_iomux();
 454         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 455 }
 456 #else
 457 int cm_fx6_setup_ecspi(void) { return 0; }
 458 #endif
 459
 460 #ifdef CONFIG_OF_BOARD_SETUP
 461 int ft_board_setup(void *blob, bd_t *bd)
 462 {
 463         uint8_t enetaddr[6];
 464
 465         /* MAC addr */
 466         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 467                 fdt_find_and_setprop(blob, "/fec", "local-mac-address",
 468                                      enetaddr, 6, 1);
 469         }
 470
 471         return 0;
 472 }
 473 #endif
 474
 475 int board_init(void)
 476 {
 477         int ret;
 478
 479         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 480         cm_fx6_setup_gpmi_nand();
 481
 482         ret = cm_fx6_setup_ecspi();
 483         if (ret)
 484                 printf("Warning: ECSPI setup failed: %d\n", ret);
 485
 486         ret = cm_fx6_setup_usb_otg();
 487         if (ret)
 488                 printf("Warning: USB OTG setup failed: %d\n", ret);
 489
 490         ret = cm_fx6_setup_usb_host();
 491         if (ret)
 492                 printf("Warning: USB host setup failed: %d\n", ret);
 493
 494         /*
 495          * cm-fx6 may have iSSD not assembled and in this case it has
 496          * bypasses for a (m)SATA socket on the baseboard. The socketed
 497          * device is not controlled by those GPIOs. So just print a warning
 498          * if the setup fails.
 499          */
 500         ret = cm_fx6_setup_issd();
 501         if (ret)
 502                 printf("Warning: iSSD setup failed: %d\n", ret);
 503
 504         /* Warn on failure but do not abort boot */
 505         ret = cm_fx6_setup_i2c();
 506         if (ret)
 507                 printf("Warning: I2C setup failed: %d\n", ret);
 508
 509         return 0;
 510 }
 511
 512 int checkboard(void)
 513 {
 514         puts("Board: CM-FX6\n");
 515         return 0;
 516 }
 517
 518 void dram_init_banksize(void)
 519 {
 520         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 521         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 522
 523         switch (gd->ram_size) {
 524         case 0x10000000: /* DDR_16BIT_256MB */
 525                 gd->bd->bi_dram[0].size = 0x10000000;
 526                 gd->bd->bi_dram[1].size = 0;
 527                 break;
 528         case 0x20000000: /* DDR_32BIT_512MB */
 529                 gd->bd->bi_dram[0].size = 0x20000000;
 530                 gd->bd->bi_dram[1].size = 0;
 531                 break;
 532         case 0x40000000:
 533                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 534                         gd->bd->bi_dram[0].size = 0x20000000;
 535                         gd->bd->bi_dram[1].size = 0x20000000;
 536                 } else { /* DDR_64BIT_1GB */
 537                         gd->bd->bi_dram[0].size = 0x40000000;
 538                         gd->bd->bi_dram[1].size = 0;
 539                 }
 540                 break;
 541         case 0x80000000: /* DDR_64BIT_2GB */
 542                 gd->bd->bi_dram[0].size = 0x40000000;
 543                 gd->bd->bi_dram[1].size = 0x40000000;
 544                 break;
 545         case 0xEFF00000: /* DDR_64BIT_4GB */
 546                 gd->bd->bi_dram[0].size = 0x70000000;
 547                 gd->bd->bi_dram[1].size = 0x7FF00000;
 548                 break;
 549         }
 550 }
 551
 552 int dram_init(void)
 553 {
 554         gd->ram_size = imx_ddr_size();
 555         switch (gd->ram_size) {
 556         case 0x10000000:
 557         case 0x20000000:
 558         case 0x40000000:
 559         case 0x80000000:
 560                 break;
 561         case 0xF0000000:
 562                 gd->ram_size -= 0x100000;
 563                 break;
 564         default:
 565                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 566                 return -1;
 567         }
 568
 569         return 0;
 570 }
 571
 572 u32 get_board_rev(void)
 573 {
 574         return cl_eeprom_get_board_rev();
 575 }
 576
 577 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 578         .reg = (struct mxc_uart *)UART4_BASE,
 579 };
 580
 581 U_BOOT_DEVICE(cm_fx6_serial) = {
 582         .name   = "serial_mxc",
 583         .platdata = &cm_fx6_mxc_serial_plat,
 584 };