board/denx/m53evk/m53evk.c

   1 /*
   2  * DENX M53 module
   3  *
   4  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/iomux-mx53.h>
  32 #include <asm/arch/spl.h>
  33 #include <asm/errno.h>
  34 #include <netdev.h>
  35 #include <i2c.h>
  36 #include <mmc.h>
  37 #include <spl.h>
  38 #include <fsl_esdhc.h>
  39 #include <asm/gpio.h>
  40 #include <usb/ehci-fsl.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 int dram_init(void)
  45 {
  46         u32 size1, size2;
  47
  48         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  49         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  50
  51         gd->ram_size = size1 + size2;
  52
  53         return 0;
  54 }
  55 void dram_init_banksize(void)
  56 {
  57         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  58         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  59
  60         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  61         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  62 }
  63
  64 static void setup_iomux_uart(void)
  65 {
  66         static const iomux_v3_cfg_t uart_pads[] = {
  67                 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  68                 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  69         };
  70
  71         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  72 }
  73
  74 #ifdef CONFIG_USB_EHCI_MX5
  75 int board_ehci_hcd_init(int port)
  76 {
  77         if (port == 0) {
  78                 /* USB OTG PWRON */
  79                 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
  80                                         PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
  81                 gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
  82
  83                 /* USB OTG Over Current */
  84                 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
  85         } else if (port == 1) {
  86                 /* USB Host PWRON */
  87                 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
  88                                         PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
  89                 gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
  90
  91                 /* USB Host Over Current */
  92                 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
  93         }
  94
  95         return 0;
  96 }
  97 #endif
  98
  99 static void setup_iomux_fec(void)
 100 {
 101         static const iomux_v3_cfg_t fec_pads[] = {
 102                 /* MDIO pads */
 103                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
 104                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
 105                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
 106
 107                 /* FEC 0 pads */
 108                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 109                                 PAD_CTL_HYS | PAD_CTL_PKE),
 110                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 111                                 PAD_CTL_HYS | PAD_CTL_PKE),
 112                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 113                                 PAD_CTL_HYS | PAD_CTL_PKE),
 114                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 115                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 116                                 PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 118                                 PAD_CTL_HYS | PAD_CTL_PKE),
 119                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 120                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 121
 122                 /* FEC 1 pads */
 123                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 124                                 PAD_CTL_HYS | PAD_CTL_PKE),
 125                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 126                                 PAD_CTL_HYS | PAD_CTL_PKE),
 127                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 128                                 PAD_CTL_HYS | PAD_CTL_PKE),
 129                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 130                                 PAD_CTL_HYS | PAD_CTL_PKE),
 131                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 132                                 PAD_CTL_HYS | PAD_CTL_PKE),
 133                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 134                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 135                                 PAD_CTL_HYS | PAD_CTL_PKE),
 136                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 137         };
 138
 139         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 140 }
 141
 142 #ifdef CONFIG_FSL_ESDHC
 143 struct fsl_esdhc_cfg esdhc_cfg = {
 144         MMC_SDHC1_BASE_ADDR,
 145 };
 146
 147 int board_mmc_getcd(struct mmc *mmc)
 148 {
 149         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 150         gpio_direction_input(IMX_GPIO_NR(1, 1));
 151
 152         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 153 }
 154
 155 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 156                                  PAD_CTL_PUS_100K_UP)
 157 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 158                                  PAD_CTL_DSE_HIGH)
 159
 160 int board_mmc_init(bd_t *bis)
 161 {
 162         static const iomux_v3_cfg_t sd1_pads[] = {
 163                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 164                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 165                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 166                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 167                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 168                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 169                 MX53_PAD_EIM_DA13__GPIO3_13,
 170
 171                 MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
 172         };
 173
 174         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 175
 176         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 177
 178         /* GPIO 2_31 is SD power */
 179         gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
 180
 181         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 182 }
 183 #endif
 184
 185 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 186                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 187
 188 static void setup_iomux_i2c(void)
 189 {
 190         static const iomux_v3_cfg_t i2c_pads[] = {
 191                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 192                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 193         };
 194
 195         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 196 }
 197
 198 static void setup_iomux_nand(void)
 199 {
 200         static const iomux_v3_cfg_t nand_pads[] = {
 201                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 202                                 PAD_CTL_DSE_HIGH),
 203                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 204                                 PAD_CTL_DSE_HIGH),
 205                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 206                                 PAD_CTL_DSE_HIGH),
 207                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 208                                 PAD_CTL_DSE_HIGH),
 209                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 210                                 PAD_CTL_PUS_100K_UP),
 211                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 212                                 PAD_CTL_PUS_100K_UP),
 213                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 214                                 PAD_CTL_DSE_HIGH),
 215                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 216                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 217                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 218                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 219                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 220                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 221                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 222                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 223                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 224                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 225                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 226                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 227                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 228                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 229                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 230                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 231         };
 232
 233         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 234 }
 235
 236 static void m53_set_clock(void)
 237 {
 238         int ret;
 239         const uint32_t ref_clk = MXC_HCLK;
 240         const uint32_t dramclk = 400;
 241         uint32_t cpuclk;
 242
 243         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 244                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 245         gpio_direction_input(IMX_GPIO_NR(4, 0));
 246
 247         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 248         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 249
 250         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 251         if (ret)
 252                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 253
 254         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 255         if (ret) {
 256                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 257                         dramclk);
 258         }
 259
 260         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 261         if (ret)
 262                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 263 }
 264
 265 static void m53_set_nand(void)
 266 {
 267         u32 i;
 268
 269         /* NAND flash is muxed on ATA pins */
 270         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 271
 272         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 273         for (i = 0x4; i < 0x94; i += 0x18) {
 274                 clrbits_le32(WEIM_BASE_ADDR + i,
 275                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 276         }
 277
 278         mxc_set_clock(0, 33, MXC_NFC_CLK);
 279         enable_nfc_clk(1);
 280 }
 281
 282 int board_early_init_f(void)
 283 {
 284         setup_iomux_uart();
 285         setup_iomux_fec();
 286         setup_iomux_i2c();
 287         setup_iomux_nand();
 288
 289         m53_set_clock();
 290
 291         mxc_set_sata_internal_clock();
 292
 293         /* NAND clock @ 33MHz */
 294         m53_set_nand();
 295
 296         return 0;
 297 }
 298
 299 int board_init(void)
 300 {
 301         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 302
 303         return 0;
 304 }
 305
 306 int checkboard(void)
 307 {
 308         puts("Board: DENX M53EVK\n");
 309
 310         return 0;
 311 }
 312
 313 /*
 314  * NAND SPL
 315  */
 316 #ifdef CONFIG_SPL_BUILD
 317 void spl_board_init(void)
 318 {
 319         setup_iomux_nand();
 320         m53_set_clock();
 321         m53_set_nand();
 322 }
 323
 324 u32 spl_boot_device(void)
 325 {
 326         return BOOT_DEVICE_NAND;
 327 }
 328 #endif