board/esd/cpci750/mv_eth.h

   1 /*
   2  * (C) Copyright 2003
   3  * Ingo Assmus <ingo.assmus@keymile.com>
   4  *
   5  * based on - Driver for MV64360X ethernet ports
   6  * Copyright (C) 2002 rabeeh@galileo.co.il
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * mv_eth.h - header file for the polled mode GT ethernet driver
  13  */
  14
  15 #ifndef __DB64360_ETH_H__
  16 #define __DB64360_ETH_H__
  17
  18 #include <asm/types.h>
  19 #include <asm/io.h>
  20 #include <asm/byteorder.h>
  21 #include <common.h>
  22 #include <net.h>
  23 #include "mv_regs.h"
  24 #include <asm/errno.h>
  25
  26
  27 /*************************************************************************
  28 **************************************************************************
  29 **************************************************************************
  30 *  The first part is the high level driver of the gigE ethernet ports.   *
  31 **************************************************************************
  32 **************************************************************************
  33 *************************************************************************/
  34 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
  35 #ifndef MAX_SKB_FRAGS
  36 #define MAX_SKB_FRAGS 0
  37 #endif
  38
  39 /* Port attributes */
  40 /*#define MAX_RX_QUEUE_NUM      8*/
  41 /*#define MAX_TX_QUEUE_NUM      8*/
  42 #define MAX_RX_QUEUE_NUM        1
  43 #define MAX_TX_QUEUE_NUM        1
  44
  45
  46 /* Use one TX queue and one RX queue */
  47 #define MV64360_TX_QUEUE_NUM 1
  48 #define MV64360_RX_QUEUE_NUM 1
  49
  50 /*
  51  * Number of RX / TX descriptors on RX / TX rings.
  52  * Note that allocating RX descriptors is done by allocating the RX
  53  * ring AND a preallocated RX buffers (skb's) for each descriptor.
  54  * The TX descriptors only allocates the TX descriptors ring,
  55  * with no pre allocated TX buffers (skb's are allocated by higher layers.
  56  */
  57
  58 /* Default TX ring size is 10 descriptors */
  59 #ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
  60 #define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
  61 #else
  62 #define MV64360_TX_QUEUE_SIZE 4
  63 #endif
  64
  65 /* Default RX ring size is 4 descriptors */
  66 #ifdef  CONFIG_MV64360_ETH_RXQUEUE_SIZE
  67 #define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
  68 #else
  69 #define MV64360_RX_QUEUE_SIZE 4
  70 #endif
  71
  72 #ifdef CONFIG_RX_BUFFER_SIZE
  73 #define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
  74 #else
  75 #define MV64360_RX_BUFFER_SIZE 1600
  76 #endif
  77
  78 #ifdef CONFIG_TX_BUFFER_SIZE
  79 #define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
  80 #else
  81 #define MV64360_TX_BUFFER_SIZE 1600
  82 #endif
  83
  84
  85 /*
  86  *      Network device statistics. Akin to the 2.0 ether stats but
  87  *      with byte counters.
  88  */
  89
  90 struct net_device_stats
  91 {
  92         unsigned long   rx_packets;             /* total packets received       */
  93         unsigned long   tx_packets;             /* total packets transmitted    */
  94         unsigned long   rx_bytes;               /* total bytes received         */
  95         unsigned long   tx_bytes;               /* total bytes transmitted      */
  96         unsigned long   rx_errors;              /* bad packets received         */
  97         unsigned long   tx_errors;              /* packet transmit problems     */
  98         unsigned long   rx_dropped;             /* no space in linux buffers    */
  99         unsigned long   tx_dropped;             /* no space available in linux  */
 100         unsigned long   multicast;              /* multicast packets received   */
 101         unsigned long   collisions;
 102
 103         /* detailed rx_errors: */
 104         unsigned long   rx_length_errors;
 105         unsigned long   rx_over_errors;         /* receiver ring buff overflow  */
 106         unsigned long   rx_crc_errors;          /* recved pkt with crc error    */
 107         unsigned long   rx_frame_errors;        /* recv'd frame alignment error */
 108         unsigned long   rx_fifo_errors;         /* recv'r fifo overrun          */
 109         unsigned long   rx_missed_errors;       /* receiver missed packet       */
 110
 111         /* detailed tx_errors */
 112         unsigned long   tx_aborted_errors;
 113         unsigned long   tx_carrier_errors;
 114         unsigned long   tx_fifo_errors;
 115         unsigned long   tx_heartbeat_errors;
 116         unsigned long   tx_window_errors;
 117
 118         /* for cslip etc */
 119         unsigned long   rx_compressed;
 120         unsigned long   tx_compressed;
 121 };
 122
 123
 124 /* Private data structure used for ethernet device */
 125 struct mv64360_eth_priv {
 126     unsigned int port_num;
 127     struct net_device_stats *stats;
 128
 129 /* to buffer area aligned */
 130     char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];    /*pointers to alligned tx buffs in memory space */
 131     char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];    /*pointers to allinged rx buffs in memory space */
 132
 133     /* Size of Tx Ring per queue */
 134     unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
 135
 136
 137     /* Size of Rx Ring per queue */
 138     unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
 139
 140     /* Magic Number for Ethernet running */
 141     unsigned int eth_running;
 142
 143 };
 144
 145
 146 int mv64360_eth_init (struct eth_device *dev);
 147 int mv64360_eth_stop (struct eth_device *dev);
 148 int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
 149 int mv64360_eth_open (struct eth_device *dev);
 150
 151
 152 /*************************************************************************
 153 **************************************************************************
 154 **************************************************************************
 155 *  The second part is the low level driver of the gigE ethernet ports.   *
 156 **************************************************************************
 157 **************************************************************************
 158 *************************************************************************/
 159
 160
 161 /********************************************************************************
 162  * Header File for : MV-643xx network interface header
 163  *
 164  * DESCRIPTION:
 165  *       This header file contains macros typedefs and function declaration for
 166  *       the Marvell Gig Bit Ethernet Controller.
 167  *
 168  * DEPENDENCIES:
 169  *       None.
 170  *
 171  *******************************************************************************/
 172
 173
 174 #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
 175 #ifdef CONFIG_MV64360_SRAM_CACHEABLE
 176 /* In case SRAM is cacheable but not cache coherent */
 177 #define D_CACHE_FLUSH_LINE(addr, offset)       \
 178 {                   \
 179   __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
 180 }
 181 #else
 182 /* In case SRAM is cache coherent or non-cacheable */
 183 #define D_CACHE_FLUSH_LINE(addr, offset) ;
 184 #endif
 185 #else
 186 #ifdef CONFIG_NOT_COHERENT_CACHE
 187 /* In case of descriptors on DDR but not cache coherent */
 188 #define D_CACHE_FLUSH_LINE(addr, offset)       \
 189 {                   \
 190   __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
 191 }
 192 #else
 193 /* In case of descriptors on DDR and cache coherent */
 194 #define D_CACHE_FLUSH_LINE(addr, offset) ;
 195 #endif /* CONFIG_NOT_COHERENT_CACHE */
 196 #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
 197
 198
 199 #define CPU_PIPE_FLUSH             \
 200 {                 \
 201   __asm__ __volatile__ ("eieio");         \
 202 }
 203
 204
 205 /* defines  */
 206
 207 /* Default port configuration value */
 208 #define PORT_CONFIG_VALUE                       \
 209              ETH_UNICAST_NORMAL_MODE            |   \
 210              ETH_DEFAULT_RX_QUEUE_0             |   \
 211              ETH_DEFAULT_RX_ARP_QUEUE_0         |   \
 212              ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP    |   \
 213              ETH_RECEIVE_BC_IF_IP               |   \
 214              ETH_RECEIVE_BC_IF_ARP              |   \
 215              ETH_CAPTURE_TCP_FRAMES_DIS         |   \
 216              ETH_CAPTURE_UDP_FRAMES_DIS         |   \
 217              ETH_DEFAULT_RX_TCP_QUEUE_0         |   \
 218              ETH_DEFAULT_RX_UDP_QUEUE_0         |   \
 219              ETH_DEFAULT_RX_BPDU_QUEUE_0
 220
 221 /* Default port extend configuration value */
 222 #define PORT_CONFIG_EXTEND_VALUE                \
 223              ETH_SPAN_BPDU_PACKETS_AS_NORMAL    |   \
 224              ETH_PARTITION_DISABLE
 225
 226
 227 /* Default sdma control value */
 228 #ifdef CONFIG_NOT_COHERENT_CACHE
 229 #define PORT_SDMA_CONFIG_VALUE                          \
 230                          ETH_RX_BURST_SIZE_16_64BIT     |       \
 231                          GT_ETH_IPG_INT_RX(0)                   |       \
 232                          ETH_TX_BURST_SIZE_16_64BIT;
 233 #else
 234 #define PORT_SDMA_CONFIG_VALUE                  \
 235                          ETH_RX_BURST_SIZE_4_64BIT      |       \
 236                          GT_ETH_IPG_INT_RX(0)                   |       \
 237                          ETH_TX_BURST_SIZE_4_64BIT;
 238 #endif
 239
 240 #define GT_ETH_IPG_INT_RX(value)                \
 241             ((value & 0x3fff) << 8)
 242
 243 /* Default port serial control value */
 244 #define PORT_SERIAL_CONTROL_VALUE                           \
 245                         ETH_FORCE_LINK_PASS                     |       \
 246                         ETH_ENABLE_AUTO_NEG_FOR_DUPLX           |       \
 247                         ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL      |       \
 248                         ETH_ADV_SYMMETRIC_FLOW_CTRL             |       \
 249                         ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX       |       \
 250                         ETH_FORCE_BP_MODE_NO_JAM                |       \
 251                         BIT9                                    |       \
 252                         ETH_DO_NOT_FORCE_LINK_FAIL              |       \
 253                         ETH_RETRANSMIT_16_ETTEMPTS              |       \
 254                         ETH_ENABLE_AUTO_NEG_SPEED_GMII          |       \
 255                         ETH_DTE_ADV_0                           |       \
 256                         ETH_DISABLE_AUTO_NEG_BYPASS             |       \
 257                         ETH_AUTO_NEG_NO_CHANGE                  |       \
 258                         ETH_MAX_RX_PACKET_1552BYTE              |       \
 259                         ETH_CLR_EXT_LOOPBACK                    |       \
 260                         ETH_SET_FULL_DUPLEX_MODE                |       \
 261                         ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
 262
 263 #define RX_BUFFER_MAX_SIZE  0xFFFF
 264 #define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
 265
 266 #define RX_BUFFER_MIN_SIZE  0x8
 267 #define TX_BUFFER_MIN_SIZE  0x8
 268
 269 /* Tx WRR confoguration macros */
 270 #define PORT_MAX_TRAN_UNIT          0x24    /* MTU register (default) 9KByte */
 271 #define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
 272 #define PORT_TOKEN_RATE             1023    /* PTTBRC register (default)     */
 273
 274 /* MAC accepet/reject macros */
 275 #define ACCEPT_MAC_ADDR     0
 276 #define REJECT_MAC_ADDR     1
 277
 278 /* Size of a Tx/Rx descriptor used in chain list data structure */
 279 #define RX_DESC_ALIGNED_SIZE            0x20
 280 #define TX_DESC_ALIGNED_SIZE            0x20
 281
 282 /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
 283 #define TX_BUF_OFFSET_IN_DESC       0x18
 284 /* Buffer offset from buffer pointer */
 285 #define RX_BUF_OFFSET                           0x2
 286
 287 /* Gap define */
 288 #define ETH_BAR_GAP                                     0x8
 289 #define ETH_SIZE_REG_GAP                                0x8
 290 #define ETH_HIGH_ADDR_REMAP_REG_GAP                     0x4
 291 #define ETH_PORT_ACCESS_CTRL_GAP                        0x4
 292
 293 /* Gigabit Ethernet Unit Global Registers */
 294
 295 /* MIB Counters register definitions */
 296 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
 297 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
 298 #define ETH_MIB_BAD_OCTETS_RECEIVED        0x8
 299 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
 300 #define ETH_MIB_GOOD_FRAMES_RECEIVED       0x10
 301 #define ETH_MIB_BAD_FRAMES_RECEIVED        0x14
 302 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
 303 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
 304 #define ETH_MIB_FRAMES_64_OCTETS           0x20
 305 #define ETH_MIB_FRAMES_65_TO_127_OCTETS    0x24
 306 #define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
 307 #define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
 308 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
 309 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
 310 #define ETH_MIB_GOOD_OCTETS_SENT_LOW       0x38
 311 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH      0x3c
 312 #define ETH_MIB_GOOD_FRAMES_SENT           0x40
 313 #define ETH_MIB_EXCESSIVE_COLLISION        0x44
 314 #define ETH_MIB_MULTICAST_FRAMES_SENT      0x48
 315 #define ETH_MIB_BROADCAST_FRAMES_SENT      0x4c
 316 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
 317 #define ETH_MIB_FC_SENT                    0x54
 318 #define ETH_MIB_GOOD_FC_RECEIVED           0x58
 319 #define ETH_MIB_BAD_FC_RECEIVED            0x5c
 320 #define ETH_MIB_UNDERSIZE_RECEIVED         0x60
 321 #define ETH_MIB_FRAGMENTS_RECEIVED         0x64
 322 #define ETH_MIB_OVERSIZE_RECEIVED          0x68
 323 #define ETH_MIB_JABBER_RECEIVED            0x6c
 324 #define ETH_MIB_MAC_RECEIVE_ERROR          0x70
 325 #define ETH_MIB_BAD_CRC_EVENT              0x74
 326 #define ETH_MIB_COLLISION                  0x78
 327 #define ETH_MIB_LATE_COLLISION             0x7c
 328
 329 /* Port serial status reg (PSR) */
 330 #define ETH_INTERFACE_GMII_MII                          0
 331 #define ETH_INTERFACE_PCM                               BIT0
 332 #define ETH_LINK_IS_DOWN                                0
 333 #define ETH_LINK_IS_UP                                  BIT1
 334 #define ETH_PORT_AT_HALF_DUPLEX                         0
 335 #define ETH_PORT_AT_FULL_DUPLEX                         BIT2
 336 #define ETH_RX_FLOW_CTRL_DISABLED                       0
 337 #define ETH_RX_FLOW_CTRL_ENBALED                        BIT3
 338 #define ETH_GMII_SPEED_100_10                           0
 339 #define ETH_GMII_SPEED_1000                             BIT4
 340 #define ETH_MII_SPEED_10                                0
 341 #define ETH_MII_SPEED_100                               BIT5
 342 #define ETH_NO_TX                                       0
 343 #define ETH_TX_IN_PROGRESS                              BIT7
 344 #define ETH_BYPASS_NO_ACTIVE                            0
 345 #define ETH_BYPASS_ACTIVE                               BIT8
 346 #define ETH_PORT_NOT_AT_PARTITION_STATE                 0
 347 #define ETH_PORT_AT_PARTITION_STATE                     BIT9
 348 #define ETH_PORT_TX_FIFO_NOT_EMPTY                      0
 349 #define ETH_PORT_TX_FIFO_EMPTY                          BIT10
 350
 351
 352 /* These macros describes the Port configuration reg (Px_cR) bits */
 353 #define ETH_UNICAST_NORMAL_MODE                         0
 354 #define ETH_UNICAST_PROMISCUOUS_MODE                    BIT0
 355 #define ETH_DEFAULT_RX_QUEUE_0                          0
 356 #define ETH_DEFAULT_RX_QUEUE_1                          BIT1
 357 #define ETH_DEFAULT_RX_QUEUE_2                          BIT2
 358 #define ETH_DEFAULT_RX_QUEUE_3                          (BIT2 | BIT1)
 359 #define ETH_DEFAULT_RX_QUEUE_4                          BIT3
 360 #define ETH_DEFAULT_RX_QUEUE_5                          (BIT3 | BIT1)
 361 #define ETH_DEFAULT_RX_QUEUE_6                          (BIT3 | BIT2)
 362 #define ETH_DEFAULT_RX_QUEUE_7                          (BIT3 | BIT2 | BIT1)
 363 #define ETH_DEFAULT_RX_ARP_QUEUE_0                      0
 364 #define ETH_DEFAULT_RX_ARP_QUEUE_1                      BIT4
 365 #define ETH_DEFAULT_RX_ARP_QUEUE_2                      BIT5
 366 #define ETH_DEFAULT_RX_ARP_QUEUE_3                      (BIT5 | BIT4)
 367 #define ETH_DEFAULT_RX_ARP_QUEUE_4                      BIT6
 368 #define ETH_DEFAULT_RX_ARP_QUEUE_5                      (BIT6 | BIT4)
 369 #define ETH_DEFAULT_RX_ARP_QUEUE_6                      (BIT6 | BIT5)
 370 #define ETH_DEFAULT_RX_ARP_QUEUE_7                      (BIT6 | BIT5 | BIT4)
 371 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP                 0
 372 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP                  BIT7
 373 #define ETH_RECEIVE_BC_IF_IP                            0
 374 #define ETH_REJECT_BC_IF_IP                             BIT8
 375 #define ETH_RECEIVE_BC_IF_ARP                           0
 376 #define ETH_REJECT_BC_IF_ARP                            BIT9
 377 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY               BIT12
 378 #define ETH_CAPTURE_TCP_FRAMES_DIS                      0
 379 #define ETH_CAPTURE_TCP_FRAMES_EN                       BIT14
 380 #define ETH_CAPTURE_UDP_FRAMES_DIS                      0
 381 #define ETH_CAPTURE_UDP_FRAMES_EN                       BIT15
 382 #define ETH_DEFAULT_RX_TCP_QUEUE_0                      0
 383 #define ETH_DEFAULT_RX_TCP_QUEUE_1                      BIT16
 384 #define ETH_DEFAULT_RX_TCP_QUEUE_2                      BIT17
 385 #define ETH_DEFAULT_RX_TCP_QUEUE_3                      (BIT17 | BIT16)
 386 #define ETH_DEFAULT_RX_TCP_QUEUE_4                      BIT18
 387 #define ETH_DEFAULT_RX_TCP_QUEUE_5                      (BIT18 | BIT16)
 388 #define ETH_DEFAULT_RX_TCP_QUEUE_6                      (BIT18 | BIT17)
 389 #define ETH_DEFAULT_RX_TCP_QUEUE_7                      (BIT18 | BIT17 | BIT16)
 390 #define ETH_DEFAULT_RX_UDP_QUEUE_0                      0
 391 #define ETH_DEFAULT_RX_UDP_QUEUE_1                      BIT19
 392 #define ETH_DEFAULT_RX_UDP_QUEUE_2                      BIT20
 393 #define ETH_DEFAULT_RX_UDP_QUEUE_3                      (BIT20 | BIT19)
 394 #define ETH_DEFAULT_RX_UDP_QUEUE_4                      (BIT21
 395 #define ETH_DEFAULT_RX_UDP_QUEUE_5                      (BIT21 | BIT19)
 396 #define ETH_DEFAULT_RX_UDP_QUEUE_6                      (BIT21 | BIT20)
 397 #define ETH_DEFAULT_RX_UDP_QUEUE_7                      (BIT21 | BIT20 | BIT19)
 398 #define ETH_DEFAULT_RX_BPDU_QUEUE_0                      0
 399 #define ETH_DEFAULT_RX_BPDU_QUEUE_1                     BIT22
 400 #define ETH_DEFAULT_RX_BPDU_QUEUE_2                     BIT23
 401 #define ETH_DEFAULT_RX_BPDU_QUEUE_3                     (BIT23 | BIT22)
 402 #define ETH_DEFAULT_RX_BPDU_QUEUE_4                     BIT24
 403 #define ETH_DEFAULT_RX_BPDU_QUEUE_5                     (BIT24 | BIT22)
 404 #define ETH_DEFAULT_RX_BPDU_QUEUE_6                     (BIT24 | BIT23)
 405 #define ETH_DEFAULT_RX_BPDU_QUEUE_7                     (BIT24 | BIT23 | BIT22)
 406
 407
 408 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
 409 #define ETH_CLASSIFY_EN                                 BIT0
 410 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL                 0
 411 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7             BIT1
 412 #define ETH_PARTITION_DISABLE                           0
 413 #define ETH_PARTITION_ENABLE                            BIT2
 414
 415
 416 /* Tx/Rx queue command reg (RQCR/TQCR)*/
 417 #define ETH_QUEUE_0_ENABLE                              BIT0
 418 #define ETH_QUEUE_1_ENABLE                              BIT1
 419 #define ETH_QUEUE_2_ENABLE                              BIT2
 420 #define ETH_QUEUE_3_ENABLE                              BIT3
 421 #define ETH_QUEUE_4_ENABLE                              BIT4
 422 #define ETH_QUEUE_5_ENABLE                              BIT5
 423 #define ETH_QUEUE_6_ENABLE                              BIT6
 424 #define ETH_QUEUE_7_ENABLE                              BIT7
 425 #define ETH_QUEUE_0_DISABLE                             BIT8
 426 #define ETH_QUEUE_1_DISABLE                             BIT9
 427 #define ETH_QUEUE_2_DISABLE                             BIT10
 428 #define ETH_QUEUE_3_DISABLE                             BIT11
 429 #define ETH_QUEUE_4_DISABLE                             BIT12
 430 #define ETH_QUEUE_5_DISABLE                             BIT13
 431 #define ETH_QUEUE_6_DISABLE                             BIT14
 432 #define ETH_QUEUE_7_DISABLE                             BIT15
 433
 434
 435 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
 436 #define ETH_RIFB                                        BIT0
 437 #define ETH_RX_BURST_SIZE_1_64BIT                       0
 438 #define ETH_RX_BURST_SIZE_2_64BIT                       BIT1
 439 #define ETH_RX_BURST_SIZE_4_64BIT                       BIT2
 440 #define ETH_RX_BURST_SIZE_8_64BIT                       (BIT2 | BIT1)
 441 #define ETH_RX_BURST_SIZE_16_64BIT                      BIT3
 442 #define ETH_BLM_RX_NO_SWAP                              BIT4
 443 #define ETH_BLM_RX_BYTE_SWAP                            0
 444 #define ETH_BLM_TX_NO_SWAP                              BIT5
 445 #define ETH_BLM_TX_BYTE_SWAP                            0
 446 #define ETH_DESCRIPTORS_BYTE_SWAP                       BIT6
 447 #define ETH_DESCRIPTORS_NO_SWAP                         0
 448 #define ETH_TX_BURST_SIZE_1_64BIT                       0
 449 #define ETH_TX_BURST_SIZE_2_64BIT                       BIT22
 450 #define ETH_TX_BURST_SIZE_4_64BIT                       BIT23
 451 #define ETH_TX_BURST_SIZE_8_64BIT                       (BIT23 | BIT22)
 452 #define ETH_TX_BURST_SIZE_16_64BIT                      BIT24
 453
 454
 455 /* These macros describes the Port serial control reg (PSCR) bits */
 456 #define ETH_SERIAL_PORT_DISABLE                         0
 457 #define ETH_SERIAL_PORT_ENABLE                          BIT0
 458 #define ETH_FORCE_LINK_PASS                             BIT1
 459 #define ETH_DO_NOT_FORCE_LINK_PASS                      0
 460 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX                   0
 461 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX                  BIT2
 462 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL               0
 463 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL              BIT3
 464 #define ETH_ADV_NO_FLOW_CTRL                            0
 465 #define ETH_ADV_SYMMETRIC_FLOW_CTRL                     BIT4
 466 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX               0
 467 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS                  BIT5
 468 #define ETH_FORCE_BP_MODE_NO_JAM                        0
 469 #define ETH_FORCE_BP_MODE_JAM_TX                        BIT7
 470 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR              BIT8
 471 #define ETH_FORCE_LINK_FAIL                             0
 472 #define ETH_DO_NOT_FORCE_LINK_FAIL                      BIT10
 473 #define ETH_RETRANSMIT_16_ETTEMPTS                      0
 474 #define ETH_RETRANSMIT_FOREVER                          BIT11
 475 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII                 BIT13
 476 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII                  0
 477 #define ETH_DTE_ADV_0                                   0
 478 #define ETH_DTE_ADV_1                                   BIT14
 479 #define ETH_DISABLE_AUTO_NEG_BYPASS                     0
 480 #define ETH_ENABLE_AUTO_NEG_BYPASS                      BIT15
 481 #define ETH_AUTO_NEG_NO_CHANGE                          0
 482 #define ETH_RESTART_AUTO_NEG                            BIT16
 483 #define ETH_MAX_RX_PACKET_1518BYTE                      0
 484 #define ETH_MAX_RX_PACKET_1522BYTE                      BIT17
 485 #define ETH_MAX_RX_PACKET_1552BYTE                      BIT18
 486 #define ETH_MAX_RX_PACKET_9022BYTE                      (BIT18 | BIT17)
 487 #define ETH_MAX_RX_PACKET_9192BYTE                      BIT19
 488 #define ETH_MAX_RX_PACKET_9700BYTE                      (BIT19 | BIT17)
 489 #define ETH_SET_EXT_LOOPBACK                            BIT20
 490 #define ETH_CLR_EXT_LOOPBACK                            0
 491 #define ETH_SET_FULL_DUPLEX_MODE                        BIT21
 492 #define ETH_SET_HALF_DUPLEX_MODE                        0
 493 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX       BIT22
 494 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX      0
 495 #define ETH_SET_GMII_SPEED_TO_10_100                    0
 496 #define ETH_SET_GMII_SPEED_TO_1000                      BIT23
 497 #define ETH_SET_MII_SPEED_TO_10                         0
 498 #define ETH_SET_MII_SPEED_TO_100                        BIT24
 499
 500
 501 /* SMI reg */
 502 #define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
 503 #define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
 504 #define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
 505 #define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress             */
 506
 507 /* SDMA command status fields macros */
 508
 509 /* Tx & Rx descriptors status */
 510 #define ETH_ERROR_SUMMARY                   (BIT0)
 511
 512 /* Tx & Rx descriptors command */
 513 #define ETH_BUFFER_OWNED_BY_DMA             (BIT31)
 514
 515 /* Tx descriptors status */
 516 #define ETH_LC_ERROR                        (0    )
 517 #define ETH_UR_ERROR                        (BIT1 )
 518 #define ETH_RL_ERROR                        (BIT2 )
 519 #define ETH_LLC_SNAP_FORMAT                 (BIT9 )
 520
 521 /* Rx descriptors status */
 522 #define ETH_CRC_ERROR                       (0    )
 523 #define ETH_OVERRUN_ERROR                   (BIT1 )
 524 #define ETH_MAX_FRAME_LENGTH_ERROR          (BIT2 )
 525 #define ETH_RESOURCE_ERROR                  ((BIT2 | BIT1))
 526 #define ETH_VLAN_TAGGED                     (BIT19)
 527 #define ETH_BPDU_FRAME                      (BIT20)
 528 #define ETH_TCP_FRAME_OVER_IP_V_4           (0    )
 529 #define ETH_UDP_FRAME_OVER_IP_V_4           (BIT21)
 530 #define ETH_OTHER_FRAME_TYPE                (BIT22)
 531 #define ETH_LAYER_2_IS_ETH_V_2              (BIT23)
 532 #define ETH_FRAME_TYPE_IP_V_4               (BIT24)
 533 #define ETH_FRAME_HEADER_OK                 (BIT25)
 534 #define ETH_RX_LAST_DESC                    (BIT26)
 535 #define ETH_RX_FIRST_DESC                   (BIT27)
 536 #define ETH_UNKNOWN_DESTINATION_ADDR        (BIT28)
 537 #define ETH_RX_ENABLE_INTERRUPT             (BIT29)
 538 #define ETH_LAYER_4_CHECKSUM_OK             (BIT30)
 539
 540 /* Rx descriptors byte count */
 541 #define ETH_FRAME_FRAGMENTED                (BIT2)
 542
 543 /* Tx descriptors command */
 544 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
 545 #define ETH_FRAME_SET_TO_VLAN               (BIT15)
 546 #define ETH_TCP_FRAME                       (0    )
 547 #define ETH_UDP_FRAME                       (BIT16)
 548 #define ETH_GEN_TCP_UDP_CHECKSUM            (BIT17)
 549 #define ETH_GEN_IP_V_4_CHECKSUM             (BIT18)
 550 #define ETH_ZERO_PADDING                    (BIT19)
 551 #define ETH_TX_LAST_DESC                    (BIT20)
 552 #define ETH_TX_FIRST_DESC                   (BIT21)
 553 #define ETH_GEN_CRC                         (BIT22)
 554 #define ETH_TX_ENABLE_INTERRUPT             (BIT23)
 555 #define ETH_AUTO_MODE                       (BIT30)
 556
 557 /* Address decode parameters */
 558 /* Ethernet Base Address Register bits */
 559 #define EBAR_TARGET_DRAM                                        0x00000000
 560 #define EBAR_TARGET_DEVICE                                      0x00000001
 561 #define EBAR_TARGET_CBS                                         0x00000002
 562 #define EBAR_TARGET_PCI0                                        0x00000003
 563 #define EBAR_TARGET_PCI1                                        0x00000004
 564 #define EBAR_TARGET_CUNIT                                       0x00000005
 565 #define EBAR_TARGET_AUNIT                                       0x00000006
 566 #define EBAR_TARGET_GUNIT                                       0x00000007
 567
 568 /* Window attributes */
 569 #define EBAR_ATTR_DRAM_CS0                                      0x00000E00
 570 #define EBAR_ATTR_DRAM_CS1                                      0x00000D00
 571 #define EBAR_ATTR_DRAM_CS2                                      0x00000B00
 572 #define EBAR_ATTR_DRAM_CS3                                      0x00000700
 573
 574 /* DRAM Target interface */
 575 #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY       0x00000000
 576 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT       0x00001000
 577 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB       0x00002000
 578
 579 /* Device Bus Target interface */
 580 #define EBAR_ATTR_DEVICE_DEVCS0                         0x00001E00
 581 #define EBAR_ATTR_DEVICE_DEVCS1                         0x00001D00
 582 #define EBAR_ATTR_DEVICE_DEVCS2                         0x00001B00
 583 #define EBAR_ATTR_DEVICE_DEVCS3                         0x00001700
 584 #define EBAR_ATTR_DEVICE_BOOTCS3                        0x00000F00
 585
 586 /* PCI Target interface */
 587 #define EBAR_ATTR_PCI_BYTE_SWAP                         0x00000000
 588 #define EBAR_ATTR_PCI_NO_SWAP                           0x00000100
 589 #define EBAR_ATTR_PCI_BYTE_WORD_SWAP            0x00000200
 590 #define EBAR_ATTR_PCI_WORD_SWAP                         0x00000300
 591 #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT       0x00000000
 592 #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT           0x00000400
 593 #define EBAR_ATTR_PCI_IO_SPACE                          0x00000000
 594 #define EBAR_ATTR_PCI_MEMORY_SPACE                      0x00000800
 595 #define EBAR_ATTR_PCI_REQ64_FORCE                       0x00000000
 596 #define EBAR_ATTR_PCI_REQ64_SIZE                        0x00001000
 597
 598 /* CPU 60x bus or internal SRAM interface */
 599 #define EBAR_ATTR_CBS_SRAM_BLOCK0                       0x00000000
 600 #define EBAR_ATTR_CBS_SRAM_BLOCK1                       0x00000100
 601 #define EBAR_ATTR_CBS_SRAM                                      0x00000000
 602 #define EBAR_ATTR_CBS_CPU_BUS                           0x00000800
 603
 604 /* Window access control */
 605 #define EWIN_ACCESS_NOT_ALLOWED 0
 606 #define EWIN_ACCESS_READ_ONLY   BIT0
 607 #define EWIN_ACCESS_FULL        (BIT1 | BIT0)
 608 #define EWIN0_ACCESS_MASK               0x0003
 609 #define EWIN1_ACCESS_MASK               0x000C
 610 #define EWIN2_ACCESS_MASK               0x0030
 611 #define EWIN3_ACCESS_MASK               0x00C0
 612
 613 /* typedefs */
 614
 615 typedef enum _eth_port
 616 {
 617     ETH_0 = 0,
 618         ETH_1 = 1,
 619         ETH_2 = 2
 620 }ETH_PORT;
 621
 622 typedef enum _eth_func_ret_status
 623 {
 624     ETH_OK,                     /* Returned as expected.                    */
 625     ETH_ERROR,                  /* Fundamental error.                       */
 626     ETH_RETRY,                  /* Could not process request. Try later.    */
 627     ETH_END_OF_JOB,             /* Ring has nothing to process.             */
 628     ETH_QUEUE_FULL,             /* Ring resource error.                     */
 629     ETH_QUEUE_LAST_RESOURCE     /* Ring resources about to exhaust.         */
 630 }ETH_FUNC_RET_STATUS;
 631
 632 typedef enum _eth_queue
 633 {
 634         ETH_Q0 = 0,
 635         ETH_Q1 = 1,
 636         ETH_Q2 = 2,
 637         ETH_Q3 = 3,
 638         ETH_Q4 = 4,
 639         ETH_Q5 = 5,
 640         ETH_Q6 = 6,
 641     ETH_Q7 = 7
 642 } ETH_QUEUE;
 643
 644 typedef enum _addr_win
 645 {
 646         ETH_WIN0,
 647         ETH_WIN1,
 648         ETH_WIN2,
 649         ETH_WIN3,
 650         ETH_WIN4,
 651     ETH_WIN5
 652 } ETH_ADDR_WIN;
 653
 654 typedef enum _eth_target
 655 {
 656         ETH_TARGET_DRAM  ,
 657         ETH_TARGET_DEVICE,
 658         ETH_TARGET_CBS   ,
 659         ETH_TARGET_PCI0  ,
 660         ETH_TARGET_PCI1
 661 }ETH_TARGET;
 662
 663 typedef struct _eth_rx_desc
 664 {
 665         unsigned short  byte_cnt           ;    /* Descriptor buffer byte count     */
 666         unsigned short  buf_size           ;    /* Buffer size                      */
 667         unsigned int    cmd_sts    ;    /* Descriptor command status        */
 668         unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
 669         unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
 670     unsigned int    return_info ;    /* User resource return information */
 671 } ETH_RX_DESC;
 672
 673
 674 typedef struct _eth_tx_desc
 675 {
 676     unsigned short  byte_cnt       ;    /* Descriptor buffer byte count     */
 677     unsigned short  l4i_chk        ;    /* CPU provided TCP Checksum        */
 678     unsigned int    cmd_sts        ;    /* Descriptor command status        */
 679     unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
 680     unsigned int    buf_ptr        ;    /* Descriptor buffer pointer        */
 681     unsigned int    return_info ;    /* User resource return information */
 682 } ETH_TX_DESC;
 683
 684 /* Unified struct for Rx and Tx operations. The user is not required to */
 685 /* be familier with neither Tx nor Rx descriptors.                       */
 686 typedef struct _pkt_info
 687 {
 688         unsigned short  byte_cnt   ;    /* Descriptor buffer byte count     */
 689         unsigned short  l4i_chk    ;    /* Tx CPU provided TCP Checksum     */
 690         unsigned int    cmd_sts    ;    /* Descriptor command status        */
 691         unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
 692     unsigned int    return_info ;    /* User resource return information */
 693 } PKT_INFO;
 694
 695
 696 typedef struct _eth_win_param
 697 {
 698     ETH_ADDR_WIN win;   /* Window number. See ETH_ADDR_WIN enum */
 699     ETH_TARGET  target;    /* System targets. See ETH_TARGET enum */
 700     unsigned short attributes;  /* BAR attributes. See above macros. */
 701     unsigned int base_addr; /* Window base address in unsigned int form */
 702     unsigned int high_addr; /* Window high address in unsigned int form */
 703     unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
 704     bool enable; /* Enable/disable access to the window. */
 705     unsigned short access_ctrl; /* Access ctrl register. see above macros */
 706 } ETH_WIN_PARAM;
 707
 708
 709 /* Ethernet port specific infomation */
 710
 711 typedef struct _eth_port_ctrl
 712 {
 713     ETH_PORT  port_num; /* User Ethernet port number */
 714     int port_phy_addr;  /* User phy address of Ethrnet port */
 715     unsigned char port_mac_addr[6]; /* User defined port MAC address. */
 716     unsigned int  port_config; /* User port configuration value */
 717     unsigned int  port_config_extend; /* User port config extend value */
 718     unsigned int  port_sdma_config; /* User port SDMA config value */
 719     unsigned int  port_serial_control; /* User port serial control value */
 720     unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
 721     unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
 722
 723     /* User function to cast virtual address to CPU bus address */
 724     unsigned int  (*port_virt_to_phys)(unsigned int addr);
 725     /* User scratch pad for user specific data structures */
 726     void *port_private;
 727
 728     bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
 729     bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
 730
 731     /* Tx/Rx rings managment indexes fields. For driver use */
 732
 733     /* Next available Rx resource */
 734     volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
 735     /* Returning Rx resource */
 736     volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
 737
 738     /* Next available Tx resource */
 739     volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
 740     /* Returning Tx resource */
 741     volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
 742     /* An extra Tx index to support transmit of multiple buffers per packet */
 743     volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
 744
 745     /* Tx/Rx rings size and base variables fields. For driver use */
 746
 747     volatile ETH_RX_DESC        *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
 748     unsigned int                 rx_desc_area_size[MAX_RX_QUEUE_NUM];
 749     char                        *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
 750
 751     volatile ETH_TX_DESC        *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
 752     unsigned int                 tx_desc_area_size[MAX_TX_QUEUE_NUM];
 753     char                        *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
 754
 755 } ETH_PORT_INFO;
 756
 757
 758 /* ethernet.h API list */
 759
 760 /* Port operation control routines */
 761 static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
 762 static void eth_port_reset(ETH_PORT     eth_port_num);
 763 static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
 764
 765
 766 /* Port MAC address routines */
 767 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
 768                                   unsigned char *p_addr,
 769                                   ETH_QUEUE queue);
 770 #if 0   /* FIXME */
 771 static void eth_port_mc_addr    (ETH_PORT eth_port_num,
 772                                  unsigned char *p_addr,
 773                                  ETH_QUEUE queue,
 774                                  int option);
 775 #endif
 776
 777 /* PHY and MIB routines */
 778 static bool ethernet_phy_reset(ETH_PORT eth_port_num);
 779
 780 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
 781                                    unsigned int phy_reg,
 782                                    unsigned int value);
 783
 784 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
 785                                   unsigned int phy_reg,
 786                                   unsigned int* value);
 787
 788 static void eth_clear_mib_counters(ETH_PORT     eth_port_num);
 789
 790 /* Port data flow control routines */
 791 static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
 792                                              ETH_QUEUE tx_queue,
 793                                              PKT_INFO *p_pkt_info);
 794 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
 795                                               ETH_QUEUE tx_queue,
 796                                               PKT_INFO *p_pkt_info);
 797 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
 798                                              ETH_QUEUE rx_queue,
 799                                              PKT_INFO *p_pkt_info);
 800 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
 801                                               ETH_QUEUE rx_queue,
 802                                               PKT_INFO *p_pkt_info);
 803
 804
 805 static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
 806                                     ETH_QUEUE   tx_queue,
 807                                     int                         tx_desc_num,
 808                                     int                         tx_buff_size,
 809                                     unsigned int        tx_desc_base_addr,
 810                                     unsigned int        tx_buff_base_addr);
 811
 812 static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
 813                                     ETH_QUEUE   rx_queue,
 814                                     int                         rx_desc_num,
 815                                     int                         rx_buff_size,
 816                                     unsigned int        rx_desc_base_addr,
 817                                     unsigned int        rx_buff_base_addr);
 818
 819 #endif /* MV64360_ETH_ */