board/esd/cpci750/sdram_init.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * adaption for the Marvell DB64360 Board
  26  * Ingo Assmus (ingo.assmus@keymile.com)
  27  *
  28  * adaption for the cpci750 Board
  29  * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
  30  *************************************************************************/
  31
  32
  33 /* sdram_init.c - automatic memory sizing */
  34
  35 #include <common.h>
  36 #include <74xx_7xx.h>
  37 #include "../../Marvell/include/memory.h"
  38 #include "../../Marvell/include/pci.h"
  39 #include "../../Marvell/include/mv_gen_reg.h"
  40 #include <net.h>
  41
  42 #include "eth.h"
  43 #include "mpsc.h"
  44 #include "../../Marvell/common/i2c.h"
  45 #include "64360.h"
  46 #include "mv_regs.h"
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 #undef  DEBUG
  51 /* #define DEBUG */
  52 #ifdef CONFIG_PCI
  53 #define MAP_PCI
  54 #endif /* of CONFIG_PCI */
  55
  56 #ifdef DEBUG
  57 #define DP(x) x
  58 #else
  59 #define DP(x)
  60 #endif
  61
  62 int set_dfcdlInit(void);        /* setup delay line of Mv64360 */
  63
  64 /* ------------------------------------------------------------------------- */
  65
  66 int
  67 memory_map_bank(unsigned int bankNo,
  68                 unsigned int bankBase,
  69                 unsigned int bankLength)
  70 {
  71 #ifdef MAP_PCI
  72         PCI_HOST host;
  73 #endif
  74
  75
  76 #ifdef DEBUG
  77         if (bankLength > 0) {
  78                 printf("mapping bank %d at %08x - %08x\n",
  79                        bankNo, bankBase, bankBase + bankLength - 1);
  80         } else {
  81                 printf("unmapping bank %d\n", bankNo);
  82         }
  83 #endif
  84
  85         memoryMapBank(bankNo, bankBase, bankLength);
  86
  87 #ifdef MAP_PCI
  88         for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
  89                 const int features=
  90                         PREFETCH_ENABLE |
  91                         DELAYED_READ_ENABLE |
  92                         AGGRESSIVE_PREFETCH |
  93                         READ_LINE_AGGRESSIVE_PREFETCH |
  94                         READ_MULTI_AGGRESSIVE_PREFETCH |
  95                         MAX_BURST_4 |
  96                         PCI_NO_SWAP;
  97
  98                 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
  99
 100                 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
 101                                 bankLength);
 102
 103                 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
 104         }
 105 #endif
 106         return 0;
 107 }
 108
 109 #define GB         (1 << 30)
 110
 111 /* much of this code is based on (or is) the code in the pip405 port */
 112 /* thanks go to the authors of said port - Josh */
 113
 114 /* structure to store the relevant information about an sdram bank */
 115 typedef struct sdram_info {
 116         uchar drb_size;
 117         uchar registered, ecc;
 118         uchar tpar;
 119         uchar tras_clocks;
 120         uchar burst_len;
 121         uchar banks, slot;
 122 } sdram_info_t;
 123
 124 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
 125
 126 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
 127
 128 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
 129                                 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
 130                                } VOLTAGE_INTERFACE;
 131
 132 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
 133 typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
 134
 135
 136 /* SDRAM/DDR information struct */
 137 typedef struct _gtMemoryDimmInfo {
 138         MEMORY_TYPE memoryType;
 139         unsigned int numOfRowAddresses;
 140         unsigned int numOfColAddresses;
 141         unsigned int numOfModuleBanks;
 142         unsigned int dataWidth;
 143         VOLTAGE_INTERFACE voltageInterface;
 144         unsigned int errorCheckType;                    /* ECC , PARITY.. */
 145         unsigned int sdramWidth;                        /* 4,8,16 or 32 */ ;
 146         unsigned int errorCheckDataWidth;               /* 0 - no, 1 - Yes */
 147         unsigned int minClkDelay;
 148         unsigned int burstLengthSupported;
 149         unsigned int numOfBanksOnEachDevice;
 150         unsigned int suportedCasLatencies;
 151         unsigned int RefreshInterval;
 152         unsigned int maxCASlatencySupported_LoP;        /* LoP left of point (measured in ns) */
 153         unsigned int maxCASlatencySupported_RoP;        /* RoP right of point (measured in ns) */
 154         MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
 155         MAX_CL_SUPPORTED_SD maxClSupported_SD;
 156         unsigned int moduleBankDensity;
 157         /* module attributes (true for yes) */
 158         bool bufferedAddrAndControlInputs;
 159         bool registeredAddrAndControlInputs;
 160         bool onCardPLL;
 161         bool bufferedDQMBinputs;
 162         bool registeredDQMBinputs;
 163         bool differentialClockInput;
 164         bool redundantRowAddressing;
 165
 166         /* module general attributes */
 167         bool suportedAutoPreCharge;
 168         bool suportedPreChargeAll;
 169         bool suportedEarlyRasPreCharge;
 170         bool suportedWrite1ReadBurst;
 171         bool suported5PercentLowVCC;
 172         bool suported5PercentUpperVCC;
 173         /* module timing parameters */
 174         unsigned int minRasToCasDelay;
 175         unsigned int minRowActiveRowActiveDelay;
 176         unsigned int minRasPulseWidth;
 177         unsigned int minRowPrechargeTime;               /* measured in ns */
 178
 179         int addrAndCommandHoldTime;                     /* LoP left of point (measured in ns) */
 180         int addrAndCommandSetupTime;                    /* (measured in ns/100) */
 181         int dataInputSetupTime;                         /* LoP left of point (measured in ns) */
 182         int dataInputHoldTime;                          /* LoP left of point (measured in ns) */
 183 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
 184         unsigned int clockToDataOut_LoP;                /* LoP left of point (measured in ns) */
 185         unsigned int clockToDataOut_RoP;                /* RoP right of point (measured in ns) */
 186         unsigned int clockToDataOutMinus1_LoP;          /* LoP left of point (measured in ns) */
 187         unsigned int clockToDataOutMinus1_RoP;          /* RoP right of point (measured in ns) */
 188         unsigned int clockToDataOutMinus2_LoP;          /* LoP left of point (measured in ns) */
 189         unsigned int clockToDataOutMinus2_RoP;          /* RoP right of point (measured in ns) */
 190
 191         unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;       /* LoP left of point (measured in ns) */
 192         unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;       /* RoP right of point (measured in ns) */
 193
 194         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
 195         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
 196
 197         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
 198         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
 199
 200         /* Parameters calculated from
 201            the extracted DIMM information */
 202         unsigned int size;
 203         unsigned int deviceDensity;                     /* 16,64,128,256 or 512 Mbit */
 204         unsigned int numberOfDevices;
 205         uchar drb_size;                                 /* DRAM size in n*64Mbit */
 206         uchar slot;                                     /* Slot Number this module is inserted in */
 207         uchar spd_raw_data[128];                        /* Content of SPD-EEPROM copied 1:1 */
 208 #ifdef DEBUG
 209         uchar manufactura[8];                           /* Content of SPD-EEPROM Byte 64-71 */
 210         uchar modul_id[18];                             /* Content of SPD-EEPROM Byte 73-90 */
 211         uchar vendor_data[27];                          /* Content of SPD-EEPROM Byte 99-125 */
 212         unsigned long modul_serial_no;                  /* Content of SPD-EEPROM Byte 95-98 */
 213         unsigned int manufac_date;                      /* Content of SPD-EEPROM Byte 93-94 */
 214         unsigned int modul_revision;                    /* Content of SPD-EEPROM Byte 91-92 */
 215         uchar manufac_place;                            /* Content of SPD-EEPROM Byte 72 */
 216
 217 #endif
 218 } AUX_MEM_DIMM_INFO;
 219
 220
 221 /*
 222  * translate ns.ns/10 coding of SPD timing values
 223  * into 10 ps unit values
 224  */
 225 static inline unsigned short
 226 NS10to10PS(unsigned char spd_byte)
 227 {
 228         unsigned short ns, ns10;
 229
 230         /* isolate upper nibble */
 231         ns = (spd_byte >> 4) & 0x0F;
 232         /* isolate lower nibble */
 233         ns10 = (spd_byte & 0x0F);
 234
 235         return(ns*100 + ns10*10);
 236 }
 237
 238 /*
 239  * translate ns coding of SPD timing values
 240  * into 10 ps unit values
 241  */
 242 static inline unsigned short
 243 NSto10PS(unsigned char spd_byte)
 244 {
 245         return(spd_byte*100);
 246 }
 247
 248 /* This code reads the SPD chip on the sdram and populates
 249  * the array which is passed in with the relevant information */
 250 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 251 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 252 {
 253         unsigned long spd_checksum;
 254
 255         uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 256         int ret;
 257         unsigned int i, j, density = 1, devicesForErrCheck = 0;
 258
 259 #ifdef DEBUG
 260         unsigned int k;
 261 #endif
 262         unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
 263         int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
 264         uchar supp_cal, cal_val;
 265         ulong memclk, tmemclk;
 266         ulong tmp;
 267         uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
 268         uchar data[128];
 269
 270         memclk = gd->bus_clk;
 271         tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
 272
 273         memset (data, 0, sizeof (data));
 274
 275
 276         ret = 0;
 277
 278         DP (puts ("before i2c read\n"));
 279
 280         ret = i2c_read (addr, 0, 2, data, 128);
 281
 282         DP (puts ("after i2c read\n"));
 283
 284         if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
 285             || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
 286             || (data[70] != 'b') || (data[71] != 'h')) {
 287                 ret = -1;
 288         }
 289
 290         if ((ret != 0) && (slot == 0)) {
 291                 memset (data, 0, sizeof (data));
 292                 data[0] = 0x80;
 293                 data[1] = 0x08;
 294                 data[2] = 0x07;
 295                 data[3] = 0x0c;
 296                 data[4] = 0x09;
 297                 data[5] = 0x01;
 298                 data[6] = 0x48;
 299                 data[7] = 0x00;
 300                 data[8] = 0x04;
 301                 data[9] = 0x75;
 302                 data[10] = 0x80;
 303                 data[11] = 0x02;
 304                 data[12] = 0x80;
 305                 data[13] = 0x10;
 306                 data[14] = 0x08;
 307                 data[15] = 0x01;
 308                 data[16] = 0x0e;
 309                 data[17] = 0x04;
 310                 data[18] = 0x0c;
 311                 data[19] = 0x01;
 312                 data[20] = 0x02;
 313                 data[21] = 0x20;
 314                 data[22] = 0x00;
 315                 data[23] = 0xa0;
 316                 data[24] = 0x80;
 317                 data[25] = 0x00;
 318                 data[26] = 0x00;
 319                 data[27] = 0x50;
 320                 data[28] = 0x3c;
 321                 data[29] = 0x50;
 322                 data[30] = 0x32;
 323                 data[31] = 0x10;
 324                 data[32] = 0xb0;
 325                 data[33] = 0xb0;
 326                 data[34] = 0x60;
 327                 data[35] = 0x60;
 328                 data[64] = 'e';
 329                 data[65] = 's';
 330                 data[66] = 'd';
 331                 data[67] = '-';
 332                 data[68] = 'g';
 333                 data[69] = 'm';
 334                 data[70] = 'b';
 335                 data[71] = 'h';
 336                 ret = 0;
 337         }
 338
 339         /* zero all the values */
 340         memset (dimmInfo, 0, sizeof (*dimmInfo));
 341
 342         /* copy the SPD content 1:1 into the dimmInfo structure */
 343         for (i = 0; i <= 127; i++) {
 344                 dimmInfo->spd_raw_data[i] = data[i];
 345         }
 346
 347         if (ret) {
 348                 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
 349                 return 0;
 350         } else
 351                 dimmInfo->slot = slot;  /* start to fill up dimminfo for this "slot" */
 352
 353 #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 354
 355         for (i = 0; i <= 127; i++) {
 356                 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
 357                         data[i]);
 358         }
 359
 360 #endif
 361 #ifdef DEBUG
 362         /* find Manufacturer of Dimm Module */
 363         for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
 364                 dimmInfo->manufactura[i] = data[64 + i];
 365         }
 366         printf ("\nThis RAM-Module is produced by:              %s\n",
 367                 dimmInfo->manufactura);
 368
 369         /* find Manul-ID of Dimm Module */
 370         for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
 371                 dimmInfo->modul_id[i] = data[73 + i];
 372         }
 373         printf ("The Module-ID of this RAM-Module is:           %s\n",
 374                 dimmInfo->modul_id);
 375
 376         /* find Vendor-Data of Dimm Module */
 377         for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
 378                 dimmInfo->vendor_data[i] = data[99 + i];
 379         }
 380         printf ("Vendor Data of this RAM-Module is:             %s\n",
 381                 dimmInfo->vendor_data);
 382
 383         /* find modul_serial_no of Dimm Module */
 384         dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
 385         printf ("Serial No. of this RAM-Module is:              %ld (%lx)\n",
 386                 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 387
 388         /* find Manufac-Data of Dimm Module */
 389         dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
 390         printf ("Manufactoring Date of this RAM-Module is:      %d.%d\n", data[93], data[94]);  /*dimmInfo->manufac_date */
 391
 392         /* find modul_revision of Dimm Module */
 393         dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
 394         printf ("Module Revision of this RAM-Module is:                 %d.%d\n", data[91], data[92]);  /* dimmInfo->modul_revision */
 395
 396         /* find manufac_place of Dimm Module */
 397         dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
 398         printf ("manufac_place of this RAM-Module is:           %d\n",
 399                 dimmInfo->manufac_place);
 400
 401 #endif
 402 /*------------------------------------------------------------------------------------------------------------------------------*/
 403 /* calculate SPD checksum */
 404 /*------------------------------------------------------------------------------------------------------------------------------*/
 405         spd_checksum = 0;
 406 #if 0                           /* test-only */
 407         for (i = 0; i <= 62; i++) {
 408                 spd_checksum += data[i];
 409         }
 410
 411         if ((spd_checksum & 0xff) != data[63]) {
 412                 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
 413                 hang ();
 414         }
 415
 416         else
 417                 printf ("SPD Checksum ok!\n");
 418 #endif /* test-only */
 419
 420 /*------------------------------------------------------------------------------------------------------------------------------*/
 421         for (i = 2; i <= 35; i++) {
 422                 switch (i) {
 423                 case 2: /* Memory type (DDR / SDRAM) */
 424                         dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
 425 #ifdef DEBUG
 426                         if (dimmInfo->memoryType == 0)
 427                                 DP (printf
 428                                     ("Dram_type in slot %d is:                  SDRAM\n",
 429                                      dimmInfo->slot));
 430                         if (dimmInfo->memoryType == 1)
 431                                 DP (printf
 432                                     ("Dram_type in slot %d is:                  DDRAM\n",
 433                                      dimmInfo->slot));
 434 #endif
 435                         break;
 436 /*------------------------------------------------------------------------------------------------------------------------------*/
 437
 438                 case 3: /* Number Of Row Addresses */
 439                         dimmInfo->numOfRowAddresses = data[i];
 440                         DP (printf
 441                             ("Module Number of row addresses:           %d\n",
 442                              dimmInfo->numOfRowAddresses));
 443                         break;
 444 /*------------------------------------------------------------------------------------------------------------------------------*/
 445
 446                 case 4: /* Number Of Column Addresses */
 447                         dimmInfo->numOfColAddresses = data[i];
 448                         DP (printf
 449                             ("Module Number of col addresses:           %d\n",
 450                              dimmInfo->numOfColAddresses));
 451                         break;
 452 /*------------------------------------------------------------------------------------------------------------------------------*/
 453
 454                 case 5: /* Number Of Module Banks */
 455                         dimmInfo->numOfModuleBanks = data[i];
 456                         DP (printf
 457                             ("Number of Banks on Mod. :                                 %d\n",
 458                              dimmInfo->numOfModuleBanks));
 459                         break;
 460 /*------------------------------------------------------------------------------------------------------------------------------*/
 461
 462                 case 6: /* Data Width */
 463                         dimmInfo->dataWidth = data[i];
 464                         DP (printf
 465                             ("Module Data Width:                                %d\n",
 466                              dimmInfo->dataWidth));
 467                         break;
 468 /*------------------------------------------------------------------------------------------------------------------------------*/
 469
 470                 case 8: /* Voltage Interface */
 471                         switch (data[i]) {
 472                         case 0x0:
 473                                 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
 474                                 DP (printf
 475                                     ("Module is                                         TTL_5V_TOLERANT\n"));
 476                                 break;
 477                         case 0x1:
 478                                 dimmInfo->voltageInterface = LVTTL;
 479                                 DP (printf
 480                                     ("Module is                                         LVTTL\n"));
 481                                 break;
 482                         case 0x2:
 483                                 dimmInfo->voltageInterface = HSTL_1_5V;
 484                                 DP (printf
 485                                     ("Module is                                         TTL_5V_TOLERANT\n"));
 486                                 break;
 487                         case 0x3:
 488                                 dimmInfo->voltageInterface = SSTL_3_3V;
 489                                 DP (printf
 490                                     ("Module is                                         HSTL_1_5V\n"));
 491                                 break;
 492                         case 0x4:
 493                                 dimmInfo->voltageInterface = SSTL_2_5V;
 494                                 DP (printf
 495                                     ("Module is                                         SSTL_2_5V\n"));
 496                                 break;
 497                         default:
 498                                 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
 499                                 DP (printf
 500                                     ("Module is                                         VOLTAGE_UNKNOWN\n"));
 501                                 break;
 502                         }
 503                         break;
 504 /*------------------------------------------------------------------------------------------------------------------------------*/
 505
 506                 case 9: /* Minimum Cycle Time At Max CasLatancy */
 507                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 508                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 509                         maskLeftOfPoint =
 510                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 511                         maskRightOfPoint =
 512                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 513                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 514                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 515                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
 516                                 leftOfPoint;
 517                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
 518                                 rightOfPoint;
 519                         DP (printf
 520                             ("Minimum Cycle Time At Max CasLatancy:             %d.%d [ns]\n",
 521                              leftOfPoint, rightOfPoint));
 522                         break;
 523 /*------------------------------------------------------------------------------------------------------------------------------*/
 524
 525                 case 10:        /* Clock To Data Out */
 526                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 527                         time_tmp =
 528                                 (((data[i] & 0xf0) >> 4) * 10) +
 529                                 ((data[i] & 0x0f));
 530                         leftOfPoint = time_tmp / div;
 531                         rightOfPoint = time_tmp % div;
 532                         dimmInfo->clockToDataOut_LoP = leftOfPoint;
 533                         dimmInfo->clockToDataOut_RoP = rightOfPoint;
 534                         DP (printf
 535                             ("Clock To Data Out:                                %d.%2d [ns]\n",
 536                              leftOfPoint, rightOfPoint));
 537                         /*dimmInfo->clockToDataOut */
 538                         break;
 539 /*------------------------------------------------------------------------------------------------------------------------------*/
 540
 541 #ifdef CONFIG_MV64360_ECC
 542                 case 11:        /* Error Check Type */
 543                         dimmInfo->errorCheckType = data[i];
 544                         DP (printf
 545                             ("Error Check Type (0=NONE):                        %d\n",
 546                              dimmInfo->errorCheckType));
 547                         break;
 548 #endif /* of ifdef CONFIG_MV64360_ECC */
 549 /*------------------------------------------------------------------------------------------------------------------------------*/
 550
 551                 case 12:        /* Refresh Interval */
 552                         dimmInfo->RefreshInterval = data[i];
 553                         DP (printf
 554                             ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
 555                              dimmInfo->RefreshInterval));
 556                         break;
 557 /*------------------------------------------------------------------------------------------------------------------------------*/
 558
 559                 case 13:        /* Sdram Width */
 560                         dimmInfo->sdramWidth = data[i];
 561                         DP (printf
 562                             ("Sdram Width:                                      %d\n",
 563                              dimmInfo->sdramWidth));
 564                         break;
 565 /*------------------------------------------------------------------------------------------------------------------------------*/
 566
 567                 case 14:        /* Error Check Data Width */
 568                         dimmInfo->errorCheckDataWidth = data[i];
 569                         DP (printf
 570                             ("Error Check Data Width:                   %d\n",
 571                              dimmInfo->errorCheckDataWidth));
 572                         break;
 573 /*------------------------------------------------------------------------------------------------------------------------------*/
 574
 575                 case 15:        /* Minimum Clock Delay */
 576                         dimmInfo->minClkDelay = data[i];
 577                         DP (printf
 578                             ("Minimum Clock Delay:                              %d\n",
 579                              dimmInfo->minClkDelay));
 580                         break;
 581 /*------------------------------------------------------------------------------------------------------------------------------*/
 582
 583                 case 16:        /* Burst Length Supported */
 584                            /******-******-******-*******
 585                            * bit3 | bit2 | bit1 | bit0 *
 586                            *******-******-******-*******
 587             burst length = *  8   |  4   |   2  |   1  *
 588                            *****************************
 589
 590             If for example bit0 and bit2 are set, the burst
 591             length supported are 1 and 4. */
 592
 593                         dimmInfo->burstLengthSupported = data[i];
 594 #ifdef DEBUG
 595                         DP (printf
 596                             ("Burst Length Supported:                   "));
 597                         if (dimmInfo->burstLengthSupported & 0x01)
 598                                 DP (printf ("1, "));
 599                         if (dimmInfo->burstLengthSupported & 0x02)
 600                                 DP (printf ("2, "));
 601                         if (dimmInfo->burstLengthSupported & 0x04)
 602                                 DP (printf ("4, "));
 603                         if (dimmInfo->burstLengthSupported & 0x08)
 604                                 DP (printf ("8, "));
 605                         DP (printf (" Bit \n"));
 606 #endif
 607                         break;
 608 /*------------------------------------------------------------------------------------------------------------------------------*/
 609
 610                 case 17:        /* Number Of Banks On Each Device */
 611                         dimmInfo->numOfBanksOnEachDevice = data[i];
 612                         DP (printf
 613                             ("Number Of Banks On Each Chip:                     %d\n",
 614                              dimmInfo->numOfBanksOnEachDevice));
 615                         break;
 616 /*------------------------------------------------------------------------------------------------------------------------------*/
 617
 618                 case 18:        /* Suported Cas Latencies */
 619
 620                         /*     DDR:
 621                          *******-******-******-******-******-******-******-*******
 622                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 623                          *******-******-******-******-******-******-******-*******
 624                          CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 625                          *********************************************************
 626                          SDRAM:
 627                          *******-******-******-******-******-******-******-*******
 628                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 629                          *******-******-******-******-******-******-******-*******
 630                          CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
 631                          ********************************************************/
 632                         dimmInfo->suportedCasLatencies = data[i];
 633 #ifdef DEBUG
 634                         DP (printf
 635                             ("Suported Cas Latencies: (CL)                      "));
 636                         if (dimmInfo->memoryType == 0) {        /* SDRAM */
 637                                 for (k = 0; k <= 7; k++) {
 638                                         if (dimmInfo->
 639                                             suportedCasLatencies & (1 << k))
 640                                                 DP (printf
 641                                                     ("%d,                       ",
 642                                                      k + 1));
 643                                 }
 644
 645                         } else {        /* DDR-RAM */
 646
 647                                 if (dimmInfo->suportedCasLatencies & 1)
 648                                         DP (printf ("1, "));
 649                                 if (dimmInfo->suportedCasLatencies & 2)
 650                                         DP (printf ("1.5, "));
 651                                 if (dimmInfo->suportedCasLatencies & 4)
 652                                         DP (printf ("2, "));
 653                                 if (dimmInfo->suportedCasLatencies & 8)
 654                                         DP (printf ("2.5, "));
 655                                 if (dimmInfo->suportedCasLatencies & 16)
 656                                         DP (printf ("3, "));
 657                                 if (dimmInfo->suportedCasLatencies & 32)
 658                                         DP (printf ("3.5, "));
 659
 660                         }
 661                         DP (printf ("\n"));
 662 #endif
 663                         /* Calculating MAX CAS latency */
 664                         for (j = 7; j > 0; j--) {
 665                                 if (((dimmInfo->
 666                                       suportedCasLatencies >> j) & 0x1) ==
 667                                     1) {
 668                                         switch (dimmInfo->memoryType) {
 669                                         case DDR:
 670                                                 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
 671                                                 switch (j) {
 672                                                 case 7:
 673                                                         DP (printf
 674                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n"));
 675                                                         dimmInfo->
 676                                                                 maxClSupported_DDR
 677                                                                 =
 678                                                                 DDR_CL_FAULT;
 679                                                         hang ();
 680                                                         break;
 681                                                 case 6:
 682                                                         DP (printf
 683                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n"));
 684                                                         dimmInfo->
 685                                                                 maxClSupported_DDR
 686                                                                 =
 687                                                                 DDR_CL_FAULT;
 688                                                         hang ();
 689                                                         break;
 690                                                 case 5:
 691                                                         DP (printf
 692                                                             ("Max. Cas Latencies (DDR):                         3.5 clk's\n"));
 693                                                         dimmInfo->
 694                                                                 maxClSupported_DDR
 695                                                                 = DDR_CL_3_5;
 696                                                         break;
 697                                                 case 4:
 698                                                         DP (printf
 699                                                             ("Max. Cas Latencies (DDR):                         3 clk's \n"));
 700                                                         dimmInfo->
 701                                                                 maxClSupported_DDR
 702                                                                 = DDR_CL_3;
 703                                                         break;
 704                                                 case 3:
 705                                                         DP (printf
 706                                                             ("Max. Cas Latencies (DDR):                         2.5 clk's \n"));
 707                                                         dimmInfo->
 708                                                                 maxClSupported_DDR
 709                                                                 = DDR_CL_2_5;
 710                                                         break;
 711                                                 case 2:
 712                                                         DP (printf
 713                                                             ("Max. Cas Latencies (DDR):                         2 clk's \n"));
 714                                                         dimmInfo->
 715                                                                 maxClSupported_DDR
 716                                                                 = DDR_CL_2;
 717                                                         break;
 718                                                 case 1:
 719                                                         DP (printf
 720                                                             ("Max. Cas Latencies (DDR):                         1.5 clk's \n"));
 721                                                         dimmInfo->
 722                                                                 maxClSupported_DDR
 723                                                                 = DDR_CL_1_5;
 724                                                         break;
 725                                                 }
 726                                                 dimmInfo->
 727                                                         maxCASlatencySupported_LoP
 728                                                         =
 729                                                         1 +
 730                                                         (int) (5 * j / 10);
 731                                                 if (((5 * j) % 10) != 0)
 732                                                         dimmInfo->
 733                                                                 maxCASlatencySupported_RoP
 734                                                                 = 5;
 735                                                 else
 736                                                         dimmInfo->
 737                                                                 maxCASlatencySupported_RoP
 738                                                                 = 0;
 739                                                 DP (printf
 740                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation):        %d.%d \n",
 741                                                      dimmInfo->
 742                                                      maxCASlatencySupported_LoP,
 743                                                      dimmInfo->
 744                                                      maxCASlatencySupported_RoP));
 745                                                 break;
 746                                         case SDRAM:
 747                                                 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
 748                                                 dimmInfo->maxClSupported_SD = j;        /*  Cas Latency DDR-RAM Coded                   */
 749                                                 DP (printf
 750                                                     ("Max. Cas Latencies (SD): %d\n",
 751                                                      dimmInfo->
 752                                                      maxClSupported_SD));
 753                                                 dimmInfo->
 754                                                         maxCASlatencySupported_LoP
 755                                                         = j;
 756                                                 dimmInfo->
 757                                                         maxCASlatencySupported_RoP
 758                                                         = 0;
 759                                                 DP (printf
 760                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
 761                                                      dimmInfo->
 762                                                      maxCASlatencySupported_LoP,
 763                                                      dimmInfo->
 764                                                      maxCASlatencySupported_RoP));
 765                                                 break;
 766                                         }
 767                                         break;
 768                                 }
 769                         }
 770                         break;
 771 /*------------------------------------------------------------------------------------------------------------------------------*/
 772
 773                 case 21:        /* Buffered Address And Control Inputs */
 774                         DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
 775                         dimmInfo->bufferedAddrAndControlInputs =
 776                                 data[i] & BIT0;
 777                         dimmInfo->registeredAddrAndControlInputs =
 778                                 (data[i] & BIT1) >> 1;
 779                         dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
 780                         dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
 781                         dimmInfo->registeredDQMBinputs =
 782                                 (data[i] & BIT4) >> 4;
 783                         dimmInfo->differentialClockInput =
 784                                 (data[i] & BIT5) >> 5;
 785                         dimmInfo->redundantRowAddressing =
 786                                 (data[i] & BIT6) >> 6;
 787 #ifdef DEBUG
 788                         if (dimmInfo->bufferedAddrAndControlInputs == 1)
 789                                 DP (printf
 790                                     (" - Buffered Address/Control Input:                Yes \n"));
 791                         else
 792                                 DP (printf
 793                                     (" - Buffered Address/Control Input:                No \n"));
 794
 795                         if (dimmInfo->registeredAddrAndControlInputs == 1)
 796                                 DP (printf
 797                                     (" - Registered Address/Control Input:              Yes \n"));
 798                         else
 799                                 DP (printf
 800                                     (" - Registered Address/Control Input:              No \n"));
 801
 802                         if (dimmInfo->onCardPLL == 1)
 803                                 DP (printf
 804                                     (" - On-Card PLL (clock):                           Yes \n"));
 805                         else
 806                                 DP (printf
 807                                     (" - On-Card PLL (clock):                           No \n"));
 808
 809                         if (dimmInfo->bufferedDQMBinputs == 1)
 810                                 DP (printf
 811                                     (" - Bufferd DQMB Inputs:                           Yes \n"));
 812                         else
 813                                 DP (printf
 814                                     (" - Bufferd DQMB Inputs:                           No \n"));
 815
 816                         if (dimmInfo->registeredDQMBinputs == 1)
 817                                 DP (printf
 818                                     (" - Registered DQMB Inputs:                        Yes \n"));
 819                         else
 820                                 DP (printf
 821                                     (" - Registered DQMB Inputs:                        No \n"));
 822
 823                         if (dimmInfo->differentialClockInput == 1)
 824                                 DP (printf
 825                                     (" - Differential Clock Input:                      Yes \n"));
 826                         else
 827                                 DP (printf
 828                                     (" - Differential Clock Input:                      No \n"));
 829
 830                         if (dimmInfo->redundantRowAddressing == 1)
 831                                 DP (printf
 832                                     (" - redundant Row Addressing:                      Yes \n"));
 833                         else
 834                                 DP (printf
 835                                     (" - redundant Row Addressing:                      No \n"));
 836
 837 #endif
 838                         break;
 839 /*------------------------------------------------------------------------------------------------------------------------------*/
 840
 841                 case 22:        /* Suported AutoPreCharge */
 842                         DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
 843                         dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
 844                         dimmInfo->suportedAutoPreCharge =
 845                                 (data[i] & BIT1) >> 1;
 846                         dimmInfo->suportedPreChargeAll =
 847                                 (data[i] & BIT2) >> 2;
 848                         dimmInfo->suportedWrite1ReadBurst =
 849                                 (data[i] & BIT3) >> 3;
 850                         dimmInfo->suported5PercentLowVCC =
 851                                 (data[i] & BIT4) >> 4;
 852                         dimmInfo->suported5PercentUpperVCC =
 853                                 (data[i] & BIT5) >> 5;
 854 #ifdef DEBUG
 855                         if (dimmInfo->suportedEarlyRasPreCharge == 1)
 856                                 DP (printf
 857                                     (" - Early Ras Precharge:                   Yes \n"));
 858                         else
 859                                 DP (printf
 860                                     (" -  Early Ras Precharge:                  No \n"));
 861
 862                         if (dimmInfo->suportedAutoPreCharge == 1)
 863                                 DP (printf
 864                                     (" - AutoPreCharge:                         Yes \n"));
 865                         else
 866                                 DP (printf
 867                                     (" -  AutoPreCharge:                                No \n"));
 868
 869                         if (dimmInfo->suportedPreChargeAll == 1)
 870                                 DP (printf
 871                                     (" - Precharge All:                         Yes \n"));
 872                         else
 873                                 DP (printf
 874                                     (" -  Precharge All:                                No \n"));
 875
 876                         if (dimmInfo->suportedWrite1ReadBurst == 1)
 877                                 DP (printf
 878                                     (" - Write 1/ReadBurst:                             Yes \n"));
 879                         else
 880                                 DP (printf
 881                                     (" -  Write 1/ReadBurst:                            No \n"));
 882
 883                         if (dimmInfo->suported5PercentLowVCC == 1)
 884                                 DP (printf
 885                                     (" - lower VCC tolerance:                   5 Percent \n"));
 886                         else
 887                                 DP (printf
 888                                     ("  - lower VCC tolerance:                  10 Percent \n"));
 889
 890                         if (dimmInfo->suported5PercentUpperVCC == 1)
 891                                 DP (printf
 892                                     (" - upper VCC tolerance:                   5 Percent \n"));
 893                         else
 894                                 DP (printf
 895                                     (" -  upper VCC tolerance:                  10 Percent \n"));
 896
 897 #endif
 898                         break;
 899 /*------------------------------------------------------------------------------------------------------------------------------*/
 900
 901                 case 23:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
 902                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 903                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 904                         maskLeftOfPoint =
 905                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 906                         maskRightOfPoint =
 907                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 908                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 909                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 910                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
 911                                 leftOfPoint;
 912                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
 913                                 rightOfPoint;
 914                         DP (printf
 915                             ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 916                              leftOfPoint, rightOfPoint));
 917                         /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 918                         break;
 919 /*------------------------------------------------------------------------------------------------------------------------------*/
 920
 921                 case 24:        /* Clock To Data Out 2nd highest Cas Latency Value */
 922                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 923                         time_tmp =
 924                                 (((data[i] & 0xf0) >> 4) * 10) +
 925                                 ((data[i] & 0x0f));
 926                         leftOfPoint = time_tmp / div;
 927                         rightOfPoint = time_tmp % div;
 928                         dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
 929                         dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
 930                         DP (printf
 931                             ("Clock To Data Out (2nd CL value):                 %d.%2d [ns]\n",
 932                              leftOfPoint, rightOfPoint));
 933                         break;
 934 /*------------------------------------------------------------------------------------------------------------------------------*/
 935
 936                 case 25:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
 937                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 938                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 939                         maskLeftOfPoint =
 940                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 941                         maskRightOfPoint =
 942                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 943                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 944                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 945                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
 946                                 leftOfPoint;
 947                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
 948                                 rightOfPoint;
 949                         DP (printf
 950                             ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 951                              leftOfPoint, rightOfPoint));
 952                         /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 953                         break;
 954 /*------------------------------------------------------------------------------------------------------------------------------*/
 955
 956                 case 26:        /* Clock To Data Out 3rd highest Cas Latency Value */
 957                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 958                         time_tmp =
 959                                 (((data[i] & 0xf0) >> 4) * 10) +
 960                                 ((data[i] & 0x0f));
 961                         leftOfPoint = time_tmp / div;
 962                         rightOfPoint = time_tmp % div;
 963                         dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
 964                         dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
 965                         DP (printf
 966                             ("Clock To Data Out (3rd CL value):                 %d.%2d [ns]\n",
 967                              leftOfPoint, rightOfPoint));
 968                         break;
 969 /*------------------------------------------------------------------------------------------------------------------------------*/
 970
 971                 case 27:        /* Minimum Row Precharge Time */
 972                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 973                         maskLeftOfPoint =
 974                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 975                         maskRightOfPoint =
 976                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 977                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 978                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 979
 980                         dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);   /* measured in n times 10ps Intervals */
 981                         trp_clocks =
 982                                 (dimmInfo->minRowPrechargeTime +
 983                                  (tmemclk - 1)) / tmemclk;
 984                         DP (printf
 985                             ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
 986                              tmemclk, tmemclk / 100, tmemclk % 100));
 987                         DP (printf
 988                             ("Minimum Row Precharge Time [ns]:          %d.%2d = in Clk cycles %d\n",
 989                              leftOfPoint, rightOfPoint, trp_clocks));
 990                         break;
 991 /*------------------------------------------------------------------------------------------------------------------------------*/
 992
 993                 case 28:        /* Minimum Row Active to Row Active Time */
 994                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 995                         maskLeftOfPoint =
 996                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 997                         maskRightOfPoint =
 998                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 999                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1000                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1001
1002                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
1003                         trrd_clocks =
1004                                 (dimmInfo->minRowActiveRowActiveDelay +
1005                                  (tmemclk - 1)) / tmemclk;
1006                         DP (printf
1007                             ("Minimum Row Active -To- Row Active Delay [ns]:    %d.%2d = in Clk cycles %d\n",
1008                              leftOfPoint, rightOfPoint, trp_clocks));
1009                         break;
1010 /*------------------------------------------------------------------------------------------------------------------------------*/
1011
1012                 case 29:        /* Minimum Ras-To-Cas Delay */
1013                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
1014                         maskLeftOfPoint =
1015                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1016                         maskRightOfPoint =
1017                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1018                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1019                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1020
1021                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
1022                         trcd_clocks =
1023                                 (dimmInfo->minRowActiveRowActiveDelay +
1024                                  (tmemclk - 1)) / tmemclk;
1025                         DP (printf
1026                             ("Minimum Ras-To-Cas Delay [ns]:                    %d.%2d = in Clk cycles %d\n",
1027                              leftOfPoint, rightOfPoint, trp_clocks));
1028                         break;
1029 /*------------------------------------------------------------------------------------------------------------------------------*/
1030
1031                 case 30:        /* Minimum Ras Pulse Width */
1032                         dimmInfo->minRasPulseWidth = data[i];
1033                         tras_clocks =
1034                                 (NSto10PS (data[i]) +
1035                                  (tmemclk - 1)) / tmemclk;
1036                         DP (printf
1037                             ("Minimum Ras Pulse Width [ns]:                     %d = in Clk cycles %d\n",
1038                              dimmInfo->minRasPulseWidth, tras_clocks));
1039
1040                         break;
1041 /*------------------------------------------------------------------------------------------------------------------------------*/
1042
1043                 case 31:        /* Module Bank Density */
1044                         dimmInfo->moduleBankDensity = data[i];
1045                         DP (printf
1046                             ("Module Bank Density:                              %d\n",
1047                              dimmInfo->moduleBankDensity));
1048 #ifdef DEBUG
1049                         DP (printf
1050                             ("*** Offered Densities (more than 1 = Multisize-Module): "));
1051                         {
1052                                 if (dimmInfo->moduleBankDensity & 1)
1053                                         DP (printf ("4MB, "));
1054                                 if (dimmInfo->moduleBankDensity & 2)
1055                                         DP (printf ("8MB, "));
1056                                 if (dimmInfo->moduleBankDensity & 4)
1057                                         DP (printf ("16MB, "));
1058                                 if (dimmInfo->moduleBankDensity & 8)
1059                                         DP (printf ("32MB, "));
1060                                 if (dimmInfo->moduleBankDensity & 16)
1061                                         DP (printf ("64MB, "));
1062                                 if (dimmInfo->moduleBankDensity & 32)
1063                                         DP (printf ("128MB, "));
1064                                 if ((dimmInfo->moduleBankDensity & 64)
1065                                     || (dimmInfo->moduleBankDensity & 128)) {
1066                                         DP (printf ("ERROR, "));
1067                                         hang ();
1068                                 }
1069                         }
1070                         DP (printf ("\n"));
1071 #endif
1072                         break;
1073 /*------------------------------------------------------------------------------------------------------------------------------*/
1074
1075                 case 32:        /* Address And Command Setup Time (measured in ns/1000) */
1076                         sign = 1;
1077                         switch (dimmInfo->memoryType) {
1078                         case DDR:
1079                                 time_tmp =
1080                                         (((data[i] & 0xf0) >> 4) * 10) +
1081                                         ((data[i] & 0x0f));
1082                                 leftOfPoint = time_tmp / 100;
1083                                 rightOfPoint = time_tmp % 100;
1084                                 break;
1085                         case SDRAM:
1086                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1087                                 if (leftOfPoint > 7) {
1088                                         leftOfPoint = data[i] & 0x70 >> 4;
1089                                         sign = -1;
1090                                 }
1091                                 rightOfPoint = (data[i] & 0x0f);
1092                                 break;
1093                         }
1094                         dimmInfo->addrAndCommandSetupTime =
1095                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1096                         DP (printf
1097                             ("Address And Command Setup Time [ns]:              %d.%d\n",
1098                              sign * leftOfPoint, rightOfPoint));
1099                         break;
1100 /*------------------------------------------------------------------------------------------------------------------------------*/
1101
1102                 case 33:        /* Address And Command Hold Time */
1103                         sign = 1;
1104                         switch (dimmInfo->memoryType) {
1105                         case DDR:
1106                                 time_tmp =
1107                                         (((data[i] & 0xf0) >> 4) * 10) +
1108                                         ((data[i] & 0x0f));
1109                                 leftOfPoint = time_tmp / 100;
1110                                 rightOfPoint = time_tmp % 100;
1111                                 break;
1112                         case SDRAM:
1113                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1114                                 if (leftOfPoint > 7) {
1115                                         leftOfPoint = data[i] & 0x70 >> 4;
1116                                         sign = -1;
1117                                 }
1118                                 rightOfPoint = (data[i] & 0x0f);
1119                                 break;
1120                         }
1121                         dimmInfo->addrAndCommandHoldTime =
1122                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1123                         DP (printf
1124                             ("Address And Command Hold Time [ns]:               %d.%d\n",
1125                              sign * leftOfPoint, rightOfPoint));
1126                         break;
1127 /*------------------------------------------------------------------------------------------------------------------------------*/
1128
1129                 case 34:        /* Data Input Setup Time */
1130                         sign = 1;
1131                         switch (dimmInfo->memoryType) {
1132                         case DDR:
1133                                 time_tmp =
1134                                         (((data[i] & 0xf0) >> 4) * 10) +
1135                                         ((data[i] & 0x0f));
1136                                 leftOfPoint = time_tmp / 100;
1137                                 rightOfPoint = time_tmp % 100;
1138                                 break;
1139                         case SDRAM:
1140                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1141                                 if (leftOfPoint > 7) {
1142                                         leftOfPoint = data[i] & 0x70 >> 4;
1143                                         sign = -1;
1144                                 }
1145                                 rightOfPoint = (data[i] & 0x0f);
1146                                 break;
1147                         }
1148                         dimmInfo->dataInputSetupTime =
1149                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1150                         DP (printf
1151                             ("Data Input Setup Time [ns]:                       %d.%d\n",
1152                              sign * leftOfPoint, rightOfPoint));
1153                         break;
1154 /*------------------------------------------------------------------------------------------------------------------------------*/
1155
1156                 case 35:        /* Data Input Hold Time */
1157                         sign = 1;
1158                         switch (dimmInfo->memoryType) {
1159                         case DDR:
1160                                 time_tmp =
1161                                         (((data[i] & 0xf0) >> 4) * 10) +
1162                                         ((data[i] & 0x0f));
1163                                 leftOfPoint = time_tmp / 100;
1164                                 rightOfPoint = time_tmp % 100;
1165                                 break;
1166                         case SDRAM:
1167                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1168                                 if (leftOfPoint > 7) {
1169                                         leftOfPoint = data[i] & 0x70 >> 4;
1170                                         sign = -1;
1171                                 }
1172                                 rightOfPoint = (data[i] & 0x0f);
1173                                 break;
1174                         }
1175                         dimmInfo->dataInputHoldTime =
1176                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1177                         DP (printf
1178                             ("Data Input Hold Time [ns]:                        %d.%d\n\n",
1179                              sign * leftOfPoint, rightOfPoint));
1180                         break;
1181 /*------------------------------------------------------------------------------------------------------------------------------*/
1182                 }
1183         }
1184         /* calculating the sdram density */
1185         for (i = 0;
1186              i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1187              i++) {
1188                 density = density * 2;
1189         }
1190         dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1191                 dimmInfo->sdramWidth;
1192         dimmInfo->numberOfDevices =
1193                 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1194                 dimmInfo->numOfModuleBanks;
1195         devicesForErrCheck =
1196                 (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1197         if ((dimmInfo->errorCheckType == 0x1)
1198             || (dimmInfo->errorCheckType == 0x2)
1199             || (dimmInfo->errorCheckType == 0x3)) {
1200                 dimmInfo->size =
1201                         (dimmInfo->deviceDensity / 8) *
1202                         (dimmInfo->numberOfDevices - devicesForErrCheck);
1203         } else {
1204                 dimmInfo->size =
1205                         (dimmInfo->deviceDensity / 8) *
1206                         dimmInfo->numberOfDevices;
1207         }
1208
1209         /* compute the module DRB size */
1210         tmp = (1 <<
1211                (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1212         tmp *= dimmInfo->numOfModuleBanks;
1213         tmp *= dimmInfo->sdramWidth;
1214         tmp = tmp >> 24;        /* div by 0x4000000 (64M)       */
1215         dimmInfo->drb_size = (uchar) tmp;
1216         DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
1217
1218         /* try a CAS latency of 3 first... */
1219
1220         /* bit 1 is CL2, bit 2 is CL3 */
1221         supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1222
1223         cal_val = 0;
1224         if (supp_cal & 8) {
1225                 if (NS10to10PS (data[9]) <= tmemclk)
1226                         cal_val = 6;
1227         }
1228         if (supp_cal & 4) {
1229                 if (NS10to10PS (data[9]) <= tmemclk)
1230                         cal_val = 5;
1231         }
1232
1233         /* then 2... */
1234         if (supp_cal & 2) {
1235                 if (NS10to10PS (data[23]) <= tmemclk)
1236                         cal_val = 4;
1237         }
1238
1239         DP (printf ("cal_val = %d\n", cal_val * 5));
1240
1241         /* bummer, did't work... */
1242         if (cal_val == 0) {
1243                 DP (printf ("Couldn't find a good CAS latency\n"));
1244                 hang ();
1245                 return 0;
1246         }
1247
1248         return true;
1249 }
1250
1251 /* sets up the GT properly with information passed in */
1252 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1253 {
1254         ulong tmp;
1255         ulong tmp_sdram_mode = 0;       /* 0x141c */
1256         ulong tmp_dunit_control_low = 0;        /* 0x1404 */
1257         uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
1258         int i;
1259
1260         /* sanity checking */
1261         if (!info->numOfModuleBanks) {
1262                 printf ("setup_sdram called with 0 banks\n");
1263                 return 1;
1264         }
1265
1266         /* delay line */
1267
1268         /* Program the GT with the discovered data */
1269         if (info->registeredAddrAndControlInputs == true)
1270                 DP (printf
1271                     ("Module is registered, but we do not support registered Modules !!!\n"));
1272
1273         /* delay line */
1274         set_dfcdlInit ();       /* may be its not needed */
1275         DP (printf ("Delay line set done\n"));
1276
1277         /* set SDRAM mode NOP */ /* To_do check it */
1278         GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1279         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1280                 DP (printf
1281                     ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
1282         }
1283
1284 #ifdef CONFIG_MV64360_ECC
1285         if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
1286                 /* DRAM has ECC, so turn it on */
1287                 sdram_config_reg |= BIT18;
1288                 DP(printf("Enabling ECC\n"));
1289         }
1290 #endif /* of ifdef CONFIG_MV64360_ECC */
1291
1292         /* SDRAM configuration */
1293         GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
1294         DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
1295
1296         /* SDRAM open pages controll keep open as much as I can */
1297         GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1298         DP (printf
1299             ("sdram_open_pages_controll 0x1414: %08x\n",
1300              GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
1301
1302
1303         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1304         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1305         if (tmp == 0)
1306                 DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
1307         else
1308                 DP (printf
1309                     ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
1310
1311         /* SDRAM set CAS Lentency according to SPD information */
1312         switch (info->memoryType) {
1313         case SDRAM:
1314                 DP (printf ("### SD-RAM not supported yet !!!\n"));
1315                 hang ();
1316                 /* ToDo fill SD-RAM if needed !!!!! */
1317                 break;
1318
1319         case DDR:
1320                 DP (printf ("### SET-CL for DDR-RAM\n"));
1321
1322                 switch (info->maxClSupported_DDR) {
1323                 case DDR_CL_3:
1324                         tmp_dunit_control_low = 0x3c000000;     /* Read-Data sampled on falling edge of Clk */
1325                         tmp_sdram_mode = 0x32;  /* CL=3 Burstlength = 4 */
1326                         DP (printf
1327                             ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1328                              tmp_sdram_mode, tmp_dunit_control_low));
1329                         break;
1330
1331                 case DDR_CL_2_5:
1332                         if (tmp == 1) { /* clocks sync */
1333                                 tmp_dunit_control_low = 0x24000000;     /* Read-Data sampled on falling edge of Clk */
1334                                 tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1335                                 DP (printf
1336                                     ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1337                                      tmp_sdram_mode, tmp_dunit_control_low));
1338                         } else {        /* clk sync. bypassed     */
1339
1340                                 tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1341                                 tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1342                                 DP (printf
1343                                     ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1344                                      tmp_sdram_mode, tmp_dunit_control_low));
1345                         }
1346                         break;
1347
1348                 case DDR_CL_2:
1349                         if (tmp == 1) { /* Sync */
1350                                 tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1351                                 tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1352                                 DP (printf
1353                                     ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1354                                      tmp_sdram_mode, tmp_dunit_control_low));
1355                         } else {        /* Not sync.      */
1356
1357                                 tmp_dunit_control_low = 0x3b000000;     /* Read-Data sampled on rising edge of Clk */
1358                                 tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1359                                 DP (printf
1360                                     ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1361                                      tmp_sdram_mode, tmp_dunit_control_low));
1362                         }
1363                         break;
1364
1365                 case DDR_CL_1_5:
1366                         if (tmp == 1) { /* Sync */
1367                                 tmp_dunit_control_low = 0x23000000;     /* Read-Data sampled on falling edge of Clk */
1368                                 tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1369                                 DP (printf
1370                                     ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1371                                      tmp_sdram_mode, tmp_dunit_control_low));
1372                         } else {        /* not sync */
1373
1374                                 tmp_dunit_control_low = 0x1a000000;     /* Read-Data sampled on rising edge of Clk */
1375                                 tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1376                                 DP (printf
1377                                     ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1378                                      tmp_sdram_mode, tmp_dunit_control_low));
1379                         }
1380                         break;
1381
1382                 default:
1383                         printf ("Max. CL is out of range %d\n",
1384                                 info->maxClSupported_DDR);
1385                         hang ();
1386                         break;
1387                 }
1388                 break;
1389         }
1390
1391         /* Write results of CL detection procedure */
1392         GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1393         /* set SDRAM mode SetCommand 0x1418 */
1394         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1395         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1396                 DP (printf
1397                     ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1398         }
1399
1400
1401         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1402         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1403         if (tmp != 1) {         /*clocks are not sync */
1404                 /* asyncmode */
1405                 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1406                               (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1407                               0x18110780 | tmp_dunit_control_low);
1408         } else {
1409                 /* syncmode */
1410                 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1411                               (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1412                               0x00110000 | tmp_dunit_control_low);
1413         }
1414
1415         /* set SDRAM mode SetCommand 0x1418 */
1416         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1417         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1418                 DP (printf
1419                     ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
1420         }
1421
1422 /*------------------------------------------------------------------------------ */
1423
1424
1425         /* bank parameters */
1426         /* SDRAM address decode register */
1427         /* program this with the default value */
1428         tmp = 0x02;
1429
1430
1431         DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
1432         switch (info->drb_size) {
1433         case 1:         /* 64 Mbit */
1434         case 2:         /* 128 Mbit */
1435                 DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
1436                 tmp |= (0x00 << 4);
1437                 break;
1438         case 4:         /* 256 Mbit */
1439         case 8:         /* 512 Mbit */
1440                 DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
1441                 tmp |= (0x01 << 4);
1442                 break;
1443         case 16:                /* 1 Gbit */
1444         case 32:                /* 2 Gbit */
1445                 DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
1446                 tmp |= (0x02 << 4);
1447                 break;
1448         default:
1449                 printf ("Error in dram size calculation\n");
1450                 DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
1451                 tmp |= (0x02 << 4);
1452                 return 1;
1453         }
1454
1455         /* SDRAM bank parameters */
1456         /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1457         DP (printf
1458             ("setting up slot %d config with: %08lx \n", info->slot, tmp));
1459         GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1460
1461 /* ------------------------------------------------------------------------------ */
1462
1463         DP (printf
1464             ("setting up sdram_timing_control_low with: %08x \n",
1465              0x11511220));
1466         GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1467
1468
1469 /* ------------------------------------------------------------------------------ */
1470
1471         /* SDRAM configuration */
1472         tmp = GTREGREAD (SDRAM_CONFIG);
1473
1474         if (info->registeredAddrAndControlInputs
1475             || info->registeredDQMBinputs) {
1476                 tmp |= (1 << 17);
1477                 DP (printf
1478                     ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1479                      info->registeredAddrAndControlInputs,
1480                      info->registeredDQMBinputs));
1481         }
1482
1483         /* Use buffer 1 to return read data to the CPU
1484          * Page 426 MV64360 */
1485         tmp |= (1 << 26);
1486         DP (printf
1487             ("Before Buffer assignment - sdram_conf: %08x\n",
1488              GTREGREAD (SDRAM_CONFIG)));
1489         DP (printf
1490             ("After Buffer assignment - sdram_conf: %08x\n",
1491              GTREGREAD (SDRAM_CONFIG)));
1492
1493         /* SDRAM timing To_do: */
1494
1495
1496         tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1497         DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp));
1498
1499         /* SDRAM address decode register */
1500         /* program this with the default value */
1501         tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1502         DP (printf
1503             ("SDRAM address control (before: decode): %08x  ",
1504              GTREGREAD (SDRAM_ADDR_CONTROL)));
1505         GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1506         DP (printf
1507             ("SDRAM address control (after: decode): %08x\n",
1508              GTREGREAD (SDRAM_ADDR_CONTROL)));
1509
1510         /* set the SDRAM configuration for each bank */
1511
1512 /*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1513         {
1514                 int l, l1;
1515
1516                 i = info->slot;
1517                 DP (printf
1518                     ("\n*** Running a MRS cycle for bank %d ***\n", i));
1519
1520                 /* map the bank */
1521                 memory_map_bank (i, 0, GB / 4);
1522 #if 1                           /* test only */
1523
1524                 tmp = GTREGREAD (SDRAM_MODE);
1525                 GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
1526                 GT_REG_WRITE (SDRAM_OPERATION, 0x4);
1527                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1528                         DP (printf
1529                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1530                 }
1531
1532                 GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
1533                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1534                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1535                         DP (printf
1536                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1537                 }
1538                 l1 = 0;
1539                 for (l=0;l<200;l++)
1540                         l1 += GTREGREAD (SDRAM_OPERATION);
1541
1542                 GT_REG_WRITE (SDRAM_MODE, tmp);
1543                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1544                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1545                         DP (printf
1546                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1547                 }
1548
1549                 /* switch back to normal operation mode */
1550                 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1551                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1552                         DP (printf
1553                             ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1554                 }
1555
1556 #endif /* test only */
1557                 /* unmap the bank */
1558                 memory_map_bank (i, 0, 0);
1559         }
1560
1561         return 0;
1562 }
1563
1564 /*
1565  * Check memory range for valid RAM. A simple memory test determines
1566  * the actually available RAM size between addresses `base' and
1567  * `base + maxsize'. Some (not all) hardware errors are detected:
1568  * - short between address lines
1569  * - short between data lines
1570  */
1571 long int
1572 dram_size(long int *base, long int maxsize)
1573 {
1574     volatile long int    *addr, *b=base;
1575     long int     cnt, val, save1, save2;
1576
1577 #define STARTVAL (1<<20)        /* start test at 1M */
1578     for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1579             addr = base + cnt;  /* pointer arith! */
1580
1581             save1 = *addr;              /* save contents of addr */
1582             save2 = *b;         /* save contents of base */
1583
1584             *addr=cnt;          /* write cnt to addr */
1585             *b=0;                       /* put null at base */
1586
1587             /* check at base address */
1588             if ((*b) != 0) {
1589                 *addr=save1;    /* restore *addr */
1590                 *b=save2;       /* restore *b */
1591                 return (0);
1592             }
1593             val = *addr;                /* read *addr */
1594             val = *addr;                /* read *addr */
1595
1596             *addr=save1;
1597             *b=save2;
1598
1599             if (val != cnt) {
1600                     DP(printf("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
1601                     /* fix boundary condition.. STARTVAL means zero */
1602                     if(cnt==STARTVAL/sizeof(long)) cnt=0;
1603                     return (cnt * sizeof(long));
1604             }
1605     }
1606     return maxsize;
1607 }
1608
1609 #ifdef CONFIG_MV64360_ECC
1610 /*
1611  * mv_dma_is_channel_active:
1612  * Checks if a engine is busy.
1613  */
1614 int mv_dma_is_channel_active(int engine)
1615 {
1616         ulong data;
1617
1618         data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
1619         if (data & BIT14)       /* activity status */
1620                 return 1;
1621
1622         return 0;
1623 }
1624
1625 /*
1626  * mv_dma_set_memory_space:
1627  * Set a DMA memory window for the DMA's address decoding map.
1628  */
1629 int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
1630                             ulong mem_space_attr, ulong base_address,
1631                             ulong size)
1632 {
1633         ulong temp;
1634
1635         /* The base address must be aligned to the size.  */
1636         if (base_address % size != 0)
1637                 return 0;
1638
1639         if (size >= 0x10000) {
1640                 size &= 0xffff0000;
1641                 base_address = (base_address & 0xffff0000);
1642                 /* Set the new attributes */
1643                 GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
1644                              (base_address | mem_space_target |
1645                               mem_space_attr));
1646                 GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
1647                              (size - 1) & 0xffff0000);
1648                 temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
1649                 GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
1650                              (temp & ~(BIT0 << mem_space)));
1651                 return 1;
1652         }
1653
1654         return 0;
1655 }
1656
1657
1658 /*
1659  * mv_dma_transfer:
1660  * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
1661  */
1662 int mv_dma_transfer(int engine, ulong source_addr,
1663                     ulong dest_addr, ulong bytes, ulong command)
1664 {
1665         ulong eng_off_reg;      /* Engine Offset Register */
1666
1667         if (bytes > 0xffff)
1668                 command = command | BIT31;       /* DMA_16M_DESCRIPTOR_MODE */
1669
1670         command = command | ((command >> 6) & 0x7);
1671         eng_off_reg = engine * 4;
1672         GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
1673                      bytes);
1674         GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
1675                      source_addr);
1676         GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
1677                      dest_addr);
1678         command |= BIT12        /* DMA_CHANNEL_ENABLE */
1679                 | BIT9;         /* DMA_NON_CHAIN_MODE */
1680
1681         /* Activate DMA engine By writting to mv_dma_control_register */
1682         GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
1683
1684         return 1;
1685 }
1686 #endif /* of ifdef CONFIG_MV64360_ECC */
1687
1688 /* ppcboot interface function to SDRAM init - this is where all the
1689  * controlling logic happens */
1690 phys_size_t
1691 initdram(int board_type)
1692 {
1693         int s0 = 0, s1 = 0;
1694         int checkbank[4] = { [0 ... 3] = 0 };
1695         ulong realsize, total, check;
1696         AUX_MEM_DIMM_INFO dimmInfo1;
1697         AUX_MEM_DIMM_INFO dimmInfo2;
1698         int bank_no, nhr;
1699 #ifdef CONFIG_MV64360_ECC
1700         ulong dest, mem_space_attr;
1701 #endif /* of ifdef CONFIG_MV64360_ECC */
1702
1703         /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1704
1705         /* check the NHR bit and skip mem init if it's already done */
1706         nhr = get_hid0() & (1 << 16);
1707
1708         if (nhr) {
1709                 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1710         } else {
1711                 /* DIMM0 */
1712                 s0 = check_dimm(0, &dimmInfo1);
1713
1714                 /* DIMM1 */
1715                 s1 = check_dimm(1, &dimmInfo2);
1716
1717                 memory_map_bank(0, 0, 0);
1718                 memory_map_bank(1, 0, 0);
1719                 memory_map_bank(2, 0, 0);
1720                 memory_map_bank(3, 0, 0);
1721
1722                 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1723                         printf("Setup for DIMM1 failed.\n");
1724                 }
1725
1726                 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1727                         printf("Setup for DIMM2 failed.\n");
1728                 }
1729
1730                 /* set the NHR bit */
1731                 set_hid0(get_hid0() | (1 << 16));
1732         }
1733         /* next, size the SDRAM banks */
1734
1735         realsize = total = 0;
1736         check = GB/4;
1737         if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1738         if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1739         if (dimmInfo1.numOfModuleBanks > 2)
1740                 printf("Error, SPD claims DIMM1 has >2 banks\n");
1741
1742         if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1743         if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1744         if (dimmInfo2.numOfModuleBanks > 2)
1745                 printf("Error, SPD claims DIMM2 has >2 banks\n");
1746
1747         for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1748                 /* skip over banks that are not populated */
1749                 if (! checkbank[bank_no])
1750                         continue;
1751
1752                 if ((total + check) > CONFIG_SYS_GT_REGS)
1753                         check = CONFIG_SYS_GT_REGS - total;
1754
1755                 memory_map_bank(bank_no, total, check);
1756                 realsize = dram_size((long int *)total, check);
1757                 memory_map_bank(bank_no, total, realsize);
1758
1759 #ifdef CONFIG_MV64360_ECC
1760                 if (((dimmInfo1.errorCheckType != 0) &&
1761                      ((dimmInfo2.errorCheckType != 0) ||
1762                       (dimmInfo2.numOfModuleBanks == 0))) &&
1763                     (CPCI750_ECC_TEST)) {
1764                         printf("ECC Initialization of Bank %d:", bank_no);
1765                         mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1766                         mv_dma_set_memory_space(0, 0, mem_space_attr, total,
1767                                                 realsize);
1768                         for (dest = total; dest < total + realsize;
1769                              dest += _8M) {
1770                                 mv_dma_transfer(0, total, dest, _8M,
1771                                                 BIT8 |  /* DMA_DTL_128BYTES */
1772                                                 BIT3 |  /* DMA_HOLD_SOURCE_ADDR */
1773                                                 BIT11); /* DMA_BLOCK_TRANSFER_MODE */
1774                                 while (mv_dma_is_channel_active(0))
1775                                         ;
1776                         }
1777                         printf(" PASS\n");
1778                 }
1779 #endif /* of ifdef CONFIG_MV64360_ECC */
1780
1781                 total += realsize;
1782         }
1783
1784 /*      Setup Ethernet DMA Adress window to DRAM Area */
1785         return(total);
1786 }
1787
1788 /* ***************************************************************************************
1789 ! *                             SDRAM INIT                                              *
1790 ! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb       *
1791 ! *               This procedure fits only the Atlantis                                *
1792 ! *                                                                                     *
1793 ! *************************************************************************************** */
1794
1795
1796 /* ***************************************************************************************
1797 ! *                             DFCDL initialize MV643xx Design Considerations             *
1798 ! *                                                                                     *
1799 ! *************************************************************************************** */
1800 int set_dfcdlInit (void)
1801 {
1802         int i;
1803         unsigned int dfcdl_word = 0x0000014f;
1804
1805         for (i = 0; i < 64; i++) {
1806                 GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1807         }
1808         GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);       /* enable dynamic delay line updating */
1809
1810
1811         return (0);
1812 }
1813
1814 int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
1815 {
1816         unsigned int ecc_counter;
1817         unsigned int ecc_addr;
1818
1819         GT_REG_READ(0x1458, &ecc_counter);
1820         GT_REG_READ(0x1450, &ecc_addr);
1821         GT_REG_WRITE(0x1450, 0);
1822
1823         printf("Error Counter since Reset:  %8d\n", ecc_counter);
1824         printf("Last error address       :0x%08x (" , ecc_addr & 0xfffffff8);
1825         if (ecc_addr & 0x01)
1826                 printf("double");
1827         else
1828                 printf("single");
1829         printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
1830
1831         return 0;
1832 }
1833
1834
1835 U_BOOT_CMD(
1836         show_ecc, 1, 1, do_show_ecc,
1837         "Show Marvell MV64360 ECC Info",
1838         "Show Marvell MV64360 ECC Counter and last error."
1839 );