board/esd/cpci750/sdram_init.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * adaption for the Marvell DB64360 Board
  26  * Ingo Assmus (ingo.assmus@keymile.com)
  27  *
  28  * adaption for the cpci750 Board
  29  * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
  30  *************************************************************************/
  31
  32
  33 /* sdram_init.c - automatic memory sizing */
  34
  35 #include <common.h>
  36 #include <74xx_7xx.h>
  37 #include "../../Marvell/include/memory.h"
  38 #include "../../Marvell/include/pci.h"
  39 #include "../../Marvell/include/mv_gen_reg.h"
  40 #include <net.h>
  41
  42 #include "eth.h"
  43 #include "mpsc.h"
  44 #include "../../Marvell/common/i2c.h"
  45 #include "64360.h"
  46 #include "mv_regs.h"
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 int set_dfcdlInit(void);        /* setup delay line of Mv64360 */
  51
  52 /* ------------------------------------------------------------------------- */
  53
  54 int
  55 memory_map_bank(unsigned int bankNo,
  56                 unsigned int bankBase,
  57                 unsigned int bankLength)
  58 {
  59 #ifdef MAP_PCI
  60         PCI_HOST host;
  61 #endif
  62
  63
  64 #ifdef DEBUG
  65         if (bankLength > 0) {
  66                 printf("mapping bank %d at %08x - %08x\n",
  67                        bankNo, bankBase, bankBase + bankLength - 1);
  68         } else {
  69                 printf("unmapping bank %d\n", bankNo);
  70         }
  71 #endif
  72
  73         memoryMapBank(bankNo, bankBase, bankLength);
  74
  75 #ifdef MAP_PCI
  76         for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
  77                 const int features=
  78                         PREFETCH_ENABLE |
  79                         DELAYED_READ_ENABLE |
  80                         AGGRESSIVE_PREFETCH |
  81                         READ_LINE_AGGRESSIVE_PREFETCH |
  82                         READ_MULTI_AGGRESSIVE_PREFETCH |
  83                         MAX_BURST_4 |
  84                         PCI_NO_SWAP;
  85
  86                 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
  87
  88                 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
  89                                 bankLength);
  90
  91                 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
  92         }
  93 #endif
  94         return 0;
  95 }
  96
  97 #define GB         (1 << 30)
  98
  99 /* much of this code is based on (or is) the code in the pip405 port */
 100 /* thanks go to the authors of said port - Josh */
 101
 102 /* structure to store the relevant information about an sdram bank */
 103 typedef struct sdram_info {
 104         uchar drb_size;
 105         uchar registered, ecc;
 106         uchar tpar;
 107         uchar tras_clocks;
 108         uchar burst_len;
 109         uchar banks, slot;
 110 } sdram_info_t;
 111
 112 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
 113
 114 typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
 115
 116 typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
 117                                 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
 118                                } VOLTAGE_INTERFACE;
 119
 120 typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
 121 typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
 122
 123
 124 /* SDRAM/DDR information struct */
 125 typedef struct _gtMemoryDimmInfo {
 126         MEMORY_TYPE memoryType;
 127         unsigned int numOfRowAddresses;
 128         unsigned int numOfColAddresses;
 129         unsigned int numOfModuleBanks;
 130         unsigned int dataWidth;
 131         VOLTAGE_INTERFACE voltageInterface;
 132         unsigned int errorCheckType;                    /* ECC , PARITY.. */
 133         unsigned int sdramWidth;                        /* 4,8,16 or 32 */ ;
 134         unsigned int errorCheckDataWidth;               /* 0 - no, 1 - Yes */
 135         unsigned int minClkDelay;
 136         unsigned int burstLengthSupported;
 137         unsigned int numOfBanksOnEachDevice;
 138         unsigned int suportedCasLatencies;
 139         unsigned int RefreshInterval;
 140         unsigned int maxCASlatencySupported_LoP;        /* LoP left of point (measured in ns) */
 141         unsigned int maxCASlatencySupported_RoP;        /* RoP right of point (measured in ns) */
 142         MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
 143         MAX_CL_SUPPORTED_SD maxClSupported_SD;
 144         unsigned int moduleBankDensity;
 145         /* module attributes (true for yes) */
 146         bool bufferedAddrAndControlInputs;
 147         bool registeredAddrAndControlInputs;
 148         bool onCardPLL;
 149         bool bufferedDQMBinputs;
 150         bool registeredDQMBinputs;
 151         bool differentialClockInput;
 152         bool redundantRowAddressing;
 153
 154         /* module general attributes */
 155         bool suportedAutoPreCharge;
 156         bool suportedPreChargeAll;
 157         bool suportedEarlyRasPreCharge;
 158         bool suportedWrite1ReadBurst;
 159         bool suported5PercentLowVCC;
 160         bool suported5PercentUpperVCC;
 161         /* module timing parameters */
 162         unsigned int minRasToCasDelay;
 163         unsigned int minRowActiveRowActiveDelay;
 164         unsigned int minRasPulseWidth;
 165         unsigned int minRowPrechargeTime;               /* measured in ns */
 166
 167         int addrAndCommandHoldTime;                     /* LoP left of point (measured in ns) */
 168         int addrAndCommandSetupTime;                    /* (measured in ns/100) */
 169         int dataInputSetupTime;                         /* LoP left of point (measured in ns) */
 170         int dataInputHoldTime;                          /* LoP left of point (measured in ns) */
 171 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
 172         unsigned int clockToDataOut_LoP;                /* LoP left of point (measured in ns) */
 173         unsigned int clockToDataOut_RoP;                /* RoP right of point (measured in ns) */
 174         unsigned int clockToDataOutMinus1_LoP;          /* LoP left of point (measured in ns) */
 175         unsigned int clockToDataOutMinus1_RoP;          /* RoP right of point (measured in ns) */
 176         unsigned int clockToDataOutMinus2_LoP;          /* LoP left of point (measured in ns) */
 177         unsigned int clockToDataOutMinus2_RoP;          /* RoP right of point (measured in ns) */
 178
 179         unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;       /* LoP left of point (measured in ns) */
 180         unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;       /* RoP right of point (measured in ns) */
 181
 182         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
 183         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
 184
 185         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
 186         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
 187
 188         /* Parameters calculated from
 189            the extracted DIMM information */
 190         unsigned int size;
 191         unsigned int deviceDensity;                     /* 16,64,128,256 or 512 Mbit */
 192         unsigned int numberOfDevices;
 193         uchar drb_size;                                 /* DRAM size in n*64Mbit */
 194         uchar slot;                                     /* Slot Number this module is inserted in */
 195         uchar spd_raw_data[128];                        /* Content of SPD-EEPROM copied 1:1 */
 196 #ifdef DEBUG
 197         uchar manufactura[8];                           /* Content of SPD-EEPROM Byte 64-71 */
 198         uchar modul_id[18];                             /* Content of SPD-EEPROM Byte 73-90 */
 199         uchar vendor_data[27];                          /* Content of SPD-EEPROM Byte 99-125 */
 200         unsigned long modul_serial_no;                  /* Content of SPD-EEPROM Byte 95-98 */
 201         unsigned int manufac_date;                      /* Content of SPD-EEPROM Byte 93-94 */
 202         unsigned int modul_revision;                    /* Content of SPD-EEPROM Byte 91-92 */
 203         uchar manufac_place;                            /* Content of SPD-EEPROM Byte 72 */
 204
 205 #endif
 206 } AUX_MEM_DIMM_INFO;
 207
 208
 209 /*
 210  * translate ns.ns/10 coding of SPD timing values
 211  * into 10 ps unit values
 212  */
 213 static inline unsigned short
 214 NS10to10PS(unsigned char spd_byte)
 215 {
 216         unsigned short ns, ns10;
 217
 218         /* isolate upper nibble */
 219         ns = (spd_byte >> 4) & 0x0F;
 220         /* isolate lower nibble */
 221         ns10 = (spd_byte & 0x0F);
 222
 223         return(ns*100 + ns10*10);
 224 }
 225
 226 /*
 227  * translate ns coding of SPD timing values
 228  * into 10 ps unit values
 229  */
 230 static inline unsigned short
 231 NSto10PS(unsigned char spd_byte)
 232 {
 233         return(spd_byte*100);
 234 }
 235
 236 /* This code reads the SPD chip on the sdram and populates
 237  * the array which is passed in with the relevant information */
 238 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 239 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 240 {
 241         uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 242         int ret;
 243         unsigned int i, j, density = 1, devicesForErrCheck = 0;
 244
 245 #ifdef DEBUG
 246         unsigned int k;
 247 #endif
 248         unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
 249         int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
 250         uchar supp_cal, cal_val;
 251         ulong memclk, tmemclk;
 252         ulong tmp;
 253         uchar trp_clocks = 0, tras_clocks;
 254         uchar data[128];
 255
 256         memclk = gd->bus_clk;
 257         tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
 258
 259         memset (data, 0, sizeof (data));
 260
 261
 262         ret = 0;
 263
 264         debug("before i2c read\n");
 265
 266         ret = i2c_read (addr, 0, 2, data, 128);
 267
 268         debug("after i2c read\n");
 269
 270         if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
 271             || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
 272             || (data[70] != 'b') || (data[71] != 'h')) {
 273                 ret = -1;
 274         }
 275
 276         if ((ret != 0) && (slot == 0)) {
 277                 memset (data, 0, sizeof (data));
 278                 data[0] = 0x80;
 279                 data[1] = 0x08;
 280                 data[2] = 0x07;
 281                 data[3] = 0x0c;
 282                 data[4] = 0x09;
 283                 data[5] = 0x01;
 284                 data[6] = 0x48;
 285                 data[7] = 0x00;
 286                 data[8] = 0x04;
 287                 data[9] = 0x75;
 288                 data[10] = 0x80;
 289                 data[11] = 0x02;
 290                 data[12] = 0x80;
 291                 data[13] = 0x10;
 292                 data[14] = 0x08;
 293                 data[15] = 0x01;
 294                 data[16] = 0x0e;
 295                 data[17] = 0x04;
 296                 data[18] = 0x0c;
 297                 data[19] = 0x01;
 298                 data[20] = 0x02;
 299                 data[21] = 0x20;
 300                 data[22] = 0x00;
 301                 data[23] = 0xa0;
 302                 data[24] = 0x80;
 303                 data[25] = 0x00;
 304                 data[26] = 0x00;
 305                 data[27] = 0x50;
 306                 data[28] = 0x3c;
 307                 data[29] = 0x50;
 308                 data[30] = 0x32;
 309                 data[31] = 0x10;
 310                 data[32] = 0xb0;
 311                 data[33] = 0xb0;
 312                 data[34] = 0x60;
 313                 data[35] = 0x60;
 314                 data[64] = 'e';
 315                 data[65] = 's';
 316                 data[66] = 'd';
 317                 data[67] = '-';
 318                 data[68] = 'g';
 319                 data[69] = 'm';
 320                 data[70] = 'b';
 321                 data[71] = 'h';
 322                 ret = 0;
 323         }
 324
 325         /* zero all the values */
 326         memset (dimmInfo, 0, sizeof (*dimmInfo));
 327
 328         /* copy the SPD content 1:1 into the dimmInfo structure */
 329         for (i = 0; i <= 127; i++) {
 330                 dimmInfo->spd_raw_data[i] = data[i];
 331         }
 332
 333         if (ret) {
 334                 debug("No DIMM in slot %d [err = %x]\n", slot, ret);
 335                 return 0;
 336         } else
 337                 dimmInfo->slot = slot;  /* start to fill up dimminfo for this "slot" */
 338
 339 #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 340
 341         for (i = 0; i <= 127; i++) {
 342                 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
 343                         data[i]);
 344         }
 345
 346 #endif
 347 #ifdef DEBUG
 348         /* find Manufacturer of Dimm Module */
 349         for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
 350                 dimmInfo->manufactura[i] = data[64 + i];
 351         }
 352         printf ("\nThis RAM-Module is produced by:              %s\n",
 353                 dimmInfo->manufactura);
 354
 355         /* find Manul-ID of Dimm Module */
 356         for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
 357                 dimmInfo->modul_id[i] = data[73 + i];
 358         }
 359         printf ("The Module-ID of this RAM-Module is:           %s\n",
 360                 dimmInfo->modul_id);
 361
 362         /* find Vendor-Data of Dimm Module */
 363         for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
 364                 dimmInfo->vendor_data[i] = data[99 + i];
 365         }
 366         printf ("Vendor Data of this RAM-Module is:             %s\n",
 367                 dimmInfo->vendor_data);
 368
 369         /* find modul_serial_no of Dimm Module */
 370         dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
 371         printf ("Serial No. of this RAM-Module is:              %ld (%lx)\n",
 372                 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 373
 374         /* find Manufac-Data of Dimm Module */
 375         dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
 376         printf ("Manufactoring Date of this RAM-Module is:      %d.%d\n", data[93], data[94]);  /*dimmInfo->manufac_date */
 377
 378         /* find modul_revision of Dimm Module */
 379         dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
 380         printf ("Module Revision of this RAM-Module is:                 %d.%d\n", data[91], data[92]);  /* dimmInfo->modul_revision */
 381
 382         /* find manufac_place of Dimm Module */
 383         dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
 384         printf ("manufac_place of this RAM-Module is:           %d\n",
 385                 dimmInfo->manufac_place);
 386
 387 #endif
 388 /*------------------------------------------------------------------------------------------------------------------------------*/
 389 /* calculate SPD checksum */
 390 /*------------------------------------------------------------------------------------------------------------------------------*/
 391 #if 0                           /* test-only */
 392         spd_checksum = 0;
 393
 394         for (i = 0; i <= 62; i++) {
 395                 spd_checksum += data[i];
 396         }
 397
 398         if ((spd_checksum & 0xff) != data[63]) {
 399                 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
 400                 hang ();
 401         }
 402
 403         else
 404                 printf ("SPD Checksum ok!\n");
 405 #endif /* test-only */
 406
 407 /*------------------------------------------------------------------------------------------------------------------------------*/
 408         for (i = 2; i <= 35; i++) {
 409                 switch (i) {
 410                 case 2: /* Memory type (DDR / SDRAM) */
 411                         dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
 412 #ifdef DEBUG
 413                         if (dimmInfo->memoryType == 0)
 414                                 debug("Dram_type in slot %d is:                 SDRAM\n",
 415                                      dimmInfo->slot);
 416                         if (dimmInfo->memoryType == 1)
 417                                 debug("Dram_type in slot %d is:                 DDRAM\n",
 418                                      dimmInfo->slot);
 419 #endif
 420                         break;
 421 /*------------------------------------------------------------------------------------------------------------------------------*/
 422
 423                 case 3: /* Number Of Row Addresses */
 424                         dimmInfo->numOfRowAddresses = data[i];
 425                         debug("Module Number of row addresses:          %d\n",
 426                              dimmInfo->numOfRowAddresses);
 427                         break;
 428 /*------------------------------------------------------------------------------------------------------------------------------*/
 429
 430                 case 4: /* Number Of Column Addresses */
 431                         dimmInfo->numOfColAddresses = data[i];
 432                         debug("Module Number of col addresses:          %d\n",
 433                              dimmInfo->numOfColAddresses);
 434                         break;
 435 /*------------------------------------------------------------------------------------------------------------------------------*/
 436
 437                 case 5: /* Number Of Module Banks */
 438                         dimmInfo->numOfModuleBanks = data[i];
 439                         debug("Number of Banks on Mod. :                                %d\n",
 440                              dimmInfo->numOfModuleBanks);
 441                         break;
 442 /*------------------------------------------------------------------------------------------------------------------------------*/
 443
 444                 case 6: /* Data Width */
 445                         dimmInfo->dataWidth = data[i];
 446                         debug("Module Data Width:                               %d\n",
 447                              dimmInfo->dataWidth);
 448                         break;
 449 /*------------------------------------------------------------------------------------------------------------------------------*/
 450
 451                 case 8: /* Voltage Interface */
 452                         switch (data[i]) {
 453                         case 0x0:
 454                                 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
 455                                 debug("Module is                                        TTL_5V_TOLERANT\n");
 456                                 break;
 457                         case 0x1:
 458                                 dimmInfo->voltageInterface = LVTTL;
 459                                 debug("Module is                                        LVTTL\n");
 460                                 break;
 461                         case 0x2:
 462                                 dimmInfo->voltageInterface = HSTL_1_5V;
 463                                 debug("Module is                                        TTL_5V_TOLERANT\n");
 464                                 break;
 465                         case 0x3:
 466                                 dimmInfo->voltageInterface = SSTL_3_3V;
 467                                 debug("Module is                                        HSTL_1_5V\n");
 468                                 break;
 469                         case 0x4:
 470                                 dimmInfo->voltageInterface = SSTL_2_5V;
 471                                 debug("Module is                                        SSTL_2_5V\n");
 472                                 break;
 473                         default:
 474                                 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
 475                                 debug("Module is                                        VOLTAGE_UNKNOWN\n");
 476                                 break;
 477                         }
 478                         break;
 479 /*------------------------------------------------------------------------------------------------------------------------------*/
 480
 481                 case 9: /* Minimum Cycle Time At Max CasLatancy */
 482                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 483                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 484                         maskLeftOfPoint =
 485                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 486                         maskRightOfPoint =
 487                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 488                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 489                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 490                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
 491                                 leftOfPoint;
 492                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
 493                                 rightOfPoint;
 494                         debug("Minimum Cycle Time At Max CasLatancy:            %d.%d [ns]\n",
 495                              leftOfPoint, rightOfPoint);
 496                         break;
 497 /*------------------------------------------------------------------------------------------------------------------------------*/
 498
 499                 case 10:        /* Clock To Data Out */
 500                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 501                         time_tmp =
 502                                 (((data[i] & 0xf0) >> 4) * 10) +
 503                                 ((data[i] & 0x0f));
 504                         leftOfPoint = time_tmp / div;
 505                         rightOfPoint = time_tmp % div;
 506                         dimmInfo->clockToDataOut_LoP = leftOfPoint;
 507                         dimmInfo->clockToDataOut_RoP = rightOfPoint;
 508                         debug("Clock To Data Out:                               %d.%2d [ns]\n",
 509                              leftOfPoint, rightOfPoint);
 510                         /*dimmInfo->clockToDataOut */
 511                         break;
 512 /*------------------------------------------------------------------------------------------------------------------------------*/
 513
 514 #ifdef CONFIG_MV64360_ECC
 515                 case 11:        /* Error Check Type */
 516                         dimmInfo->errorCheckType = data[i];
 517                         debug("Error Check Type (0=NONE):                       %d\n",
 518                              dimmInfo->errorCheckType);
 519                         break;
 520 #endif /* of ifdef CONFIG_MV64360_ECC */
 521 /*------------------------------------------------------------------------------------------------------------------------------*/
 522
 523                 case 12:        /* Refresh Interval */
 524                         dimmInfo->RefreshInterval = data[i];
 525                         debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
 526                              dimmInfo->RefreshInterval);
 527                         break;
 528 /*------------------------------------------------------------------------------------------------------------------------------*/
 529
 530                 case 13:        /* Sdram Width */
 531                         dimmInfo->sdramWidth = data[i];
 532                         debug("Sdram Width:                                     %d\n",
 533                              dimmInfo->sdramWidth);
 534                         break;
 535 /*------------------------------------------------------------------------------------------------------------------------------*/
 536
 537                 case 14:        /* Error Check Data Width */
 538                         dimmInfo->errorCheckDataWidth = data[i];
 539                         debug("Error Check Data Width:                  %d\n",
 540                              dimmInfo->errorCheckDataWidth);
 541                         break;
 542 /*------------------------------------------------------------------------------------------------------------------------------*/
 543
 544                 case 15:        /* Minimum Clock Delay */
 545                         dimmInfo->minClkDelay = data[i];
 546                         debug("Minimum Clock Delay:                             %d\n",
 547                              dimmInfo->minClkDelay);
 548                         break;
 549 /*------------------------------------------------------------------------------------------------------------------------------*/
 550
 551                 case 16:        /* Burst Length Supported */
 552                            /******-******-******-*******
 553                            * bit3 | bit2 | bit1 | bit0 *
 554                            *******-******-******-*******
 555             burst length = *  8   |  4   |   2  |   1  *
 556                            *****************************
 557
 558             If for example bit0 and bit2 are set, the burst
 559             length supported are 1 and 4. */
 560
 561                         dimmInfo->burstLengthSupported = data[i];
 562 #ifdef DEBUG
 563                         debug("Burst Length Supported:                  ");
 564                         if (dimmInfo->burstLengthSupported & 0x01)
 565                                 debug("1, ");
 566                         if (dimmInfo->burstLengthSupported & 0x02)
 567                                 debug("2, ");
 568                         if (dimmInfo->burstLengthSupported & 0x04)
 569                                 debug("4, ");
 570                         if (dimmInfo->burstLengthSupported & 0x08)
 571                                 debug("8, ");
 572                         debug(" Bit \n");
 573 #endif
 574                         break;
 575 /*------------------------------------------------------------------------------------------------------------------------------*/
 576
 577                 case 17:        /* Number Of Banks On Each Device */
 578                         dimmInfo->numOfBanksOnEachDevice = data[i];
 579                         debug("Number Of Banks On Each Chip:                    %d\n",
 580                              dimmInfo->numOfBanksOnEachDevice);
 581                         break;
 582 /*------------------------------------------------------------------------------------------------------------------------------*/
 583
 584                 case 18:        /* Suported Cas Latencies */
 585
 586                         /*     DDR:
 587                          *******-******-******-******-******-******-******-*******
 588                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 589                          *******-******-******-******-******-******-******-*******
 590                          CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 591                          *********************************************************
 592                          SDRAM:
 593                          *******-******-******-******-******-******-******-*******
 594                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 595                          *******-******-******-******-******-******-******-*******
 596                          CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
 597                          ********************************************************/
 598                         dimmInfo->suportedCasLatencies = data[i];
 599 #ifdef DEBUG
 600                         debug("Suported Cas Latencies: (CL)                     ");
 601                         if (dimmInfo->memoryType == 0) {        /* SDRAM */
 602                                 for (k = 0; k <= 7; k++) {
 603                                         if (dimmInfo->
 604                                             suportedCasLatencies & (1 << k))
 605                                                 debug("%d,                      ",
 606                                                      k + 1);
 607                                 }
 608
 609                         } else {        /* DDR-RAM */
 610
 611                                 if (dimmInfo->suportedCasLatencies & 1)
 612                                         debug("1, ");
 613                                 if (dimmInfo->suportedCasLatencies & 2)
 614                                         debug("1.5, ");
 615                                 if (dimmInfo->suportedCasLatencies & 4)
 616                                         debug("2, ");
 617                                 if (dimmInfo->suportedCasLatencies & 8)
 618                                         debug("2.5, ");
 619                                 if (dimmInfo->suportedCasLatencies & 16)
 620                                         debug("3, ");
 621                                 if (dimmInfo->suportedCasLatencies & 32)
 622                                         debug("3.5, ");
 623
 624                         }
 625                         debug("\n");
 626 #endif
 627                         /* Calculating MAX CAS latency */
 628                         for (j = 7; j > 0; j--) {
 629                                 if (((dimmInfo->
 630                                       suportedCasLatencies >> j) & 0x1) ==
 631                                     1) {
 632                                         switch (dimmInfo->memoryType) {
 633                                         case DDR:
 634                                                 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
 635                                                 switch (j) {
 636                                                 case 7:
 637                                                         debug("Max. Cas Latencies (DDR):                        ERROR !!!\n");
 638                                                         dimmInfo->
 639                                                                 maxClSupported_DDR
 640                                                                 =
 641                                                                 DDR_CL_FAULT;
 642                                                         hang ();
 643                                                         break;
 644                                                 case 6:
 645                                                         debug("Max. Cas Latencies (DDR):                        ERROR !!!\n");
 646                                                         dimmInfo->
 647                                                                 maxClSupported_DDR
 648                                                                 =
 649                                                                 DDR_CL_FAULT;
 650                                                         hang ();
 651                                                         break;
 652                                                 case 5:
 653                                                         debug("Max. Cas Latencies (DDR):                        3.5 clk's\n");
 654                                                         dimmInfo->
 655                                                                 maxClSupported_DDR
 656                                                                 = DDR_CL_3_5;
 657                                                         break;
 658                                                 case 4:
 659                                                         debug("Max. Cas Latencies (DDR):                        3 clk's \n");
 660                                                         dimmInfo->
 661                                                                 maxClSupported_DDR
 662                                                                 = DDR_CL_3;
 663                                                         break;
 664                                                 case 3:
 665                                                         debug("Max. Cas Latencies (DDR):                        2.5 clk's \n");
 666                                                         dimmInfo->
 667                                                                 maxClSupported_DDR
 668                                                                 = DDR_CL_2_5;
 669                                                         break;
 670                                                 case 2:
 671                                                         debug("Max. Cas Latencies (DDR):                        2 clk's \n");
 672                                                         dimmInfo->
 673                                                                 maxClSupported_DDR
 674                                                                 = DDR_CL_2;
 675                                                         break;
 676                                                 case 1:
 677                                                         debug("Max. Cas Latencies (DDR):                        1.5 clk's \n");
 678                                                         dimmInfo->
 679                                                                 maxClSupported_DDR
 680                                                                 = DDR_CL_1_5;
 681                                                         break;
 682                                                 }
 683                                                 dimmInfo->
 684                                                         maxCASlatencySupported_LoP
 685                                                         =
 686                                                         1 +
 687                                                         (int) (5 * j / 10);
 688                                                 if (((5 * j) % 10) != 0)
 689                                                         dimmInfo->
 690                                                                 maxCASlatencySupported_RoP
 691                                                                 = 5;
 692                                                 else
 693                                                         dimmInfo->
 694                                                                 maxCASlatencySupported_RoP
 695                                                                 = 0;
 696                                                 debug("Max. Cas Latencies (DDR LoP.RoP Notation):       %d.%d \n",
 697                                                      dimmInfo->
 698                                                      maxCASlatencySupported_LoP,
 699                                                      dimmInfo->
 700                                                      maxCASlatencySupported_RoP);
 701                                                 break;
 702                                         case SDRAM:
 703                                                 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
 704                                                 dimmInfo->maxClSupported_SD = j;        /*  Cas Latency DDR-RAM Coded                   */
 705                                                 debug("Max. Cas Latencies (SD): %d\n",
 706                                                      dimmInfo->
 707                                                      maxClSupported_SD);
 708                                                 dimmInfo->
 709                                                         maxCASlatencySupported_LoP
 710                                                         = j;
 711                                                 dimmInfo->
 712                                                         maxCASlatencySupported_RoP
 713                                                         = 0;
 714                                                 debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
 715                                                      dimmInfo->
 716                                                      maxCASlatencySupported_LoP,
 717                                                      dimmInfo->
 718                                                      maxCASlatencySupported_RoP);
 719                                                 break;
 720                                         }
 721                                         break;
 722                                 }
 723                         }
 724                         break;
 725 /*------------------------------------------------------------------------------------------------------------------------------*/
 726
 727                 case 21:        /* Buffered Address And Control Inputs */
 728                         debug("\nModul Attributes (SPD Byte 21): \n");
 729                         dimmInfo->bufferedAddrAndControlInputs =
 730                                 data[i] & BIT0;
 731                         dimmInfo->registeredAddrAndControlInputs =
 732                                 (data[i] & BIT1) >> 1;
 733                         dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
 734                         dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
 735                         dimmInfo->registeredDQMBinputs =
 736                                 (data[i] & BIT4) >> 4;
 737                         dimmInfo->differentialClockInput =
 738                                 (data[i] & BIT5) >> 5;
 739                         dimmInfo->redundantRowAddressing =
 740                                 (data[i] & BIT6) >> 6;
 741
 742                         if (dimmInfo->bufferedAddrAndControlInputs == 1)
 743                                 debug(" - Buffered Address/Control Input:               Yes \n");
 744                         else
 745                                 debug(" - Buffered Address/Control Input:               No \n");
 746
 747                         if (dimmInfo->registeredAddrAndControlInputs == 1)
 748                                 debug(" - Registered Address/Control Input:             Yes \n");
 749                         else
 750                                 debug(" - Registered Address/Control Input:             No \n");
 751
 752                         if (dimmInfo->onCardPLL == 1)
 753                                 debug(" - On-Card PLL (clock):                          Yes \n");
 754                         else
 755                                 debug(" - On-Card PLL (clock):                          No \n");
 756
 757                         if (dimmInfo->bufferedDQMBinputs == 1)
 758                                 debug(" - Bufferd DQMB Inputs:                          Yes \n");
 759                         else
 760                                 debug(" - Bufferd DQMB Inputs:                          No \n");
 761
 762                         if (dimmInfo->registeredDQMBinputs == 1)
 763                                 debug(" - Registered DQMB Inputs:                       Yes \n");
 764                         else
 765                                 debug(" - Registered DQMB Inputs:                       No \n");
 766
 767                         if (dimmInfo->differentialClockInput == 1)
 768                                 debug(" - Differential Clock Input:                     Yes \n");
 769                         else
 770                                 debug(" - Differential Clock Input:                     No \n");
 771
 772                         if (dimmInfo->redundantRowAddressing == 1)
 773                                 debug(" - redundant Row Addressing:                     Yes \n");
 774                         else
 775                                 debug(" - redundant Row Addressing:                     No \n");
 776
 777                         break;
 778 /*------------------------------------------------------------------------------------------------------------------------------*/
 779
 780                 case 22:        /* Suported AutoPreCharge */
 781                         debug("\nModul Attributes (SPD Byte 22): \n");
 782                         dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
 783                         dimmInfo->suportedAutoPreCharge =
 784                                 (data[i] & BIT1) >> 1;
 785                         dimmInfo->suportedPreChargeAll =
 786                                 (data[i] & BIT2) >> 2;
 787                         dimmInfo->suportedWrite1ReadBurst =
 788                                 (data[i] & BIT3) >> 3;
 789                         dimmInfo->suported5PercentLowVCC =
 790                                 (data[i] & BIT4) >> 4;
 791                         dimmInfo->suported5PercentUpperVCC =
 792                                 (data[i] & BIT5) >> 5;
 793
 794                         if (dimmInfo->suportedEarlyRasPreCharge == 1)
 795                                 debug(" - Early Ras Precharge:                  Yes \n");
 796                         else
 797                                 debug(" -  Early Ras Precharge:                 No \n");
 798
 799                         if (dimmInfo->suportedAutoPreCharge == 1)
 800                                 debug(" - AutoPreCharge:                                Yes \n");
 801                         else
 802                                 debug(" -  AutoPreCharge:                               No \n");
 803
 804                         if (dimmInfo->suportedPreChargeAll == 1)
 805                                 debug(" - Precharge All:                                Yes \n");
 806                         else
 807                                 debug(" -  Precharge All:                               No \n");
 808
 809                         if (dimmInfo->suportedWrite1ReadBurst == 1)
 810                                 debug(" - Write 1/ReadBurst:                            Yes \n");
 811                         else
 812                                 debug(" -  Write 1/ReadBurst:                           No \n");
 813
 814                         if (dimmInfo->suported5PercentLowVCC == 1)
 815                                 debug(" - lower VCC tolerance:                  5 Percent \n");
 816                         else
 817                                 debug(" - lower VCC tolerance:                  10 Percent \n");
 818
 819                         if (dimmInfo->suported5PercentUpperVCC == 1)
 820                                 debug(" - upper VCC tolerance:                  5 Percent \n");
 821                         else
 822                                 debug(" -  upper VCC tolerance:                 10 Percent \n");
 823
 824                         break;
 825 /*------------------------------------------------------------------------------------------------------------------------------*/
 826
 827                 case 23:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
 828                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 829                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 830                         maskLeftOfPoint =
 831                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 832                         maskRightOfPoint =
 833                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 834                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 835                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 836                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
 837                                 leftOfPoint;
 838                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
 839                                 rightOfPoint;
 840                         debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 841                              leftOfPoint, rightOfPoint);
 842                         /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 843                         break;
 844 /*------------------------------------------------------------------------------------------------------------------------------*/
 845
 846                 case 24:        /* Clock To Data Out 2nd highest Cas Latency Value */
 847                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 848                         time_tmp =
 849                                 (((data[i] & 0xf0) >> 4) * 10) +
 850                                 ((data[i] & 0x0f));
 851                         leftOfPoint = time_tmp / div;
 852                         rightOfPoint = time_tmp % div;
 853                         dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
 854                         dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
 855                         debug("Clock To Data Out (2nd CL value):                %d.%2d [ns]\n",
 856                              leftOfPoint, rightOfPoint);
 857                         break;
 858 /*------------------------------------------------------------------------------------------------------------------------------*/
 859
 860                 case 25:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
 861                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 862                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 863                         maskLeftOfPoint =
 864                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 865                         maskRightOfPoint =
 866                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 867                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 868                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 869                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
 870                                 leftOfPoint;
 871                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
 872                                 rightOfPoint;
 873                         debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 874                              leftOfPoint, rightOfPoint);
 875                         /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 876                         break;
 877 /*------------------------------------------------------------------------------------------------------------------------------*/
 878
 879                 case 26:        /* Clock To Data Out 3rd highest Cas Latency Value */
 880                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 881                         time_tmp =
 882                                 (((data[i] & 0xf0) >> 4) * 10) +
 883                                 ((data[i] & 0x0f));
 884                         leftOfPoint = time_tmp / div;
 885                         rightOfPoint = time_tmp % div;
 886                         dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
 887                         dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
 888                         debug("Clock To Data Out (3rd CL value):                %d.%2d [ns]\n",
 889                              leftOfPoint, rightOfPoint);
 890                         break;
 891 /*------------------------------------------------------------------------------------------------------------------------------*/
 892
 893                 case 27:        /* Minimum Row Precharge Time */
 894                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 895                         maskLeftOfPoint =
 896                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 897                         maskRightOfPoint =
 898                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 899                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 900                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 901
 902                         dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);   /* measured in n times 10ps Intervals */
 903                         trp_clocks =
 904                                 (dimmInfo->minRowPrechargeTime +
 905                                  (tmemclk - 1)) / tmemclk;
 906                         debug("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
 907                              tmemclk, tmemclk / 100, tmemclk % 100);
 908                         debug("Minimum Row Precharge Time [ns]:         %d.%2d = in Clk cycles %d\n",
 909                              leftOfPoint, rightOfPoint, trp_clocks);
 910                         break;
 911 /*------------------------------------------------------------------------------------------------------------------------------*/
 912
 913                 case 28:        /* Minimum Row Active to Row Active Time */
 914                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 915                         maskLeftOfPoint =
 916                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 917                         maskRightOfPoint =
 918                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 919                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 920                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 921
 922                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
 923                         debug("Minimum Row Active -To- Row Active Delay [ns]:   %d.%2d = in Clk cycles %d\n",
 924                              leftOfPoint, rightOfPoint, trp_clocks);
 925                         break;
 926 /*------------------------------------------------------------------------------------------------------------------------------*/
 927
 928                 case 29:        /* Minimum Ras-To-Cas Delay */
 929                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 930                         maskLeftOfPoint =
 931                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 932                         maskRightOfPoint =
 933                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 934                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 935                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 936
 937                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
 938                         debug("Minimum Ras-To-Cas Delay [ns]:                   %d.%2d = in Clk cycles %d\n",
 939                              leftOfPoint, rightOfPoint, trp_clocks);
 940                         break;
 941 /*------------------------------------------------------------------------------------------------------------------------------*/
 942
 943                 case 30:        /* Minimum Ras Pulse Width */
 944                         dimmInfo->minRasPulseWidth = data[i];
 945                         tras_clocks =
 946                                 (NSto10PS (data[i]) +
 947                                  (tmemclk - 1)) / tmemclk;
 948                         debug("Minimum Ras Pulse Width [ns]:                    %d = in Clk cycles %d\n",
 949                              dimmInfo->minRasPulseWidth, tras_clocks);
 950
 951                         break;
 952 /*------------------------------------------------------------------------------------------------------------------------------*/
 953
 954                 case 31:        /* Module Bank Density */
 955                         dimmInfo->moduleBankDensity = data[i];
 956                         debug("Module Bank Density:                             %d\n",
 957                              dimmInfo->moduleBankDensity);
 958 #ifdef DEBUG
 959                         debug("*** Offered Densities (more than 1 = Multisize-Module): ");
 960                         {
 961                                 if (dimmInfo->moduleBankDensity & 1)
 962                                         debug("4MB, ");
 963                                 if (dimmInfo->moduleBankDensity & 2)
 964                                         debug("8MB, ");
 965                                 if (dimmInfo->moduleBankDensity & 4)
 966                                         debug("16MB, ");
 967                                 if (dimmInfo->moduleBankDensity & 8)
 968                                         debug("32MB, ");
 969                                 if (dimmInfo->moduleBankDensity & 16)
 970                                         debug("64MB, ");
 971                                 if (dimmInfo->moduleBankDensity & 32)
 972                                         debug("128MB, ");
 973                                 if ((dimmInfo->moduleBankDensity & 64)
 974                                     || (dimmInfo->moduleBankDensity & 128)) {
 975                                         debug("ERROR, ");
 976                                         hang ();
 977                                 }
 978                         }
 979                         debug("\n");
 980 #endif
 981                         break;
 982 /*------------------------------------------------------------------------------------------------------------------------------*/
 983
 984                 case 32:        /* Address And Command Setup Time (measured in ns/1000) */
 985                         sign = 1;
 986                         switch (dimmInfo->memoryType) {
 987                         case DDR:
 988                                 time_tmp =
 989                                         (((data[i] & 0xf0) >> 4) * 10) +
 990                                         ((data[i] & 0x0f));
 991                                 leftOfPoint = time_tmp / 100;
 992                                 rightOfPoint = time_tmp % 100;
 993                                 break;
 994                         case SDRAM:
 995                                 leftOfPoint = (data[i] & 0xf0) >> 4;
 996                                 if (leftOfPoint > 7) {
 997                                         leftOfPoint = data[i] & 0x70 >> 4;
 998                                         sign = -1;
 999                                 }
1000                                 rightOfPoint = (data[i] & 0x0f);
1001                                 break;
1002                         }
1003                         dimmInfo->addrAndCommandSetupTime =
1004                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1005                         debug("Address And Command Setup Time [ns]:             %d.%d\n",
1006                              sign * leftOfPoint, rightOfPoint);
1007                         break;
1008 /*------------------------------------------------------------------------------------------------------------------------------*/
1009
1010                 case 33:        /* Address And Command Hold Time */
1011                         sign = 1;
1012                         switch (dimmInfo->memoryType) {
1013                         case DDR:
1014                                 time_tmp =
1015                                         (((data[i] & 0xf0) >> 4) * 10) +
1016                                         ((data[i] & 0x0f));
1017                                 leftOfPoint = time_tmp / 100;
1018                                 rightOfPoint = time_tmp % 100;
1019                                 break;
1020                         case SDRAM:
1021                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1022                                 if (leftOfPoint > 7) {
1023                                         leftOfPoint = data[i] & 0x70 >> 4;
1024                                         sign = -1;
1025                                 }
1026                                 rightOfPoint = (data[i] & 0x0f);
1027                                 break;
1028                         }
1029                         dimmInfo->addrAndCommandHoldTime =
1030                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1031                         debug("Address And Command Hold Time [ns]:              %d.%d\n",
1032                              sign * leftOfPoint, rightOfPoint);
1033                         break;
1034 /*------------------------------------------------------------------------------------------------------------------------------*/
1035
1036                 case 34:        /* Data Input Setup Time */
1037                         sign = 1;
1038                         switch (dimmInfo->memoryType) {
1039                         case DDR:
1040                                 time_tmp =
1041                                         (((data[i] & 0xf0) >> 4) * 10) +
1042                                         ((data[i] & 0x0f));
1043                                 leftOfPoint = time_tmp / 100;
1044                                 rightOfPoint = time_tmp % 100;
1045                                 break;
1046                         case SDRAM:
1047                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1048                                 if (leftOfPoint > 7) {
1049                                         leftOfPoint = data[i] & 0x70 >> 4;
1050                                         sign = -1;
1051                                 }
1052                                 rightOfPoint = (data[i] & 0x0f);
1053                                 break;
1054                         }
1055                         dimmInfo->dataInputSetupTime =
1056                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1057                         debug("Data Input Setup Time [ns]:                      %d.%d\n",
1058                              sign * leftOfPoint, rightOfPoint);
1059                         break;
1060 /*------------------------------------------------------------------------------------------------------------------------------*/
1061
1062                 case 35:        /* Data Input Hold Time */
1063                         sign = 1;
1064                         switch (dimmInfo->memoryType) {
1065                         case DDR:
1066                                 time_tmp =
1067                                         (((data[i] & 0xf0) >> 4) * 10) +
1068                                         ((data[i] & 0x0f));
1069                                 leftOfPoint = time_tmp / 100;
1070                                 rightOfPoint = time_tmp % 100;
1071                                 break;
1072                         case SDRAM:
1073                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1074                                 if (leftOfPoint > 7) {
1075                                         leftOfPoint = data[i] & 0x70 >> 4;
1076                                         sign = -1;
1077                                 }
1078                                 rightOfPoint = (data[i] & 0x0f);
1079                                 break;
1080                         }
1081                         dimmInfo->dataInputHoldTime =
1082                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1083                         debug("Data Input Hold Time [ns]:                       %d.%d\n\n",
1084                              sign * leftOfPoint, rightOfPoint);
1085                         break;
1086 /*------------------------------------------------------------------------------------------------------------------------------*/
1087                 }
1088         }
1089         /* calculating the sdram density */
1090         for (i = 0;
1091              i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1092              i++) {
1093                 density = density * 2;
1094         }
1095         dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1096                 dimmInfo->sdramWidth;
1097         dimmInfo->numberOfDevices =
1098                 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1099                 dimmInfo->numOfModuleBanks;
1100         devicesForErrCheck =
1101                 (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1102         if ((dimmInfo->errorCheckType == 0x1)
1103             || (dimmInfo->errorCheckType == 0x2)
1104             || (dimmInfo->errorCheckType == 0x3)) {
1105                 dimmInfo->size =
1106                         (dimmInfo->deviceDensity / 8) *
1107                         (dimmInfo->numberOfDevices - devicesForErrCheck);
1108         } else {
1109                 dimmInfo->size =
1110                         (dimmInfo->deviceDensity / 8) *
1111                         dimmInfo->numberOfDevices;
1112         }
1113
1114         /* compute the module DRB size */
1115         tmp = (1 <<
1116                (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1117         tmp *= dimmInfo->numOfModuleBanks;
1118         tmp *= dimmInfo->sdramWidth;
1119         tmp = tmp >> 24;        /* div by 0x4000000 (64M)       */
1120         dimmInfo->drb_size = (uchar) tmp;
1121         debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
1122
1123         /* try a CAS latency of 3 first... */
1124
1125         /* bit 1 is CL2, bit 2 is CL3 */
1126         supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1127
1128         cal_val = 0;
1129         if (supp_cal & 8) {
1130                 if (NS10to10PS (data[9]) <= tmemclk)
1131                         cal_val = 6;
1132         }
1133         if (supp_cal & 4) {
1134                 if (NS10to10PS (data[9]) <= tmemclk)
1135                         cal_val = 5;
1136         }
1137
1138         /* then 2... */
1139         if (supp_cal & 2) {
1140                 if (NS10to10PS (data[23]) <= tmemclk)
1141                         cal_val = 4;
1142         }
1143
1144         debug("cal_val = %d\n", cal_val * 5);
1145
1146         /* bummer, did't work... */
1147         if (cal_val == 0) {
1148                 debug("Couldn't find a good CAS latency\n");
1149                 hang ();
1150                 return 0;
1151         }
1152
1153         return true;
1154 }
1155
1156 /* sets up the GT properly with information passed in */
1157 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1158 {
1159         ulong tmp;
1160         ulong tmp_sdram_mode = 0;       /* 0x141c */
1161         ulong tmp_dunit_control_low = 0;        /* 0x1404 */
1162         uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
1163         int i;
1164
1165         /* sanity checking */
1166         if (!info->numOfModuleBanks) {
1167                 printf ("setup_sdram called with 0 banks\n");
1168                 return 1;
1169         }
1170
1171         /* delay line */
1172
1173         /* Program the GT with the discovered data */
1174         if (info->registeredAddrAndControlInputs == true)
1175                 debug("Module is registered, but we do not support registered Modules !!!\n");
1176
1177         /* delay line */
1178         set_dfcdlInit ();       /* may be its not needed */
1179         debug("Delay line set done\n");
1180
1181         /* set SDRAM mode NOP */ /* To_do check it */
1182         GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1183         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1184                 debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
1185         }
1186
1187 #ifdef CONFIG_MV64360_ECC
1188         if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
1189                 /* DRAM has ECC, so turn it on */
1190                 sdram_config_reg |= BIT18;
1191                 debug("Enabling ECC\n");
1192         }
1193 #endif /* of ifdef CONFIG_MV64360_ECC */
1194
1195         /* SDRAM configuration */
1196         GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
1197         debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
1198
1199         /* SDRAM open pages controll keep open as much as I can */
1200         GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1201         debug("sdram_open_pages_controll 0x1414: %08x\n",
1202              GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
1203
1204
1205         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1206         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1207         if (tmp == 0)
1208                 debug("Core Signals are sync (by HW-Setting)!!!\n");
1209         else
1210                 debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
1211
1212         /* SDRAM set CAS Lentency according to SPD information */
1213         switch (info->memoryType) {
1214         case SDRAM:
1215                 debug("### SD-RAM not supported yet !!!\n");
1216                 hang ();
1217                 /* ToDo fill SD-RAM if needed !!!!! */
1218                 break;
1219
1220         case DDR:
1221                 debug("### SET-CL for DDR-RAM\n");
1222
1223                 switch (info->maxClSupported_DDR) {
1224                 case DDR_CL_3:
1225                         tmp_dunit_control_low = 0x3c000000;     /* Read-Data sampled on falling edge of Clk */
1226                         tmp_sdram_mode = 0x32;  /* CL=3 Burstlength = 4 */
1227                         debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1228                              tmp_sdram_mode, tmp_dunit_control_low);
1229                         break;
1230
1231                 case DDR_CL_2_5:
1232                         if (tmp == 1) { /* clocks sync */
1233                                 tmp_dunit_control_low = 0x24000000;     /* Read-Data sampled on falling edge of Clk */
1234                                 tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1235                                 debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1236                                      tmp_sdram_mode, tmp_dunit_control_low);
1237                         } else {        /* clk sync. bypassed     */
1238
1239                                 tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1240                                 tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1241                                 debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1242                                      tmp_sdram_mode, tmp_dunit_control_low);
1243                         }
1244                         break;
1245
1246                 case DDR_CL_2:
1247                         if (tmp == 1) { /* Sync */
1248                                 tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1249                                 tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1250                                 debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1251                                      tmp_sdram_mode, tmp_dunit_control_low);
1252                         } else {        /* Not sync.      */
1253
1254                                 tmp_dunit_control_low = 0x3b000000;     /* Read-Data sampled on rising edge of Clk */
1255                                 tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1256                                 debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1257                                      tmp_sdram_mode, tmp_dunit_control_low);
1258                         }
1259                         break;
1260
1261                 case DDR_CL_1_5:
1262                         if (tmp == 1) { /* Sync */
1263                                 tmp_dunit_control_low = 0x23000000;     /* Read-Data sampled on falling edge of Clk */
1264                                 tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1265                                 debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1266                                      tmp_sdram_mode, tmp_dunit_control_low);
1267                         } else {        /* not sync */
1268
1269                                 tmp_dunit_control_low = 0x1a000000;     /* Read-Data sampled on rising edge of Clk */
1270                                 tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1271                                 debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1272                                      tmp_sdram_mode, tmp_dunit_control_low);
1273                         }
1274                         break;
1275
1276                 default:
1277                         printf ("Max. CL is out of range %d\n",
1278                                 info->maxClSupported_DDR);
1279                         hang ();
1280                         break;
1281                 }
1282                 break;
1283         }
1284
1285         /* Write results of CL detection procedure */
1286         GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1287         /* set SDRAM mode SetCommand 0x1418 */
1288         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1289         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1290                 debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1291         }
1292
1293
1294         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1295         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1296         if (tmp != 1) {         /*clocks are not sync */
1297                 /* asyncmode */
1298                 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1299                               (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1300                               0x18110780 | tmp_dunit_control_low);
1301         } else {
1302                 /* syncmode */
1303                 GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1304                               (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1305                               0x00110000 | tmp_dunit_control_low);
1306         }
1307
1308         /* set SDRAM mode SetCommand 0x1418 */
1309         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1310         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1311                 debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
1312         }
1313
1314 /*------------------------------------------------------------------------------ */
1315
1316
1317         /* bank parameters */
1318         /* SDRAM address decode register */
1319         /* program this with the default value */
1320         tmp = 0x02;
1321
1322
1323         debug("drb_size (n*64Mbit): %d\n", info->drb_size);
1324         switch (info->drb_size) {
1325         case 1:         /* 64 Mbit */
1326         case 2:         /* 128 Mbit */
1327                 debug("RAM-Device_size 64Mbit or 128Mbit)\n");
1328                 tmp |= (0x00 << 4);
1329                 break;
1330         case 4:         /* 256 Mbit */
1331         case 8:         /* 512 Mbit */
1332                 debug("RAM-Device_size 256Mbit or 512Mbit)\n");
1333                 tmp |= (0x01 << 4);
1334                 break;
1335         case 16:                /* 1 Gbit */
1336         case 32:                /* 2 Gbit */
1337                 debug("RAM-Device_size 1Gbit or 2Gbit)\n");
1338                 tmp |= (0x02 << 4);
1339                 break;
1340         default:
1341                 printf ("Error in dram size calculation\n");
1342                 debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
1343                 tmp |= (0x02 << 4);
1344                 return 1;
1345         }
1346
1347         /* SDRAM bank parameters */
1348         /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1349         debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
1350         GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1351
1352 /* ------------------------------------------------------------------------------ */
1353
1354         debug("setting up sdram_timing_control_low with: %08x \n",
1355              0x11511220);
1356         GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1357
1358
1359 /* ------------------------------------------------------------------------------ */
1360
1361         /* SDRAM configuration */
1362         tmp = GTREGREAD (SDRAM_CONFIG);
1363
1364         if (info->registeredAddrAndControlInputs
1365             || info->registeredDQMBinputs) {
1366                 tmp |= (1 << 17);
1367                 debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1368                      info->registeredAddrAndControlInputs,
1369                      info->registeredDQMBinputs);
1370         }
1371
1372         /* Use buffer 1 to return read data to the CPU
1373          * Page 426 MV64360 */
1374         tmp |= (1 << 26);
1375         debug("Before Buffer assignment - sdram_conf: %08x\n",
1376              GTREGREAD (SDRAM_CONFIG));
1377         debug("After Buffer assignment - sdram_conf: %08x\n",
1378              GTREGREAD (SDRAM_CONFIG));
1379
1380         /* SDRAM timing To_do: */
1381
1382
1383         tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1384         debug("# sdram_timing_control_high is : %08lx \n", tmp);
1385
1386         /* SDRAM address decode register */
1387         /* program this with the default value */
1388         tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1389         debug("SDRAM address control (before: decode): %08x  ",
1390              GTREGREAD (SDRAM_ADDR_CONTROL));
1391         GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1392         debug("SDRAM address control (after: decode): %08x\n",
1393              GTREGREAD (SDRAM_ADDR_CONTROL));
1394
1395         /* set the SDRAM configuration for each bank */
1396
1397 /*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1398         {
1399                 int l, l1;
1400
1401                 i = info->slot;
1402                 debug("\n*** Running a MRS cycle for bank %d ***\n", i);
1403
1404                 /* map the bank */
1405                 memory_map_bank (i, 0, GB / 4);
1406 #if 1                           /* test only */
1407
1408                 tmp = GTREGREAD (SDRAM_MODE);
1409                 GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
1410                 GT_REG_WRITE (SDRAM_OPERATION, 0x4);
1411                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1412                         debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1413                 }
1414
1415                 GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
1416                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1417                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1418                         debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1419                 }
1420                 l1 = 0;
1421                 for (l=0;l<200;l++)
1422                         l1 += GTREGREAD (SDRAM_OPERATION);
1423
1424                 GT_REG_WRITE (SDRAM_MODE, tmp);
1425                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1426                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1427                         debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1428                 }
1429
1430                 /* switch back to normal operation mode */
1431                 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1432                 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1433                         debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1434                 }
1435
1436 #endif /* test only */
1437                 /* unmap the bank */
1438                 memory_map_bank (i, 0, 0);
1439         }
1440
1441         return 0;
1442 }
1443
1444 /*
1445  * Check memory range for valid RAM. A simple memory test determines
1446  * the actually available RAM size between addresses `base' and
1447  * `base + maxsize'. Some (not all) hardware errors are detected:
1448  * - short between address lines
1449  * - short between data lines
1450  */
1451 long int
1452 dram_size(long int *base, long int maxsize)
1453 {
1454     volatile long int    *addr, *b=base;
1455     long int     cnt, val, save1, save2;
1456
1457 #define STARTVAL (1<<20)        /* start test at 1M */
1458     for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1459             addr = base + cnt;  /* pointer arith! */
1460
1461             save1 = *addr;              /* save contents of addr */
1462             save2 = *b;         /* save contents of base */
1463
1464             *addr=cnt;          /* write cnt to addr */
1465             *b=0;                       /* put null at base */
1466
1467             /* check at base address */
1468             if ((*b) != 0) {
1469                 *addr=save1;    /* restore *addr */
1470                 *b=save2;       /* restore *b */
1471                 return (0);
1472             }
1473             val = *addr;                /* read *addr */
1474             val = *addr;                /* read *addr */
1475
1476             *addr=save1;
1477             *b=save2;
1478
1479             if (val != cnt) {
1480                     debug("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
1481                     /* fix boundary condition.. STARTVAL means zero */
1482                     if(cnt==STARTVAL/sizeof(long)) cnt=0;
1483                     return (cnt * sizeof(long));
1484             }
1485     }
1486     return maxsize;
1487 }
1488
1489 #ifdef CONFIG_MV64360_ECC
1490 /*
1491  * mv_dma_is_channel_active:
1492  * Checks if a engine is busy.
1493  */
1494 int mv_dma_is_channel_active(int engine)
1495 {
1496         ulong data;
1497
1498         data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
1499         if (data & BIT14)       /* activity status */
1500                 return 1;
1501
1502         return 0;
1503 }
1504
1505 /*
1506  * mv_dma_set_memory_space:
1507  * Set a DMA memory window for the DMA's address decoding map.
1508  */
1509 int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
1510                             ulong mem_space_attr, ulong base_address,
1511                             ulong size)
1512 {
1513         ulong temp;
1514
1515         /* The base address must be aligned to the size.  */
1516         if (base_address % size != 0)
1517                 return 0;
1518
1519         if (size >= 0x10000) {
1520                 size &= 0xffff0000;
1521                 base_address = (base_address & 0xffff0000);
1522                 /* Set the new attributes */
1523                 GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
1524                              (base_address | mem_space_target |
1525                               mem_space_attr));
1526                 GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
1527                              (size - 1) & 0xffff0000);
1528                 temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
1529                 GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
1530                              (temp & ~(BIT0 << mem_space)));
1531                 return 1;
1532         }
1533
1534         return 0;
1535 }
1536
1537
1538 /*
1539  * mv_dma_transfer:
1540  * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
1541  */
1542 int mv_dma_transfer(int engine, ulong source_addr,
1543                     ulong dest_addr, ulong bytes, ulong command)
1544 {
1545         ulong eng_off_reg;      /* Engine Offset Register */
1546
1547         if (bytes > 0xffff)
1548                 command = command | BIT31;       /* DMA_16M_DESCRIPTOR_MODE */
1549
1550         command = command | ((command >> 6) & 0x7);
1551         eng_off_reg = engine * 4;
1552         GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
1553                      bytes);
1554         GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
1555                      source_addr);
1556         GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
1557                      dest_addr);
1558         command |= BIT12        /* DMA_CHANNEL_ENABLE */
1559                 | BIT9;         /* DMA_NON_CHAIN_MODE */
1560
1561         /* Activate DMA engine By writting to mv_dma_control_register */
1562         GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
1563
1564         return 1;
1565 }
1566 #endif /* of ifdef CONFIG_MV64360_ECC */
1567
1568 /* ppcboot interface function to SDRAM init - this is where all the
1569  * controlling logic happens */
1570 phys_size_t
1571 initdram(int board_type)
1572 {
1573         int checkbank[4] = { [0 ... 3] = 0 };
1574         ulong realsize, total, check;
1575         AUX_MEM_DIMM_INFO dimmInfo1;
1576         AUX_MEM_DIMM_INFO dimmInfo2;
1577         int bank_no, nhr;
1578 #ifdef CONFIG_MV64360_ECC
1579         ulong dest, mem_space_attr;
1580 #endif /* of ifdef CONFIG_MV64360_ECC */
1581
1582         /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1583
1584         /* check the NHR bit and skip mem init if it's already done */
1585         nhr = get_hid0() & (1 << 16);
1586
1587         if (nhr) {
1588                 printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1589         } else {
1590                 /* DIMM0 */
1591                 (void)check_dimm(0, &dimmInfo1);
1592
1593                 /* DIMM1 */
1594                 (void)check_dimm(1, &dimmInfo2);
1595
1596                 memory_map_bank(0, 0, 0);
1597                 memory_map_bank(1, 0, 0);
1598                 memory_map_bank(2, 0, 0);
1599                 memory_map_bank(3, 0, 0);
1600
1601                 if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1602                         printf("Setup for DIMM1 failed.\n");
1603                 }
1604
1605                 if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1606                         printf("Setup for DIMM2 failed.\n");
1607                 }
1608
1609                 /* set the NHR bit */
1610                 set_hid0(get_hid0() | (1 << 16));
1611         }
1612         /* next, size the SDRAM banks */
1613
1614         realsize = total = 0;
1615         check = GB/4;
1616         if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1617         if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1618         if (dimmInfo1.numOfModuleBanks > 2)
1619                 printf("Error, SPD claims DIMM1 has >2 banks\n");
1620
1621         if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1622         if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1623         if (dimmInfo2.numOfModuleBanks > 2)
1624                 printf("Error, SPD claims DIMM2 has >2 banks\n");
1625
1626         for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1627                 /* skip over banks that are not populated */
1628                 if (! checkbank[bank_no])
1629                         continue;
1630
1631                 if ((total + check) > CONFIG_SYS_GT_REGS)
1632                         check = CONFIG_SYS_GT_REGS - total;
1633
1634                 memory_map_bank(bank_no, total, check);
1635                 realsize = dram_size((long int *)total, check);
1636                 memory_map_bank(bank_no, total, realsize);
1637
1638 #ifdef CONFIG_MV64360_ECC
1639                 if (((dimmInfo1.errorCheckType != 0) &&
1640                      ((dimmInfo2.errorCheckType != 0) ||
1641                       (dimmInfo2.numOfModuleBanks == 0))) &&
1642                     (CPCI750_ECC_TEST)) {
1643                         printf("ECC Initialization of Bank %d:", bank_no);
1644                         mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1645                         mv_dma_set_memory_space(0, 0, mem_space_attr, total,
1646                                                 realsize);
1647                         for (dest = total; dest < total + realsize;
1648                              dest += _8M) {
1649                                 mv_dma_transfer(0, total, dest, _8M,
1650                                                 BIT8 |  /* DMA_DTL_128BYTES */
1651                                                 BIT3 |  /* DMA_HOLD_SOURCE_ADDR */
1652                                                 BIT11); /* DMA_BLOCK_TRANSFER_MODE */
1653                                 while (mv_dma_is_channel_active(0))
1654                                         ;
1655                         }
1656                         printf(" PASS\n");
1657                 }
1658 #endif /* of ifdef CONFIG_MV64360_ECC */
1659
1660                 total += realsize;
1661         }
1662
1663 /*      Setup Ethernet DMA Adress window to DRAM Area */
1664         return(total);
1665 }
1666
1667 /* ***************************************************************************************
1668 ! *                             SDRAM INIT                                              *
1669 ! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb       *
1670 ! *               This procedure fits only the Atlantis                                *
1671 ! *                                                                                     *
1672 ! *************************************************************************************** */
1673
1674
1675 /* ***************************************************************************************
1676 ! *                             DFCDL initialize MV643xx Design Considerations             *
1677 ! *                                                                                     *
1678 ! *************************************************************************************** */
1679 int set_dfcdlInit (void)
1680 {
1681         int i;
1682         unsigned int dfcdl_word = 0x0000014f;
1683
1684         for (i = 0; i < 64; i++) {
1685                 GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1686         }
1687         GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);       /* enable dynamic delay line updating */
1688
1689
1690         return (0);
1691 }
1692
1693 int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1694 {
1695         unsigned int ecc_counter;
1696         unsigned int ecc_addr;
1697
1698         GT_REG_READ(0x1458, &ecc_counter);
1699         GT_REG_READ(0x1450, &ecc_addr);
1700         GT_REG_WRITE(0x1450, 0);
1701
1702         printf("Error Counter since Reset:  %8d\n", ecc_counter);
1703         printf("Last error address       :0x%08x (" , ecc_addr & 0xfffffff8);
1704         if (ecc_addr & 0x01)
1705                 printf("double");
1706         else
1707                 printf("single");
1708         printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
1709
1710         return 0;
1711 }
1712
1713
1714 U_BOOT_CMD(
1715         show_ecc, 1, 1, do_show_ecc,
1716         "Show Marvell MV64360 ECC Info",
1717         "Show Marvell MV64360 ECC Counter and last error."
1718 );