board/esd/pmc440/pmc440.c

   1 /*
   2  * (Cg) Copyright 2007-2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4  * Based on board/amcc/sequoia/sequoia.c
   5  *
   6  * (C) Copyright 2006
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2006
  10  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15 #include <common.h>
  16 #include <libfdt.h>
  17 #include <fdt_support.h>
  18 #include <asm/ppc440.h>
  19 #include <asm/processor.h>
  20 #include <asm/io.h>
  21 #include <asm/bitops.h>
  22 #include <command.h>
  23 #include <i2c.h>
  24 #ifdef CONFIG_RESET_PHY_R
  25 #include <miiphy.h>
  26 #endif
  27 #include <serial.h>
  28 #include <asm/4xx_pci.h>
  29 #include <usb.h>
  30
  31 #include "fpga.h"
  32 #include "pmc440.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  37 extern void __ft_board_setup(void *blob, bd_t *bd);
  38
  39 ulong flash_get_size(ulong base, int banknum);
  40 static int pci_is_66mhz(void);
  41 int is_monarch(void);
  42 static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
  43                                  uchar *buffer, unsigned cnt);
  44
  45 struct serial_device *default_serial_console(void)
  46 {
  47         uchar buf[4];
  48         ulong delay;
  49         int i;
  50         ulong val;
  51
  52         /*
  53          * Use default console on P4 when strapping jumper
  54          * is installed (bootstrap option != 'H').
  55          */
  56         mfsdr(SDR0_PINSTP, val);
  57         if (((val & 0xf0000000) >> 29) != 7)
  58                 return &eserial2_device;
  59
  60         ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
  61         if (!(scratchreg & 0x80)) {
  62                 /* mark scratchreg valid */
  63                 scratchreg = (scratchreg & 0xffffff00) | 0x80;
  64
  65                 i2c_init_all();
  66
  67                 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
  68                                           0x10, buf, 4);
  69                 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
  70                         scratchreg |= buf[2];
  71
  72                         /* bringup delay for console */
  73                         for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
  74                                 udelay(1000);
  75                 } else
  76                         scratchreg |= 0x01;
  77                 out_be32((void *)GPIO0_ISR3L, scratchreg);
  78         }
  79
  80         if (scratchreg & 0x01)
  81                 return &eserial2_device;
  82         else
  83                 return &eserial1_device;
  84 }
  85
  86 int board_early_init_f(void)
  87 {
  88         u32 sdr0_cust0;
  89         u32 sdr0_pfc1, sdr0_pfc2;
  90         u32 reg;
  91
  92         /* general EBC configuration (disable EBC timeouts) */
  93         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  94         mtdcr(EBC0_CFGDATA, 0xf8400000);
  95
  96         /* Setup the GPIO pins */
  97         out_be32((void *)GPIO0_OR,    0x40000102);
  98         out_be32((void *)GPIO0_TCR,   0x4c90011f);
  99         out_be32((void *)GPIO0_OSRL,  0x28051400);
 100         out_be32((void *)GPIO0_OSRH,  0x55005000);
 101         out_be32((void *)GPIO0_TSRL,  0x08051400);
 102         out_be32((void *)GPIO0_TSRH,  0x55005000);
 103         out_be32((void *)GPIO0_ISR1L, 0x54000000);
 104         out_be32((void *)GPIO0_ISR1H, 0x00000000);
 105         out_be32((void *)GPIO0_ISR2L, 0x44000000);
 106         out_be32((void *)GPIO0_ISR2H, 0x00000100);
 107         out_be32((void *)GPIO0_ISR3L, 0x00000000);
 108         out_be32((void *)GPIO0_ISR3H, 0x00000000);
 109
 110         out_be32((void *)GPIO1_OR,    0x80002408);
 111         out_be32((void *)GPIO1_TCR,   0xd6003c08);
 112         out_be32((void *)GPIO1_OSRL,  0x0a5a0000);
 113         out_be32((void *)GPIO1_OSRH,  0x00000000);
 114         out_be32((void *)GPIO1_TSRL,  0x00000000);
 115         out_be32((void *)GPIO1_TSRH,  0x00000000);
 116         out_be32((void *)GPIO1_ISR1L, 0x00005555);
 117         out_be32((void *)GPIO1_ISR1H, 0x40000000);
 118         out_be32((void *)GPIO1_ISR2L, 0x04010000);
 119         out_be32((void *)GPIO1_ISR2H, 0x00000000);
 120         out_be32((void *)GPIO1_ISR3L, 0x01400000);
 121         out_be32((void *)GPIO1_ISR3H, 0x00000000);
 122
 123         /* patch PLB:PCI divider for 66MHz PCI */
 124         mfcpr(CPR0_SPCID, reg);
 125         if (pci_is_66mhz() && (reg != 0x02000000)) {
 126                 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
 127
 128                 mfcpr(CPR0_ICFG, reg);
 129                 reg |= CPR0_ICFG_RLI_MASK;
 130                 mtcpr(CPR0_ICFG, reg);
 131
 132                 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
 133         }
 134
 135         /*
 136          * Setup the interrupt controller polarities, triggers, etc.
 137          */
 138         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 139         mtdcr(UIC0ER, 0x00000000);      /* disable all */
 140         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
 141         mtdcr(UIC0PR, 0xfffff7ef);
 142         mtdcr(UIC0TR, 0x00000000);
 143         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
 144         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 145
 146         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 147         mtdcr(UIC1ER, 0x00000000);      /* disable all */
 148         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
 149         mtdcr(UIC1PR, 0xffffc7f5);
 150         mtdcr(UIC1TR, 0x00000000);
 151         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
 152         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 153
 154         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 155         mtdcr(UIC2ER, 0x00000000);      /* disable all */
 156         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
 157         mtdcr(UIC2PR, 0x27ffffff);
 158         mtdcr(UIC2TR, 0x00000000);
 159         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
 160         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 161
 162         /* select Ethernet pins */
 163         mfsdr(SDR0_PFC1, sdr0_pfc1);
 164         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 165                 SDR0_PFC1_SELECT_CONFIG_4;
 166         mfsdr(SDR0_PFC2, sdr0_pfc2);
 167         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 168                 SDR0_PFC2_SELECT_CONFIG_4;
 169
 170         /* enable 2nd IIC */
 171         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
 172
 173         mtsdr(SDR0_PFC2, sdr0_pfc2);
 174         mtsdr(SDR0_PFC1, sdr0_pfc1);
 175
 176         /* setup NAND FLASH */
 177         mfsdr(SDR0_CUST0, sdr0_cust0);
 178         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 179                 SDR0_CUST0_NDFC_ENABLE          |
 180                 SDR0_CUST0_NDFC_BW_8_BIT        |
 181                 SDR0_CUST0_NDFC_ARE_MASK        |
 182                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 183         mtsdr(SDR0_CUST0, sdr0_cust0);
 184
 185         return 0;
 186 }
 187
 188 #if defined(CONFIG_MISC_INIT_F)
 189 int misc_init_f(void)
 190 {
 191         struct pci_controller hose;
 192         hose.first_busno = 0;
 193         hose.last_busno = 0;
 194         hose.region_count = 0;
 195
 196         if (getenv("pciearly") && (!is_monarch())) {
 197                 printf("PCI:   early target init\n");
 198                 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
 199                 pci_target_init(&hose);
 200         }
 201         return 0;
 202 }
 203 #endif
 204
 205 /*
 206  * misc_init_r.
 207  */
 208 int misc_init_r(void)
 209 {
 210         uint pbcr;
 211         int size_val = 0;
 212         u32 reg;
 213         unsigned long usb2d0cr = 0;
 214         unsigned long usb2phy0cr, usb2h0cr = 0;
 215         unsigned long sdr0_pfc1;
 216         unsigned long sdr0_srst0, sdr0_srst1;
 217         char *act = getenv("usbact");
 218
 219         /*
 220          * FLASH stuff...
 221          */
 222
 223         /* Re-do sizing to get full correct info */
 224
 225         /* adjust flash start and offset */
 226         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 227         gd->bd->bi_flashoffset = 0;
 228
 229         mtdcr(EBC0_CFGADDR, PB0CR);
 230         pbcr = mfdcr(EBC0_CFGDATA);
 231         size_val = ffs(gd->bd->bi_flashsize) - 21;
 232         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 233         mtdcr(EBC0_CFGADDR, PB0CR);
 234         mtdcr(EBC0_CFGDATA, pbcr);
 235
 236         /*
 237          * Re-check to get correct base address
 238          */
 239         flash_get_size(gd->bd->bi_flashstart, 0);
 240
 241 #ifdef CONFIG_ENV_IS_IN_FLASH
 242         /* Monitor protection ON by default */
 243         (void)flash_protect(FLAG_PROTECT_SET,
 244                             -CONFIG_SYS_MONITOR_LEN,
 245                             0xffffffff,
 246                             &flash_info[0]);
 247
 248         /* Env protection ON by default */
 249         (void)flash_protect(FLAG_PROTECT_SET,
 250                             CONFIG_ENV_ADDR_REDUND,
 251                             CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 252                             &flash_info[0]);
 253 #endif
 254
 255         /*
 256          * USB suff...
 257          */
 258         if ((act == NULL || strcmp(act, "host") == 0) &&
 259             !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 260                 /* SDR Setting */
 261                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 262                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 263                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 264                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 265
 266                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 267                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 268                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 269                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 270                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 271                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 272                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 273                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 274                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 275                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 276
 277                 /*
 278                  * An 8-bit/60MHz interface is the only possible alternative
 279                  * when connecting the Device to the PHY
 280                  */
 281                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 282                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 283
 284                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 285                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 286
 287                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 288                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 289                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 290                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 291
 292                 /*
 293                  * Take USB out of reset:
 294                  * -Initial status = all cores are in reset
 295                  * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
 296                  * -wait 1 ms
 297                  * -deassert reset to PHY
 298                  * -wait 1 ms
 299                  * -deassert  reset to HOST
 300                  * -wait 4 ms
 301                  * -deassert all other resets
 302                  */
 303                 mfsdr(SDR0_SRST1, sdr0_srst1);
 304                 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |      \
 305                                 SDR0_SRST1_P4OPB0 |     \
 306                                 SDR0_SRST1_OPBA2 |      \
 307                                 SDR0_SRST1_PLB42OPB1 |  \
 308                                 SDR0_SRST1_OPB2PLB40);
 309                 mtsdr(SDR0_SRST1, sdr0_srst1);
 310                 udelay(1000);
 311
 312                 mfsdr(SDR0_SRST1, sdr0_srst1);
 313                 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
 314                 mtsdr(SDR0_SRST1, sdr0_srst1);
 315                 udelay(1000);
 316
 317                 mfsdr(SDR0_SRST0, sdr0_srst0);
 318                 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
 319                 mtsdr(SDR0_SRST0, sdr0_srst0);
 320                 udelay(4000);
 321
 322                 /* finally all the other resets */
 323                 mtsdr(SDR0_SRST1, 0x00000000);
 324                 mtsdr(SDR0_SRST0, 0x00000000);
 325
 326                 if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 327                         /* enable power on USB socket */
 328                         out_be32((void *)GPIO1_OR,
 329                                  in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 330                 }
 331
 332                 printf("USB:   Host\n");
 333
 334         } else if ((strcmp(act, "dev") == 0) ||
 335                    (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 336                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 337
 338                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 339                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 340                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 341                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 342                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 343                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 344                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 345                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 346                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 347
 348                 udelay (1000);
 349                 mtsdr(SDR0_SRST1, 0x672c6000);
 350
 351                 udelay (1000);
 352                 mtsdr(SDR0_SRST0, 0x00000080);
 353
 354                 udelay (1000);
 355                 mtsdr(SDR0_SRST1, 0x60206000);
 356
 357                 *(unsigned int *)(0xe0000350) = 0x00000001;
 358
 359                 udelay (1000);
 360                 mtsdr(SDR0_SRST1, 0x60306000);
 361
 362                 /* SDR Setting */
 363                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 364                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 365                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 366                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 367
 368                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 369                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 370                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 371                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 372                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 373                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 374                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 375                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 376                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 377                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 378
 379                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 380                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 381
 382                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 383
 384                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 385                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 386
 387                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 388                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 389                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 390                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 391
 392                 /*clear resets*/
 393                 udelay(1000);
 394                 mtsdr(SDR0_SRST1, 0x00000000);
 395                 udelay(1000);
 396                 mtsdr(SDR0_SRST0, 0x00000000);
 397
 398                 printf("USB:   Device\n");
 399         }
 400
 401         /*
 402          * Clear PLB4A0_ACR[WRP]
 403          * This fix will make the MAL burst disabling patch for the Linux
 404          * EMAC driver obsolete.
 405          */
 406         reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
 407         mtdcr(PLB4A0_ACR, reg);
 408
 409 #ifdef CONFIG_FPGA
 410         pmc440_init_fpga();
 411 #endif
 412
 413         /* turn off POST LED */
 414         out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
 415         /* turn on RUN LED */
 416         out_be32((void *)GPIO0_OR,
 417                  in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
 418         return 0;
 419 }
 420
 421 int is_monarch(void)
 422 {
 423         if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
 424                 return 0;
 425
 426         return 1;
 427 }
 428
 429 static int pci_is_66mhz(void)
 430 {
 431         if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
 432                 return 1;
 433         return 0;
 434 }
 435
 436 static int board_revision(void)
 437 {
 438         return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
 439 }
 440
 441 int checkboard(void)
 442 {
 443         puts("Board: esd GmbH - PMC440");
 444
 445         gd->board_type = board_revision();
 446         printf(", Rev 1.%ld, ", gd->board_type);
 447
 448         if (!is_monarch()) {
 449                 puts("non-");
 450         }
 451
 452         printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
 453         return (0);
 454 }
 455
 456
 457 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 458 /*
 459  * Assign interrupts to PCI devices. Some OSs rely on this.
 460  */
 461 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 462 {
 463         unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
 464
 465         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 466                                    int_line[PCI_DEV(dev) & 0x03]);
 467 }
 468 #endif
 469
 470 /*
 471  * pci_target_init
 472  *
 473  * The bootstrap configuration provides default settings for the pci
 474  * inbound map (PIM). But the bootstrap config choices are limited and
 475  * may not be sufficient for a given board.
 476  */
 477 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 478 void pci_target_init(struct pci_controller *hose)
 479 {
 480         char *ptmla_str, *ptmms_str;
 481
 482         /*
 483          * Set up Direct MMIO registers
 484          */
 485         /*
 486          * PowerPC440EPX PCI Master configuration.
 487          * Map one 1Gig range of PLB/processor addresses to PCI memory space.
 488          * PLB address 0x80000000-0xBFFFFFFF
 489          *     ==> PCI address 0x80000000-0xBFFFFFFF
 490          * Use byte reversed out routines to handle endianess.
 491          * Make this region non-prefetchable.
 492          */
 493         out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
 494                                                 /* - disabled b4 setting */
 495         out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
 496         out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
 497         out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 498         out32r(PCIL0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
 499                                                 /* and enable region */
 500
 501         if (!is_monarch()) {
 502                 ptmla_str = getenv("ptm1la");
 503                 ptmms_str = getenv("ptm1ms");
 504                 if(NULL != ptmla_str && NULL != ptmms_str ) {
 505                         out32r(PCIL0_PTM1MS,
 506                                simple_strtoul(ptmms_str, NULL, 16));
 507                         out32r(PCIL0_PTM1LA,
 508                                simple_strtoul(ptmla_str, NULL, 16));
 509                 } else {
 510                         /* BAR1: default top 64MB of RAM */
 511                         out32r(PCIL0_PTM1MS, 0xfc000001);
 512                         out32r(PCIL0_PTM1LA, 0x0c000000);
 513                 }
 514         } else {
 515                 /* BAR1: default: complete 256MB RAM */
 516                 out32r(PCIL0_PTM1MS, 0xf0000001);
 517                 out32r(PCIL0_PTM1LA, 0x00000000);
 518         }
 519
 520         ptmla_str = getenv("ptm2la");           /* Local Addr. Reg */
 521         ptmms_str = getenv("ptm2ms");           /* Memory Size/Attribute */
 522         if(NULL != ptmla_str && NULL != ptmms_str ) {
 523                 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
 524                 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
 525         } else {
 526                 /* BAR2: default: 4MB FPGA */
 527                 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
 528                 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
 529         }
 530
 531         if (is_monarch()) {
 532                 /* BAR2: map FPGA registers behind system memory at 1GB */
 533                 pci_hose_write_config_dword(hose, 0,
 534                                             PCI_BASE_ADDRESS_2, 0x40000008);
 535         }
 536
 537         /*
 538          * Set up Configuration registers
 539          */
 540
 541         /* Program the board's vendor id */
 542         pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
 543                                    CONFIG_SYS_PCI_SUBSYS_VENDORID);
 544
 545         /* disabled for PMC405 backward compatibility */
 546         /* Configure command register as bus master */
 547         /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
 548
 549
 550         /* 240nS PCI clock */
 551         pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
 552
 553         /* No error reporting */
 554         pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
 555
 556         if (!is_monarch()) {
 557                 /* Program the board's subsystem id/classcode */
 558                 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
 559                                            CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
 560                 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
 561                                            CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
 562
 563                 /* PCI configuration done: release ERREADY */
 564                 out_be32((void *)GPIO1_OR,
 565                          in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
 566                 out_be32((void *)GPIO1_TCR,
 567                          in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
 568         } else {
 569                 /* Program the board's subsystem id/classcode */
 570                 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
 571                                            CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
 572                 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
 573                                            CONFIG_SYS_PCI_CLASSCODE_MONARCH);
 574         }
 575
 576         /* enable host configuration */
 577         pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
 578 }
 579 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 580
 581 /*
 582  * Override weak default pci_master_init()
 583  */
 584 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 585 void pci_master_init(struct pci_controller *hose)
 586 {
 587         /*
 588          * Only configure the master in monach mode
 589          */
 590         if (is_monarch())
 591                 __pci_master_init(hose);
 592 }
 593 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 594
 595 static void wait_for_pci_ready(void)
 596 {
 597         if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
 598                 printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
 599                 while (1) {
 600                         if (ctrlc()) {
 601                                 puts("abort\n");
 602                                 break;
 603                         }
 604                         if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
 605                                 printf("done\n");
 606                                 break;
 607                         }
 608                 }
 609         }
 610 }
 611
 612 /*
 613  * Override weak is_pci_host()
 614  *
 615  * This routine is called to determine if a pci scan should be
 616  * performed. With various hardware environments (especially cPCI and
 617  * PPMC) it's insufficient to depend on the state of the arbiter enable
 618  * bit in the strap register, or generic host/adapter assumptions.
 619  *
 620  * Rather than hard-code a bad assumption in the general 440 code, the
 621  * 440 pci code requires the board to decide at runtime.
 622  *
 623  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 624  */
 625 #if defined(CONFIG_PCI)
 626 int is_pci_host(struct pci_controller *hose)
 627 {
 628         char *s = getenv("pciscan");
 629         if (s == NULL)
 630                 if (is_monarch()) {
 631                         wait_for_pci_ready();
 632                         return 1;
 633                 } else
 634                         return 0;
 635         else if (!strcmp(s, "yes"))
 636                 return 1;
 637
 638         return 0;
 639 }
 640 #endif /* defined(CONFIG_PCI) */
 641
 642 #ifdef CONFIG_RESET_PHY_R
 643 static int pmc440_setup_vsc8601(char *devname, int phy_addr,
 644                                 unsigned short behavior, unsigned short method)
 645 {
 646         /* adjust LED behavior */
 647         if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
 648                 printf("Phy%d: register write access failed\n", phy_addr);
 649                 return -1;
 650         }
 651
 652         miiphy_write(devname, phy_addr, 0x11, 0x0010);
 653         miiphy_write(devname, phy_addr, 0x11, behavior);
 654         miiphy_write(devname, phy_addr, 0x10, method);
 655         miiphy_write(devname, phy_addr, 0x1f, 0x0000);
 656
 657         return 0;
 658 }
 659
 660 static int pmc440_setup_ksz9031(char *devname, int phy_addr)
 661 {
 662         unsigned short id1, id2;
 663
 664         if (miiphy_read(devname, phy_addr, 2, &id1) ||
 665             miiphy_read(devname, phy_addr, 3, &id2)) {
 666                 printf("Phy%d: cannot read id\n", phy_addr);
 667                 return -1;
 668         }
 669
 670         if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
 671                 printf("Phy%d: unexpected id\n", phy_addr);
 672                 return -1;
 673         }
 674
 675         /* MMD 2.08: adjust tx_clk pad skew */
 676         miiphy_write(devname, phy_addr, 0x0d, 2);
 677         miiphy_write(devname, phy_addr, 0x0e, 8);
 678         miiphy_write(devname, phy_addr, 0x0d, 0x4002);
 679         miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
 680
 681         return 0;
 682 }
 683
 684 void reset_phy(void)
 685 {
 686         char *s;
 687         unsigned short val_method, val_behavior;
 688
 689         if (gd->board_type < 4) {
 690                 /* special LED setup for NGCC/CANDES */
 691                 s = getenv("bd_type");
 692                 if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
 693                         val_method   = 0x0e0a;
 694                         val_behavior = 0x0cf2;
 695                 } else {
 696                         /* PMC440 standard type */
 697                         val_method   = 0x0e10;
 698                         val_behavior = 0x0cf0;
 699                 }
 700
 701                 /* boards up to rev. 1.3 use Vitesse VSC8601 phys */
 702                 pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
 703                                      val_method, val_behavior);
 704                 pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
 705                                      val_method, val_behavior);
 706         } else {
 707                 /* rev. 1.4 uses a Micrel KSZ9031 */
 708                 pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 709                 pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
 710         }
 711 }
 712 #endif
 713
 714 #if defined(CONFIG_SYS_EEPROM_WREN)
 715 /*
 716  *  Input: <dev_addr> I2C address of EEPROM device to enable.
 717  *         <state>    -1: deliver current state
 718  *                     0: disable write
 719  *                     1: enable write
 720  *  Returns:          -1: wrong device address
 721  *                     0: dis-/en- able done
 722  *                   0/1: current state if <state> was -1.
 723  */
 724 int eeprom_write_enable(unsigned dev_addr, int state)
 725 {
 726         if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
 727             (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
 728                 return -1;
 729         } else {
 730                 switch (state) {
 731                 case 1:
 732                         /* Enable write access, clear bit GPIO_SINT2. */
 733                         out_be32((void *)GPIO0_OR,
 734                               in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
 735                         state = 0;
 736                         break;
 737                 case 0:
 738                         /* Disable write access, set bit GPIO_SINT2. */
 739                         out_be32((void *)GPIO0_OR,
 740                                  in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
 741                         state = 0;
 742                         break;
 743                 default:
 744                         /* Read current status back. */
 745                         state = (0 == (in_be32((void *)GPIO0_OR)
 746                                        & GPIO0_EP_EEP));
 747                         break;
 748                 }
 749         }
 750         return state;
 751 }
 752 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 753
 754 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
 755 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
 756                            uchar *buffer, unsigned cnt)
 757 {
 758         unsigned end = offset + cnt;
 759         unsigned blk_off;
 760         int rcode = 0;
 761
 762 #if defined(CONFIG_SYS_EEPROM_WREN)
 763         eeprom_write_enable(dev_addr, 1);
 764 #endif
 765         /*
 766          * Write data until done or would cross a write page boundary.
 767          * We must write the address again when changing pages
 768          * because the address counter only increments within a page.
 769          */
 770         while (offset < end) {
 771                 unsigned alen, len;
 772                 unsigned maxlen;
 773                 uchar addr[2];
 774
 775                 blk_off = offset & 0xFF;        /* block offset */
 776
 777                 addr[0] = offset >> 8;          /* block number */
 778                 addr[1] = blk_off;              /* block offset */
 779                 alen    = 2;
 780                 addr[0] |= dev_addr;            /* insert device address */
 781
 782                 len = end - offset;
 783
 784 #define BOOT_EEPROM_PAGE_SIZE      (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
 785 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
 786
 787                 maxlen = BOOT_EEPROM_PAGE_SIZE -
 788                         BOOT_EEPROM_PAGE_OFFSET(blk_off);
 789                 if (maxlen > I2C_RXTX_LEN)
 790                         maxlen = I2C_RXTX_LEN;
 791
 792                 if (len > maxlen)
 793                         len = maxlen;
 794
 795                 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
 796                         rcode = 1;
 797
 798                 buffer += len;
 799                 offset += len;
 800
 801 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
 802                 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 803 #endif
 804         }
 805 #if defined(CONFIG_SYS_EEPROM_WREN)
 806         eeprom_write_enable(dev_addr, 0);
 807 #endif
 808         return rcode;
 809 }
 810
 811 static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
 812                                  uchar *buffer, unsigned cnt)
 813 {
 814         unsigned end = offset + cnt;
 815         unsigned blk_off;
 816         int rcode = 0;
 817
 818         /*
 819          * Read data until done or would cross a page boundary.
 820          * We must write the address again when changing pages
 821          * because the next page may be in a different device.
 822          */
 823         while (offset < end) {
 824                 unsigned alen, len;
 825                 unsigned maxlen;
 826                 uchar addr[2];
 827
 828                 blk_off = offset & 0xFF;        /* block offset */
 829
 830                 addr[0] = offset >> 8;          /* block number */
 831                 addr[1] = blk_off;              /* block offset */
 832                 alen    = 2;
 833
 834                 addr[0] |= dev_addr;            /* insert device address */
 835
 836                 len = end - offset;
 837
 838                 maxlen = 0x100 - blk_off;
 839                 if (maxlen > I2C_RXTX_LEN)
 840                         maxlen = I2C_RXTX_LEN;
 841                 if (len > maxlen)
 842                         len = maxlen;
 843
 844                 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
 845                         rcode = 1;
 846                 buffer += len;
 847                 offset += len;
 848         }
 849
 850         return rcode;
 851 }
 852
 853 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 854 int board_usb_init(int index, enum usb_init_type init)
 855 {
 856         char *act = getenv("usbact");
 857         int i;
 858
 859         if ((act == NULL || strcmp(act, "host") == 0) &&
 860             !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
 861                 /* enable power on USB socket */
 862                 out_be32((void *)GPIO1_OR,
 863                          in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 864
 865         for (i=0; i<1000; i++)
 866                 udelay(1000);
 867
 868         return 0;
 869 }
 870
 871 int usb_board_stop(void)
 872 {
 873         /* disable power on USB socket */
 874         out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
 875         return 0;
 876 }
 877
 878 int board_usb_cleanup(int index, enum usb_init_type init)
 879 {
 880         return usb_board_stop();
 881 }
 882 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
 883
 884 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 885 void ft_board_setup(void *blob, bd_t *bd)
 886 {
 887         int rc;
 888
 889         __ft_board_setup(blob, bd);
 890
 891         /*
 892          * Disable PCI in non-monarch mode.
 893          */
 894         if (!is_monarch()) {
 895                 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
 896                                           "disabled", sizeof("disabled"), 1);
 897                 if (rc) {
 898                         printf("Unable to update property status in PCI node, ");
 899                         printf("err=%s\n", fdt_strerror(rc));
 900                 }
 901         }
 902 }
 903 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */