board/eukrea/cpu9260/cpu9260.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * (C) Copyright 2009-2011
   8  * Eric Benard <eric@eukrea.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <asm/io.h>
  31 #include <asm/arch/at91sam9260.h>
  32 #include <asm/arch/at91sam9_smc.h>
  33 #include <asm/arch/at91_common.h>
  34 #include <asm/arch/at91_matrix.h>
  35 #include <asm/arch/at91_pmc.h>
  36 #include <asm/arch/at91_rstc.h>
  37 #include <asm/arch/at91_pio.h>
  38 #include <asm/arch/clk.h>
  39 #include <asm/arch/hardware.h>
  40 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  41 #include <net.h>
  42 #endif
  43 #include <netdev.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 /* ------------------------------------------------------------------------- */
  48 /*
  49  * Miscelaneous platform dependent initialisations
  50  */
  51
  52 #ifdef CONFIG_CMD_NAND
  53 static void cpu9260_nand_hw_init(void)
  54 {
  55         unsigned long csa;
  56         at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
  57         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  58         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  59
  60         /* Enable CS3 */
  61         csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
  62         writel(csa, &matrix->csa);
  63
  64         /* Configure SMC CS3 for NAND/SmartMedia */
  65 #if defined(CONFIG_CPU9G20)
  66         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  67                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  68                 &smc->cs[3].setup);
  69         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
  70                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  71                 &smc->cs[3].pulse);
  72         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  73                 &smc->cs[3].cycle);
  74         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  75                 AT91_SMC_MODE_EXNW_DISABLE |
  76                 AT91_SMC_MODE_DBW_8 |
  77                 AT91_SMC_MODE_TDF_CYCLE(3),
  78                 &smc->cs[3].mode);
  79 #elif defined(CONFIG_CPU9260)
  80         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  81                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  82                 &smc->cs[3].setup);
  83         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  84                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  85                 &smc->cs[3].pulse);
  86         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  87                 &smc->cs[3].cycle);
  88         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  89                 AT91_SMC_MODE_EXNW_DISABLE |
  90                 AT91_SMC_MODE_DBW_8 |
  91                 AT91_SMC_MODE_TDF_CYCLE(2),
  92                 &smc->cs[3].mode);
  93 #endif
  94
  95         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  96
  97         /* Configure RDY/BSY */
  98         at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  99
 100         /* Enable NandFlash */
 101         at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 102 }
 103 #endif
 104
 105 #ifdef CONFIG_MACB
 106 static void cpu9260_macb_hw_init(void)
 107 {
 108         unsigned long rstcmr;
 109         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 110         at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
 111
 112         /* Enable clock */
 113         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 114
 115         at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
 116
 117         rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 118
 119         /* Need to reset PHY -> 500ms reset */
 120         writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
 121                                 AT91_RSTC_MR_URSTEN, &rstc->mr);
 122
 123         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 124
 125         /* Wait for end hardware reset */
 126         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
 127                 ;
 128
 129         /* Restore NRST value */
 130         writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
 131
 132         at91_macb_hw_init();
 133 }
 134 #endif
 135
 136 int board_early_init_f(void)
 137 {
 138         at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 139
 140         writel((1 << ATMEL_ID_PIOA) |
 141                 (1 << ATMEL_ID_PIOB) |
 142                 (1 << ATMEL_ID_PIOC),
 143                 &pmc->pcer);
 144
 145         at91_seriald_hw_init();
 146
 147         return 0;
 148 }
 149
 150
 151 int board_init(void)
 152 {
 153         /* arch number of the board */
 154 #if defined(CONFIG_CPU9G20)
 155         gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
 156 #elif defined(CONFIG_CPU9260)
 157         gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
 158 #endif
 159
 160         /* adress of boot parameters */
 161         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 162
 163 #ifdef CONFIG_CMD_NAND
 164         cpu9260_nand_hw_init();
 165 #endif
 166 #ifdef CONFIG_MACB
 167         cpu9260_macb_hw_init();
 168 #endif
 169 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
 170         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
 171 #endif
 172         return 0;
 173 }
 174
 175 int dram_init(void)
 176 {
 177         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 178                         CONFIG_SYS_SDRAM_SIZE);
 179         return 0;
 180 }
 181
 182 int board_eth_init(bd_t *bis)
 183 {
 184         int rc = 0;
 185 #ifdef CONFIG_MACB
 186         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);
 187 #endif
 188         return rc;
 189 }