board/evb64260/eth.c

   1 /**************************************************************************
   2 Etherboot -  BOOTP/TFTP Bootstrap Program
   3 Skeleton NIC driver for Etherboot
   4 ***************************************************************************/
   5
   6 /*
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2, or (at
  10  * your option) any later version.
  11  */
  12
  13 /*
  14  * This file is a modified version from the Galileo polled mode
  15  * network driver for the ethernet contained within the GT64260
  16  * chip. It has been modified to fit into the U-Boot framework, from
  17  * the original (etherboot) setup.  Also, additional cleanup and features
  18  * were added.
  19  *
  20  * - Josh Huber <huber@mclx.com>
  21  */
  22
  23 #include <common.h>
  24 #include <malloc.h>
  25 #include <galileo/gt64260R.h>
  26 #include <galileo/core.h>
  27 #include <asm/cache.h>
  28 #include <miiphy.h>
  29 #include <net.h>
  30 #include <netdev.h>
  31
  32 #include "eth.h"
  33 #include "eth_addrtbl.h"
  34
  35 #if defined(CONFIG_CMD_NET)
  36
  37 #define GT6426x_ETH_BUF_SIZE    1536
  38
  39 /* if you like verbose output, turn this on! */
  40 #undef DEBUG
  41
  42 /* Restart autoneg if we detect link is up on phy init. */
  43
  44 /*
  45  * The GT doc's say that after Rst is deasserted, and the PHY
  46  * reports autoneg complete, it runs through its autoneg
  47  * procedures. This doesn't seem to be the case for MII
  48  * PHY's. To work around this check for link up && autoneg
  49  * complete when initilizing the port. If they are both set,
  50  * then restart PHY autoneg. Of course, it may be something
  51  * completly different.
  52  */
  53 #ifdef CONFIG_ETHER_PORT_MII
  54 # define RESTART_AUTONEG
  55 #endif
  56
  57 /* do this if you dont want to use snooping */
  58 #define USE_SOFTWARE_CACHE_MANAGEMENT
  59
  60 #ifdef USE_SOFTWARE_CACHE_MANAGEMENT
  61 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  62 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
  63 #define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
  64 #else
  65 /* bummer - w/o flush, nothing works, even with snooping - FIXME */
  66 /* #define FLUSH_DCACHE(a,b) */
  67 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  68 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
  69 #define INVALIDATE_DCACHE(a,b)
  70 #endif
  71 struct eth_dev_s {
  72         eth0_tx_desc_single *eth_tx_desc;
  73         eth0_rx_desc_single *eth_rx_desc;
  74         char *eth_tx_buffer;
  75         char *eth_rx_buffer[NR];
  76         int tdn, rdn;
  77         int dev;
  78         unsigned int reg_base;
  79 };
  80
  81
  82 #ifdef CONFIG_INTEL_LXT97X
  83 /* for intel LXT972 */
  84 static const char ether_port_phy_addr[3]={0,1,2};
  85 #else
  86 static const char ether_port_phy_addr[3]={4,5,6};
  87 #endif
  88
  89 /* MII PHY access routines are common for all i/f, use gal_ent0 */
  90 #define GT6426x_MII_DEVNAME     "gal_enet0"
  91
  92 int gt6426x_miiphy_read(const char *devname, unsigned char phy,
  93                 unsigned char reg, unsigned short *val);
  94
  95 static inline unsigned short
  96 miiphy_read_ret(unsigned short phy, unsigned short reg)
  97 {
  98     unsigned short val;
  99     gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
 100     return val;
 101 }
 102
 103
 104 /**************************************************************************
 105 RESET - Reset adapter
 106 ***************************************************************************/
 107 void
 108 gt6426x_eth_reset(void *v)
 109 {
 110         /*  we should do something here...
 111         struct eth_device *wp = (struct eth_device *)v;
 112         struct eth_dev_s *p = wp->priv;
 113         */
 114
 115         printf ("RESET\n");
 116         /* put the card in its initial state */
 117 }
 118
 119 static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
 120 {
 121 #ifdef DEBUG
 122     printf("SMI interrupt: ");
 123
 124     if(icr&0x20000000) {
 125         printf("SMI done\n");
 126     }
 127 #endif
 128
 129     if(icr&0x10000000) {
 130 #ifdef DEBUG
 131         unsigned int psr;
 132
 133         psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
 134         printf("PHY state change:\n"
 135                "  GT:%s:%s:%s:%s\n",
 136                 psr & 1 ? "100" : " 10",
 137                 psr & 8 ? " Link" : "nLink",
 138                 psr & 2 ? "FD" : "HD",
 139                 psr & 4 ? " FC" : "nFC");
 140
 141 #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
 142         {
 143                 unsigned short mii_11;
 144                 mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11);
 145
 146                 printf(" mii:%s:%s:%s:%s %s:%s %s\n",
 147                         mii_11 & (1 << 14) ? "100" : " 10",
 148                         mii_11 & (1 << 10) ? " Link" : "nLink",
 149                         mii_11 & (1 << 9) ? "FD" : "HD",
 150                         mii_11 & (1 << 4) ? " FC" : "nFC",
 151
 152                         mii_11 & (1 << 7) ? "ANc" : "ANnc",
 153                         mii_11 & (1 << 8) ? "AN" : "Manual",
 154                         ""
 155                         );
 156         }
 157 #endif /* CONFIG_INTEL_LXT97X */
 158 #endif /* DEBUG */
 159     }
 160 }
 161
 162 static int
 163 gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
 164 {
 165         int eth_len=0;
 166         char *eth_data;
 167
 168         eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
 169
 170         INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 171
 172         if (rx->command_status & 0x80000000) {
 173                 return 0; /* No packet received */
 174         }
 175
 176         eth_len = (unsigned int)
 177                 (rx->buff_size_byte_count) & 0x0000ffff;
 178         eth_data = (char *) p->eth_rx_buffer[p->rdn];
 179
 180 #ifdef DEBUG
 181         if (eth_len) {
 182                 printf ("%s: Recived %d byte Packet @ 0x%p\n",
 183                         __FUNCTION__, eth_len, eth_data);
 184         }
 185 #endif
 186         /*
 187          * packet is now in:
 188          * eth0_rx_buffer[RDN_ETH0];
 189          */
 190
 191         /* let the upper layer handle the packet */
 192         NetReceive ((uchar *)eth_data, eth_len);
 193
 194         rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 195
 196
 197         /* GT96100 Owner */
 198         rx->command_status = 0x80000000;
 199
 200         FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 201
 202         p->rdn ++;
 203         if (p->rdn == NR) {p->rdn = 0;}
 204
 205         sync();
 206
 207         /* Start Rx*/
 208         GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
 209
 210 #ifdef DEBUG
 211         {
 212             int i;
 213             for (i=0;i<12;i++) {
 214                 printf(" %02x", eth_data[i]);
 215             }
 216         }
 217         printf(": %d bytes\n", eth_len);
 218 #endif
 219         INVALIDATE_DCACHE((unsigned int)eth_data,
 220                 (unsigned int)eth_data+eth_len);
 221         return eth_len;
 222 }
 223
 224 /**************************************************************************
 225 POLL - look for an rx frame, handle other conditions
 226 ***************************************************************************/
 227 int
 228 gt6426x_eth_poll(void *v)
 229 {
 230         struct eth_device *wp = (struct eth_device *)v;
 231         struct eth_dev_s *p = wp->priv;
 232         unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
 233
 234         if(icr) {
 235             GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
 236 #ifdef DEBUG
 237             printf("poll got ICR %08x\n", icr);
 238 #endif
 239             /* SMI done or PHY state change*/
 240             if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
 241         }
 242         /* always process. We aren't using RX interrupts */
 243         return gt6426x_eth_receive(p, icr);
 244 }
 245
 246 /**************************************************************************
 247 TRANSMIT - Transmit a frame
 248 ***************************************************************************/
 249 int
 250 gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
 251 {
 252         struct eth_device *wp = (struct eth_device *)v;
 253         struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
 254 #ifdef DEBUG
 255         unsigned int old_command_stat,old_psr;
 256 #endif
 257         eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
 258
 259         /* wait for tx to be ready */
 260         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
 261         while (tx->command_status & 0x80000000) {
 262             int i;
 263             for(i=0;i<1000;i++);
 264                         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
 265         }
 266
 267         GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
 268                       (unsigned int)tx);
 269
 270 #ifdef DEBUG
 271         printf("copying to tx_buffer [%p], length %x, desc = %p\n",
 272                dev->eth_tx_buffer, s, dev->eth_tx_desc);
 273 #endif
 274         memcpy(dev->eth_tx_buffer, (char *) p, s);
 275
 276         tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
 277         tx->bytecount_reserved = ((__u16)s) << 16;
 278
 279         /*    31 - own
 280          *    22 - gencrc
 281          * 18:16 - pad, last, first */
 282         tx->command_status = (1<<31) | (1<<22) | (7<<16);
 283 #if 0
 284         /* FEr #18 */
 285         tx->next_desc = NULL;
 286 #else
 287         tx->next_desc =
 288                 (struct eth0_tx_desc_struct *)
 289                 &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
 290
 291         /* cpu owned */
 292         dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16);     /* pad, last, first */
 293 #endif
 294
 295 #ifdef DEBUG
 296         old_command_stat=tx->command_status,
 297         old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
 298 #endif
 299
 300         FLUSH_DCACHE((unsigned int)tx,
 301                 (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
 302
 303         FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
 304
 305         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
 306
 307 #ifdef DEBUG
 308         {
 309             unsigned int command_stat=0;
 310             printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
 311             /* wait for tx to be ready */
 312             do {
 313                 unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
 314                 command_stat=tx->command_status;
 315                 if(command_stat!=old_command_stat || psr !=old_psr) {
 316                     printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
 317                     old_command_stat = command_stat;
 318                     old_psr = psr;
 319                 }
 320                 /* gt6426x_eth0_poll(); */
 321             } while (command_stat & 0x80000000);
 322
 323             printf("sent %d byte frame\n", s);
 324
 325             if((command_stat & (3<<15)) == 3) {
 326                 printf("frame had error (stat=%08x)\n", command_stat);
 327             }
 328         }
 329 #endif
 330         return 0;
 331 }
 332
 333 /**************************************************************************
 334 DISABLE - Turn off ethernet interface
 335 ***************************************************************************/
 336 void
 337 gt6426x_eth_disable(void *v)
 338 {
 339         struct eth_device *wp = (struct eth_device *)v;
 340         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
 341
 342         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
 343 }
 344
 345 /**************************************************************************
 346 MII utilities - write: write to an MII register via SMI
 347 ***************************************************************************/
 348 int
 349 gt6426x_miiphy_write(const char *devname, unsigned char phy,
 350                 unsigned char reg, unsigned short data)
 351 {
 352     unsigned int temp= (reg<<21) | (phy<<16) | data;
 353
 354     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
 355
 356     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
 357     return 0;
 358 }
 359
 360 /**************************************************************************
 361 MII utilities - read: read from an MII register via SMI
 362 ***************************************************************************/
 363 int
 364 gt6426x_miiphy_read(const char *devname, unsigned char phy,
 365                 unsigned char reg, unsigned short *val)
 366 {
 367     unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
 368
 369     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
 370
 371     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
 372
 373     while(1) {
 374         temp=GTREGREAD(ETHERNET_SMI_REGISTER);
 375         if(temp & (1<<27)) break;               /* wait for ReadValid */
 376     }
 377     *val = temp & 0xffff;
 378
 379     return 0;
 380 }
 381
 382 #ifdef DEBUG
 383 /**************************************************************************
 384 MII utilities - dump mii registers
 385 ***************************************************************************/
 386 static void
 387 gt6426x_dump_mii(bd_t *bis, unsigned short phy)
 388 {
 389         printf("mii reg 0 - 3:   %04x %04x %04x %04x\n",
 390                 miiphy_read_ret(phy, 0x0),
 391                 miiphy_read_ret(phy, 0x1),
 392                 miiphy_read_ret(phy, 0x2),
 393                 miiphy_read_ret(phy, 0x3)
 394                 );
 395         printf("        4 - 7:   %04x %04x %04x %04x\n",
 396                 miiphy_read_ret(phy, 0x4),
 397                 miiphy_read_ret(phy, 0x5),
 398                 miiphy_read_ret(phy, 0x6),
 399                 miiphy_read_ret(phy, 0x7)
 400                 );
 401         printf("        8:       %04x\n",
 402                 miiphy_read_ret(phy, 0x8)
 403                 );
 404         printf("        16-19:   %04x %04x %04x %04x\n",
 405                 miiphy_read_ret(phy, 0x10),
 406                 miiphy_read_ret(phy, 0x11),
 407                 miiphy_read_ret(phy, 0x12),
 408                 miiphy_read_ret(phy, 0x13)
 409                 );
 410         printf("        20,30:   %04x %04x\n",
 411                 miiphy_read_ret(phy, 20),
 412                 miiphy_read_ret(phy, 30)
 413                 );
 414 }
 415 #endif
 416
 417 #ifdef RESTART_AUTONEG
 418
 419 /* If link is up && autoneg compleate, and if
 420  * GT and PHY disagree about link capabilitys,
 421  * restart autoneg - something screwy with FD/HD
 422  * unless we do this. */
 423 static void
 424 check_phy_state(struct eth_dev_s *p)
 425 {
 426         int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR);
 427         int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
 428
 429         if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) {
 430                 int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) &
 431                                 miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA);
 432                 int want;
 433
 434                 if (nego & LPA_100FULL) {
 435                         want = 0x3;
 436                         printf("MII: 100Base-TX, Full Duplex\n");
 437                 } else if (nego & LPA_100HALF) {
 438                         want = 0x1;
 439                         printf("MII: 100Base-TX, Half Duplex\n");
 440                 } else if (nego & LPA_10FULL) {
 441                         want = 0x2;
 442                         printf("MII: 10Base-T, Full Duplex\n");
 443                 } else if (nego & LPA_10HALF) {
 444                         want = 0x0;
 445                         printf("MII: 10Base-T, Half Duplex\n");
 446                 } else {
 447                         printf("MII: Unknown link-foo! %x\n", nego);
 448                         return;
 449                 }
 450
 451                 if ((psr & 0x3) != want) {
 452                         printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
 453                                         psr & 0x3, want);
 454                         miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
 455                                         miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
 456                         udelay(10000);  /* the EVB's GT takes a while to notice phy
 457                                            went down and up */
 458                 }
 459         }
 460 }
 461 #endif
 462
 463 /**************************************************************************
 464 PROBE - Look for an adapter, this routine's visible to the outside
 465 ***************************************************************************/
 466 int
 467 gt6426x_eth_probe(void *v, bd_t *bis)
 468 {
 469         struct eth_device *wp = (struct eth_device *)v;
 470         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
 471         int dev = p->dev;
 472         unsigned int reg_base = p->reg_base;
 473         unsigned long temp;
 474         int i;
 475
 476         if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
 477         {       /* This should never happen */
 478                 printf("%s: Invalid device %d\n", __FUNCTION__, dev );
 479                 return 0;
 480         }
 481
 482 #ifdef DEBUG
 483         printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
 484         printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
 485                 GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
 486                 GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
 487 #endif
 488
 489         /* clear MIB counters */
 490         for(i=0;i<255; i++)
 491             temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
 492
 493 #ifdef CONFIG_INTEL_LXT97X
 494         /* for intel LXT972 */
 495
 496         /* led 1: 0x1=txact
 497            led 2: 0xc=link/rxact
 498            led 3: 0x2=rxact (N/C)
 499            strch: 0,2=30 ms, enable */
 500         miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
 501
 502         /* 2.7ns port rise time */
 503         /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
 504 #else
 505         /* already set up in mpsc.c */
 506         /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38);        /  b400 */
 507
 508         /* already set up in sdram_init.S... */
 509         /* MPSC0, MPSC1, RMII */
 510         /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102);          /  f010 */
 511 #endif
 512         GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
 513              ether_port_phy_addr[0]     |
 514             (ether_port_phy_addr[1]<<5) |
 515             (ether_port_phy_addr[2]<<10));                      /* 2000 */
 516
 517         /* 13:12 -   10: 4x64bit burst  (cache line size = 32 bytes)
 518          *    9  -    1: RIFB - interrupt on frame boundaries only
 519          *  6:7  -   00: big endian rx and tx
 520          *  5:2  - 1111: 15 retries */
 521         GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
 522                 (2<<12) | (1<<9) | (0xf<<2) );                  /* 2440 */
 523
 524 #ifndef USE_SOFTWARE_CACHE_MANAGEMENT
 525         /* enable rx/tx desc/buffer cache snoop */
 526         GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
 527                 &temp);                                         /* f200 */
 528         temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
 529         GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
 530                 temp);
 531 #endif
 532
 533         /* 31  28 27  24 23  20 19  16
 534          *  0000   0000   0000   0000   [0004]
 535          * 15  12 11  8   7  4   3  0
 536          *  1000   1101   0000   0000   [4d00]
 537          *    20 - 0=MII 1=RMII
 538          *    19 - 0=speed autoneg
 539          * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
 540          *    11 - no force link pass
 541          *    10 - 1=disable fctl autoneg
 542          *     8 - override prio ?? */
 543         temp = 0x00004d00;
 544 #ifndef CONFIG_ETHER_PORT_MII
 545         temp |= (1<<20);        /* RMII */
 546 #endif
 547         /* set En */
 548         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
 549                      temp);                             /* 2408 */
 550
 551         /* hardcode E1 also? */
 552         /* -- according to dox, this is safer due to extra pulldowns? */
 553         if (dev<2) {
 554         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
 555                      temp);                             /* 2408 */
 556         }
 557
 558         /* wake up MAC */                                /* 2400 */
 559         GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
 560         temp |= (1<<7);         /* enable port */
 561 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 562         temp |= (1<<12);        /* hash size 1/2k */
 563 #else
 564         temp |= 1;              /* promisc */
 565 #endif
 566         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
 567                                                         /* 2400 */
 568
 569 #ifdef RESTART_AUTONEG
 570         check_phy_state(p);
 571 #endif
 572
 573         printf("%s: Waiting for link up..\n", wp->name);
 574         temp = 10 * 1000;
 575         /* wait for link back up */
 576         while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
 577                         && (--temp > 0)){
 578             udelay(1000);       /* wait 1 ms */
 579         }
 580         if ( temp == 0) {
 581                 printf("%s: Failed!\n", wp->name);
 582                 return (0);
 583         }
 584
 585         printf("%s: OK!\n", wp->name);
 586
 587         p->tdn = 0;
 588         p->rdn = 0;
 589         p->eth_tx_desc[p->tdn].command_status = 0;
 590
 591         /* Initialize Rx Side */
 592         for (temp = 0; temp < NR; temp++) {
 593                 p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
 594                 p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 595
 596                 /* GT96100 Owner */
 597                 p->eth_rx_desc[temp].command_status = 0x80000000;
 598                 p->eth_rx_desc[temp].next_desc =
 599                         (struct eth0_rx_desc_struct *)
 600                         &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
 601         }
 602
 603         FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
 604                      (unsigned int)&p->eth_tx_desc[NR]);
 605         FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
 606                      (unsigned int)&p->eth_rx_desc[NR]);
 607
 608         GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
 609                       (unsigned int) p->eth_tx_desc);
 610         GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
 611                       (unsigned int) p->eth_rx_desc);
 612         GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
 613                       (unsigned int) p->eth_rx_desc);
 614
 615 #ifdef DEBUG
 616         printf ("\nRx descriptor pointer is %08x %08x\n",
 617                 GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
 618                 GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
 619         printf ("\n\n%08x %08x\n",
 620                 (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
 621
 622         printf ("Descriptor dump:\n");
 623         printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
 624         printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
 625         printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
 626         printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
 627         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
 628         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
 629         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
 630         printf ("%08x\n\n",
 631                 *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
 632 #endif
 633
 634 #ifdef DEBUG
 635         gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
 636 #endif
 637
 638 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 639         {
 640                 unsigned int hashtable_base;
 641             u8 *b = (u8 *)(wp->enetaddr);
 642                 u32 macH, macL;
 643
 644                 /* twist the MAC up into the way the discovery wants it */
 645                 macH= (b[0]<<8) | b[1];
 646             macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
 647
 648             /* mode 0, size 0x800 */
 649             hashtable_base =initAddressTable(dev,0,1);
 650
 651             if(!hashtable_base) {
 652                         printf("initAddressTable failed\n");
 653                         return 0;
 654             }
 655
 656             addAddressTableEntry(dev, macH, macL, 1, 0);
 657             GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
 658                     hashtable_base);
 659         }
 660 #endif
 661
 662         /* Start Rx*/
 663         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
 664         printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
 665         return 1;
 666 }
 667
 668 /* enter all the galileo ethernet devs into MULTI-BOOT */
 669 void
 670 gt6426x_eth_initialize(bd_t *bis)
 671 {
 672         struct eth_device *dev;
 673         struct eth_dev_s *p;
 674         int devnum, x, temp;
 675         char *s, *e, buf[64];
 676
 677 #ifdef DEBUG
 678         printf( "\n%s\n", __FUNCTION );
 679 #endif
 680
 681         for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
 682                 dev = calloc(sizeof(*dev), 1);
 683                 if (!dev) {
 684                         printf( "%s: gal_enet%d allocation failure, %s\n",
 685                                         __FUNCTION__, devnum, "eth_device structure");
 686                         return;
 687                 }
 688
 689                 /* must be less than NAMESIZE (16) */
 690                 sprintf(dev->name, "gal_enet%d", devnum);
 691
 692 #ifdef DEBUG
 693                 printf( "Initializing %s\n", dev->name );
 694 #endif
 695
 696                 /* Extract the MAC address from the environment */
 697                 switch (devnum)
 698                 {
 699                         case 0: s = "ethaddr"; break;
 700 #if (GAL_ETH_DEVS > 1)
 701                         case 1: s = "eth1addr"; break;
 702 #endif
 703 #if (GAL_ETH_DEVS > 2)
 704                         case 2: s = "eth2addr"; break;
 705 #endif
 706                         default: /* this should never happen */
 707                                 printf( "%s: Invalid device number %d\n",
 708                                                 __FUNCTION__, devnum );
 709                                 return;
 710                 }
 711
 712                 temp = getenv_f(s, buf, sizeof(buf));
 713                 s = (temp > 0) ? buf : NULL;
 714
 715 #ifdef DEBUG
 716                 printf ("Setting MAC %d to %s\n", devnum, s );
 717 #endif
 718                 for (x = 0; x < 6; ++x) {
 719                         dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
 720                         if (s)
 721                                 s = (*e) ? e+1 : e;
 722                 }
 723
 724                 dev->init = (void*)gt6426x_eth_probe;
 725                 dev->halt = (void*)gt6426x_eth_reset;
 726                 dev->send = (void*)gt6426x_eth_transmit;
 727                 dev->recv = (void*)gt6426x_eth_poll;
 728
 729                 p = calloc( sizeof(*p), 1 );
 730                 dev->priv = (void*)p;
 731                 if (!p)
 732                 {
 733                         printf( "%s: %s allocation failure, %s\n",
 734                                         __FUNCTION__, dev->name, "Private Device Structure");
 735                         free(dev);
 736                         return;
 737                 }
 738
 739                 p->dev = devnum;
 740                 p->tdn=0;
 741                 p->rdn=0;
 742                 p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
 743
 744                 p->eth_tx_desc =
 745                         (eth0_tx_desc_single *)
 746                         (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
 747                                                 (NT+1)) & 0xfffffff0) + 0x10);
 748                 if (!p)
 749                 {
 750                         printf( "%s: %s allocation failure, %s\n",
 751                                         __FUNCTION__, dev->name, "Tx Descriptor");
 752                         free(dev);
 753                         return;
 754                 }
 755
 756                 p->eth_rx_desc =
 757                         (eth0_rx_desc_single *)
 758                         (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
 759                                                 (NR+1)) & 0xfffffff0) + 0x10);
 760                 if (!p->eth_rx_desc)
 761                 {
 762                         printf( "%s: %s allocation failure, %s\n",
 763                                         __FUNCTION__, dev->name, "Rx Descriptor");
 764                         free(dev);
 765                         free(p);
 766                         return;
 767                 }
 768
 769                 p->eth_tx_buffer =
 770                         (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
 771                 if (!p->eth_tx_buffer)
 772                 {
 773                         printf( "%s: %s allocation failure, %s\n",
 774                                         __FUNCTION__, dev->name, "Tx Bufffer");
 775                         free(dev);
 776                         free(p);
 777                         free(p->eth_rx_desc);
 778                         return;
 779                 }
 780
 781                 for (temp = 0 ; temp < NR ; temp ++) {
 782                         p->eth_rx_buffer[temp] =
 783                                 (char *)
 784                                 (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
 785                         if (!p->eth_rx_buffer[temp])
 786                         {
 787                                 printf( "%s: %s allocation failure, %s\n",
 788                                                 __FUNCTION__, dev->name, "Rx Buffers");
 789                                 free(dev);
 790                                 free(p);
 791                                 free(p->eth_tx_buffer);
 792                                 free(p->eth_rx_desc);
 793                                 free(p->eth_tx_desc);
 794                                 while (temp >= 0)
 795                                         free(p->eth_rx_buffer[--temp]);
 796                                 return;
 797                         }
 798                 }
 799
 800
 801                 eth_register(dev);
 802 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 803                 miiphy_register(dev->name,
 804                                 gt6426x_miiphy_read, gt6426x_miiphy_write);
 805 #endif
 806         }
 807
 808 }
 809 #endif