board/freescale/b4860qds/b4860qds.c

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/errno.h>
  15 #include <asm/cache.h>
  16 #include <asm/immap_85xx.h>
  17 #include <asm/fsl_law.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/fsl_portals.h>
  20 #include <asm/fsl_liodn.h>
  21 #include <fm_eth.h>
  22
  23 #include "../common/qixis.h"
  24 #include "../common/vsc3316_3308.h"
  25 #include "../common/idt8t49n222a_serdes_clk.h"
  26 #include "b4860qds.h"
  27 #include "b4860qds_qixis.h"
  28 #include "b4860qds_crossbar_con.h"
  29
  30 #define CLK_MUX_SEL_MASK        0x4
  31 #define ETH_PHY_CLK_OUT         0x4
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 int checkboard(void)
  36 {
  37         char buf[64];
  38         u8 sw;
  39         struct cpu_type *cpu = gd->arch.cpu;
  40         static const char *const freq[] = {"100", "125", "156.25", "161.13",
  41                                                 "122.88", "122.88", "122.88"};
  42         int clock;
  43
  44         printf("Board: %sQDS, ", cpu->name);
  45         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  46                 QIXIS_READ(id), QIXIS_READ(arch));
  47
  48         sw = QIXIS_READ(brdcfg[0]);
  49         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50
  51         if (sw < 0x8)
  52                 printf("vBank: %d\n", sw);
  53         else if (sw >= 0x8 && sw <= 0xE)
  54                 puts("NAND\n");
  55         else
  56                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  57
  58         printf("FPGA: v%d (%s), build %d",
  59                 (int)QIXIS_READ(scver), qixis_read_tag(buf),
  60                 (int)qixis_read_minor());
  61         /* the timestamp string contains "\n" at the end */
  62         printf(" on %s", qixis_read_time(buf));
  63
  64         /*
  65          * Display the actual SERDES reference clocks as configured by the
  66          * dip switches on the board.  Note that the SWx registers could
  67          * technically be set to force the reference clocks to match the
  68          * values that the SERDES expects (or vice versa).  For now, however,
  69          * we just display both values and hope the user notices when they
  70          * don't match.
  71          */
  72         puts("SERDES Reference Clocks: ");
  73         sw = QIXIS_READ(brdcfg[2]);
  74         clock = (sw >> 5) & 7;
  75         printf("Bank1=%sMHz ", freq[clock]);
  76         sw = QIXIS_READ(brdcfg[4]);
  77         clock = (sw >> 6) & 3;
  78         printf("Bank2=%sMHz\n", freq[clock]);
  79
  80         return 0;
  81 }
  82
  83 int select_i2c_ch_pca(u8 ch)
  84 {
  85         int ret;
  86
  87         /* Selecting proper channel via PCA*/
  88         ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
  89         if (ret) {
  90                 printf("PCA: failed to select proper channel.\n");
  91                 return ret;
  92         }
  93
  94         return 0;
  95 }
  96
  97 int configure_vsc3316_3308(void)
  98 {
  99         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 100         unsigned int num_vsc16_con, num_vsc08_con;
 101         u32 serdes1_prtcl, serdes2_prtcl;
 102         int ret;
 103
 104         serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 105                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 106         if (!serdes1_prtcl) {
 107                 printf("SERDES1 is not enabled\n");
 108                 return 0;
 109         }
 110         serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 111         debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
 112
 113         serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
 114                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 115         if (!serdes2_prtcl) {
 116                 printf("SERDES2 is not enabled\n");
 117                 return 0;
 118         }
 119         serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 120         debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
 121
 122         switch (serdes1_prtcl) {
 123         case 0x29:
 124         case 0x2a:
 125         case 0x2C:
 126         case 0x2D:
 127         case 0x2E:
 128                         /*
 129                          * Configuration:
 130                          * SERDES: 1
 131                          * Lanes: A,B: SGMII
 132                          * Lanes: C,D,E,F,G,H: CPRI
 133                          */
 134                 debug("Configuring crossbar to use onboard SGMII PHYs:"
 135                                 "srds_prctl:%x\n", serdes1_prtcl);
 136                 num_vsc16_con = NUM_CON_VSC3316;
 137                 /* Configure VSC3316 crossbar switch */
 138                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 139                 if (!ret) {
 140                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 141                                         vsc16_tx_4sfp_sgmii_12_56,
 142                                         num_vsc16_con);
 143                         if (ret)
 144                                 return ret;
 145                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 146                                         vsc16_rx_4sfp_sgmii_12_56,
 147                                         num_vsc16_con);
 148                         if (ret)
 149                                 return ret;
 150                 } else {
 151                         return ret;
 152                 }
 153                 break;
 154
 155         case 0x02:
 156         case 0x04:
 157         case 0x05:
 158         case 0x06:
 159         case 0x08:
 160         case 0x09:
 161         case 0x0A:
 162         case 0x0B:
 163         case 0x0C:
 164         case 0x30:
 165         case 0x32:
 166         case 0x33:
 167         case 0x34:
 168         case 0x39:
 169         case 0x3A:
 170         case 0x3C:
 171         case 0x3D:
 172         case 0x5C:
 173         case 0x5D:
 174                         /*
 175                          * Configuration:
 176                          * SERDES: 1
 177                          * Lanes: A,B: AURORA
 178                          * Lanes: C,d: SGMII
 179                          * Lanes: E,F,G,H: CPRI
 180                          */
 181                 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
 182                                 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
 183                 num_vsc16_con = NUM_CON_VSC3316;
 184                 /* Configure VSC3316 crossbar switch */
 185                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 186                 if (!ret) {
 187                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 188                                         vsc16_tx_sfp_sgmii_aurora,
 189                                         num_vsc16_con);
 190                         if (ret)
 191                                 return ret;
 192                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 193                                         vsc16_rx_sfp_sgmii_aurora,
 194                                         num_vsc16_con);
 195                         if (ret)
 196                                 return ret;
 197                 } else {
 198                         return ret;
 199                 }
 200                 break;
 201
 202 #ifdef CONFIG_PPC_B4420
 203         case 0x17:
 204         case 0x18:
 205                         /*
 206                          * Configuration:
 207                          * SERDES: 1
 208                          * Lanes: A,B,C,D: SGMII
 209                          * Lanes: E,F,G,H: CPRI
 210                          */
 211                 debug("Configuring crossbar to use onboard SGMII PHYs:"
 212                                 "srds_prctl:%x\n", serdes1_prtcl);
 213                 num_vsc16_con = NUM_CON_VSC3316;
 214                 /* Configure VSC3316 crossbar switch */
 215                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 216                 if (!ret) {
 217                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 218                                         vsc16_tx_sgmii_lane_cd, num_vsc16_con);
 219                         if (ret)
 220                                 return ret;
 221                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 222                                         vsc16_rx_sgmii_lane_cd, num_vsc16_con);
 223                         if (ret)
 224                                 return ret;
 225                 } else {
 226                         return ret;
 227                 }
 228                 break;
 229 #endif
 230
 231         case 0x3E:
 232         case 0x0D:
 233         case 0x0E:
 234         case 0x12:
 235                 num_vsc16_con = NUM_CON_VSC3316;
 236                 /* Configure VSC3316 crossbar switch */
 237                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 238                 if (!ret) {
 239                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 240                                         vsc16_tx_sfp, num_vsc16_con);
 241                         if (ret)
 242                                 return ret;
 243                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 244                                         vsc16_rx_sfp, num_vsc16_con);
 245                         if (ret)
 246                                 return ret;
 247                 } else {
 248                         return ret;
 249                 }
 250                 break;
 251         default:
 252                 printf("WARNING:VSC crossbars programming not supported for:%x"
 253                                         " SerDes1 Protocol.\n", serdes1_prtcl);
 254                 return -1;
 255         }
 256
 257         switch (serdes2_prtcl) {
 258         case 0x9E:
 259         case 0x9A:
 260         case 0x98:
 261         case 0xb2:
 262         case 0x49:
 263         case 0x4E:
 264         case 0x8D:
 265         case 0x7A:
 266                 num_vsc08_con = NUM_CON_VSC3308;
 267                 /* Configure VSC3308 crossbar switch */
 268                 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
 269                 if (!ret) {
 270                         ret = vsc3308_config(VSC3308_TX_ADDRESS,
 271                                         vsc08_tx_amc, num_vsc08_con);
 272                         if (ret)
 273                                 return ret;
 274                         ret = vsc3308_config(VSC3308_RX_ADDRESS,
 275                                         vsc08_rx_amc, num_vsc08_con);
 276                         if (ret)
 277                                 return ret;
 278                 } else {
 279                         return ret;
 280                 }
 281                 break;
 282         default:
 283                 printf("WARNING:VSC crossbars programming not supported for: %x"
 284                                         " SerDes2 Protocol.\n", serdes2_prtcl);
 285                 return -1;
 286         }
 287
 288         return 0;
 289 }
 290
 291 int config_serdes1_refclks(void)
 292 {
 293         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 294         serdes_corenet_t *srds_regs =
 295                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 296         u32 serdes1_prtcl, lane;
 297         unsigned int flag_sgmii_aurora_prtcl = 0;
 298         int i;
 299         int ret = 0;
 300
 301         serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 302                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 303         if (!serdes1_prtcl) {
 304                 printf("SERDES1 is not enabled\n");
 305                 return -1;
 306         }
 307         serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 308         debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
 309
 310         /* To prevent generation of reset request from SerDes
 311          * while changing the refclks, By setting SRDS_RST_MSK bit,
 312          * SerDes reset event cannot cause a reset request
 313          */
 314         setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 315
 316         /* Reconfigure IDT idt8t49n222a device for CPRI to work
 317          * For this SerDes1's Refclk1 and refclk2 need to be set
 318          * to 122.88MHz
 319          */
 320         switch (serdes1_prtcl) {
 321         case 0x2A:
 322         case 0x2C:
 323         case 0x2D:
 324         case 0x2E:
 325         case 0x02:
 326         case 0x04:
 327         case 0x05:
 328         case 0x06:
 329         case 0x08:
 330         case 0x09:
 331         case 0x0A:
 332         case 0x0B:
 333         case 0x0C:
 334         case 0x30:
 335         case 0x32:
 336         case 0x33:
 337         case 0x34:
 338         case 0x39:
 339         case 0x3A:
 340         case 0x3C:
 341         case 0x3D:
 342         case 0x5C:
 343         case 0x5D:
 344                 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
 345                         " for srds_prctl:%x\n", serdes1_prtcl);
 346                 ret = select_i2c_ch_pca(I2C_CH_IDT);
 347                 if (!ret) {
 348                         ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
 349                                         SERDES_REFCLK_122_88,
 350                                         SERDES_REFCLK_122_88, 0);
 351                         if (ret) {
 352                                 printf("IDT8T49N222A configuration failed.\n");
 353                                 goto out;
 354                         } else
 355                                 debug("IDT8T49N222A configured.\n");
 356                 } else {
 357                         goto out;
 358                 }
 359                 select_i2c_ch_pca(I2C_CH_DEFAULT);
 360
 361                 /* Change SerDes1's Refclk1 to 125MHz for on board
 362                  * SGMIIs or Aurora to work
 363                  */
 364                 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 365                         enum srds_prtcl lane_prtcl = serdes_get_prtcl
 366                                                 (0, serdes1_prtcl, lane);
 367                         switch (lane_prtcl) {
 368                         case SGMII_FM1_DTSEC1:
 369                         case SGMII_FM1_DTSEC2:
 370                         case SGMII_FM1_DTSEC3:
 371                         case SGMII_FM1_DTSEC4:
 372                         case SGMII_FM1_DTSEC5:
 373                         case SGMII_FM1_DTSEC6:
 374                         case AURORA:
 375                                 flag_sgmii_aurora_prtcl++;
 376                                 break;
 377                         default:
 378                                 break;
 379                         }
 380                 }
 381
 382                 if (flag_sgmii_aurora_prtcl)
 383                         QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
 384
 385                 /* Steps For SerDes PLLs reset and reconfiguration after
 386                  * changing SerDes's refclks
 387                  */
 388                 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 389                         debug("For PLL%d reset and reconfiguration after"
 390                                " changing refclks\n", i+1);
 391                         clrbits_be32(&srds_regs->bank[i].rstctl,
 392                                         SRDS_RSTCTL_SDRST_B);
 393                         udelay(10);
 394                         clrbits_be32(&srds_regs->bank[i].rstctl,
 395                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
 396                         udelay(10);
 397                         setbits_be32(&srds_regs->bank[i].rstctl,
 398                                         SRDS_RSTCTL_RST);
 399                         setbits_be32(&srds_regs->bank[i].rstctl,
 400                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 401                                 | SRDS_RSTCTL_SDRST_B));
 402                 }
 403                 break;
 404         default:
 405                 printf("WARNING:IDT8T49N222A configuration not"
 406                         " supported for:%x SerDes1 Protocol.\n",
 407                         serdes1_prtcl);
 408         }
 409
 410 out:
 411         /* Clearing SRDS_RST_MSK bit as now
 412          * SerDes reset event can cause a reset request
 413          */
 414         clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 415         return ret;
 416 }
 417
 418 int config_serdes2_refclks(void)
 419 {
 420         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 421         serdes_corenet_t *srds2_regs =
 422                 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
 423         u32 serdes2_prtcl;
 424         int ret = 0;
 425         int i;
 426
 427         serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
 428                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 429         if (!serdes2_prtcl) {
 430                 debug("SERDES2 is not enabled\n");
 431                 return -ENODEV;
 432         }
 433         serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 434         debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
 435
 436         /* To prevent generation of reset request from SerDes
 437          * while changing the refclks, By setting SRDS_RST_MSK bit,
 438          * SerDes reset event cannot cause a reset request
 439          */
 440         setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 441
 442         /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
 443          * For this SerDes2's Refclk1 need to be set to 100MHz
 444          */
 445         switch (serdes2_prtcl) {
 446         case 0x9E:
 447         case 0x9A:
 448         case 0xb2:
 449                 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
 450                         serdes2_prtcl);
 451                 ret = select_i2c_ch_pca(I2C_CH_IDT);
 452                 if (!ret) {
 453                         ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
 454                                         SERDES_REFCLK_100,
 455                                         SERDES_REFCLK_156_25, 0);
 456                         if (ret) {
 457                                 printf("IDT8T49N222A configuration failed.\n");
 458                                 goto out;
 459                         } else
 460                                 debug("IDT8T49N222A configured.\n");
 461                 } else {
 462                         goto out;
 463                 }
 464                 select_i2c_ch_pca(I2C_CH_DEFAULT);
 465
 466                 /* Steps For SerDes PLLs reset and reconfiguration after
 467                  * changing SerDes's refclks
 468                  */
 469                 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 470                         clrbits_be32(&srds2_regs->bank[i].rstctl,
 471                                         SRDS_RSTCTL_SDRST_B);
 472                         udelay(10);
 473                         clrbits_be32(&srds2_regs->bank[i].rstctl,
 474                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
 475                         udelay(10);
 476                         setbits_be32(&srds2_regs->bank[i].rstctl,
 477                                         SRDS_RSTCTL_RST);
 478                         setbits_be32(&srds2_regs->bank[i].rstctl,
 479                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 480                                 | SRDS_RSTCTL_SDRST_B));
 481                 }
 482                 break;
 483         default:
 484                 printf("IDT configuration not supported for:%x S2 Protocol.\n",
 485                         serdes2_prtcl);
 486         }
 487
 488 out:
 489         /* Clearing SRDS_RST_MSK bit as now
 490          * SerDes reset event can cause a reset request
 491          */
 492         clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 493         return ret;
 494 }
 495
 496 int board_early_init_r(void)
 497 {
 498         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 499         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 500         int ret;
 501
 502         /*
 503          * Remap Boot flash + PROMJET region to caching-inhibited
 504          * so that flash can be erased properly.
 505          */
 506
 507         /* Flush d-cache and invalidate i-cache of any FLASH data */
 508         flush_dcache();
 509         invalidate_icache();
 510
 511         /* invalidate existing TLB entry for flash + promjet */
 512         disable_tlb(flash_esel);
 513
 514         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 515                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 516                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 517
 518         set_liodns();
 519 #ifdef CONFIG_SYS_DPAA_QBMAN
 520         setup_portals();
 521 #endif
 522         /* SerDes1 refclks need to be set again, as default clks
 523          * are not suitable for CPRI and onboard SGMIIs to work
 524          * simultaneously.
 525          * This function will set SerDes1's Refclk1 and refclk2
 526          * as per SerDes1 protocols
 527          */
 528         if (config_serdes1_refclks())
 529                 printf("SerDes1 Refclks couldn't set properly.\n");
 530         else
 531                 printf("SerDes1 Refclks have been set.\n");
 532
 533         /* SerDes2 refclks need to be set again, as default clks
 534          * are not suitable for PCIe SATA to work
 535          * This function will set SerDes2's Refclk1 and refclk2
 536          * for SerDes2 protocols having PCIe in them
 537          * for PCIe SATA to work
 538          */
 539         ret = config_serdes2_refclks();
 540         if (!ret)
 541                 printf("SerDes2 Refclks have been set.\n");
 542         else if (ret == -ENODEV)
 543                 printf("SerDes disable, Refclks couldn't change.\n");
 544         else
 545                 printf("SerDes2 Refclk reconfiguring failed.\n");
 546
 547         /* Configure VSC3316 and VSC3308 crossbar switches */
 548         if (configure_vsc3316_3308())
 549                 printf("VSC:failed to configure VSC3316/3308.\n");
 550         else
 551                 printf("VSC:VSC3316/3308 successfully configured.\n");
 552
 553         select_i2c_ch_pca(I2C_CH_DEFAULT);
 554
 555         return 0;
 556 }
 557
 558 unsigned long get_board_sys_clk(void)
 559 {
 560         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 561
 562         switch ((sysclk_conf & 0x0C) >> 2) {
 563         case QIXIS_CLK_100:
 564                 return 100000000;
 565         case QIXIS_CLK_125:
 566                 return 125000000;
 567         case QIXIS_CLK_133:
 568                 return 133333333;
 569         }
 570         return 66666666;
 571 }
 572
 573 unsigned long get_board_ddr_clk(void)
 574 {
 575         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 576
 577         switch (ddrclk_conf & 0x03) {
 578         case QIXIS_CLK_100:
 579                 return 100000000;
 580         case QIXIS_CLK_125:
 581                 return 125000000;
 582         case QIXIS_CLK_133:
 583                 return 133333333;
 584         }
 585         return 66666666;
 586 }
 587
 588 static int serdes_refclock(u8 sw, u8 sdclk)
 589 {
 590         unsigned int clock;
 591         int ret = -1;
 592         u8 brdcfg4;
 593
 594         if (sdclk == 1) {
 595                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 596                 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
 597                         return SRDS_PLLCR0_RFCK_SEL_125;
 598                 else
 599                         clock = (sw >> 5) & 7;
 600         } else
 601                 clock = (sw >> 6) & 3;
 602
 603         switch (clock) {
 604         case 0:
 605                 ret = SRDS_PLLCR0_RFCK_SEL_100;
 606                 break;
 607         case 1:
 608                 ret = SRDS_PLLCR0_RFCK_SEL_125;
 609                 break;
 610         case 2:
 611                 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
 612                 break;
 613         case 3:
 614                 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
 615                 break;
 616         case 4:
 617         case 5:
 618         case 6:
 619                 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
 620                 break;
 621         default:
 622                 ret = -1;
 623                 break;
 624         }
 625
 626         return ret;
 627 }
 628
 629 #define NUM_SRDS_BANKS  2
 630
 631 int misc_init_r(void)
 632 {
 633         u8 sw;
 634         serdes_corenet_t *srds_regs =
 635                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 636         u32 actual[NUM_SRDS_BANKS];
 637         unsigned int i;
 638         int clock;
 639
 640         sw = QIXIS_READ(brdcfg[2]);
 641         clock = serdes_refclock(sw, 1);
 642         if (clock >= 0)
 643                 actual[0] = clock;
 644         else
 645                 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
 646
 647         sw = QIXIS_READ(brdcfg[4]);
 648         clock = serdes_refclock(sw, 2);
 649         if (clock >= 0)
 650                 actual[1] = clock;
 651         else
 652                 printf("Warning: SDREFCLK2 switch setting unsupported\n");
 653
 654         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 655                 u32 pllcr0 = srds_regs->bank[i].pllcr0;
 656                 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
 657                 if (expected != actual[i]) {
 658                         printf("Warning: SERDES bank %u expects reference clock"
 659                                " %sMHz, but actual is %sMHz\n", i + 1,
 660                                serdes_clock_to_string(expected),
 661                                serdes_clock_to_string(actual[i]));
 662                 }
 663         }
 664
 665         return 0;
 666 }
 667
 668 void ft_board_setup(void *blob, bd_t *bd)
 669 {
 670         phys_addr_t base;
 671         phys_size_t size;
 672
 673         ft_cpu_setup(blob, bd);
 674
 675         base = getenv_bootm_low();
 676         size = getenv_bootm_size();
 677
 678         fdt_fixup_memory(blob, (u64)base, (u64)size);
 679
 680 #ifdef CONFIG_PCI
 681         pci_of_setup(blob, bd);
 682 #endif
 683
 684         fdt_fixup_liodn(blob);
 685
 686 #ifdef CONFIG_HAS_FSL_DR_USB
 687         fdt_fixup_dr_usb(blob, bd);
 688 #endif
 689
 690 #ifdef CONFIG_SYS_DPAA_FMAN
 691         fdt_fixup_fman_ethernet(blob);
 692         fdt_fixup_board_enet(blob);
 693 #endif
 694 }
 695
 696 /*
 697  * Dump board switch settings.
 698  * The bits that cannot be read/sampled via some FPGA or some
 699  * registers, they will be displayed as
 700  * underscore in binary format. mask[] has those bits.
 701  * Some bits are calculated differently than the actual switches
 702  * if booting with overriding by FPGA.
 703  */
 704 void qixis_dump_switch(void)
 705 {
 706         int i;
 707         u8 sw[5];
 708
 709         /*
 710          * Any bit with 1 means that bit cannot be reverse engineered.
 711          * It will be displayed as _ in binary format.
 712          */
 713         static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
 714         char buf[10];
 715         u8 brdcfg[16], dutcfg[16];
 716
 717         for (i = 0; i < 16; i++) {
 718                 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
 719                 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
 720         }
 721
 722         sw[0] = ((brdcfg[0] & 0x0f) << 4)       | \
 723                 (brdcfg[9] & 0x08);
 724         sw[1] = ((dutcfg[1] & 0x01) << 7)       | \
 725                 ((dutcfg[2] & 0x07) << 4)       | \
 726                 ((dutcfg[6] & 0x10) >> 1)       | \
 727                 ((dutcfg[6] & 0x80) >> 5)       | \
 728                 ((dutcfg[1] & 0x40) >> 5)       | \
 729                 (dutcfg[6] & 0x01);
 730         sw[2] = dutcfg[0];
 731         sw[3] = 0;
 732         sw[4] = ((brdcfg[1] & 0x30) << 2)       | \
 733                 ((brdcfg[1] & 0xc0) >> 2)       | \
 734                 (brdcfg[1] & 0x0f);
 735
 736         puts("DIP switch settings:\n");
 737         for (i = 0; i < 5; i++) {
 738                 printf("SW%d         = 0b%s (0x%02x)\n",
 739                         i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
 740         }
 741 }