board/freescale/mpc8349emds/ddr.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8
   9 #include <fsl_ddr_sdram.h>
  10 #include <fsl_ddr_dimm_params.h>
  11
  12 struct board_specific_parameters {
  13         u32 n_ranks;
  14         u32 datarate_mhz_high;
  15         u32 clk_adjust;
  16         u32 cpo;
  17         u32 write_data_delay;
  18         u32 force_2t;
  19 };
  20
  21 /*
  22  * This table contains all valid speeds we want to override with board
  23  * specific parameters. datarate_mhz_high values need to be in ascending order
  24  * for each n_ranks group.
  25  */
  26 static const struct board_specific_parameters udimm0[] = {
  27         /*
  28          * memory controller 0
  29          *   num|  hi|  clk| cpo|wrdata|2T
  30          * ranks| mhz|adjst|    | delay|
  31          */
  32         {2,  300,    4,   4,    2,  0},
  33         {2,  365,    4,   6,    2,  0},
  34         {2,  450,    4,   7,    2,  0},
  35         {2,  850,    4,  31,    2,  0},
  36         {1,  300,    4,   4,    2,  0},
  37         {1,  365,    4,   6,    2,  0},
  38         {1,  450,    4,   7,    2,  0},
  39         {1,  850,    4,  31,    2,  0},
  40         {}
  41 };
  42
  43 void fsl_ddr_board_options(memctl_options_t *popts,
  44                                 dimm_params_t *pdimm,
  45                                 unsigned int ctrl_num)
  46 {
  47         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  48         unsigned int i;
  49         ulong ddr_freq;
  50
  51         if (ctrl_num != 0)      /* we have only one controller */
  52                 return;
  53         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  54                 if (pdimm[i].n_ranks)
  55                         break;
  56         }
  57         if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)    /* no DIMM */
  58                 return;
  59
  60         pbsp = udimm0;
  61
  62         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  63          * freqency and n_banks specified in board_specific_parameters table.
  64          */
  65         ddr_freq = get_ddr_freq(0) / 1000000;
  66         while (pbsp->datarate_mhz_high) {
  67                 if (pbsp->n_ranks ==  pdimm[i].n_ranks) {
  68                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  69                                 popts->clk_adjust = pbsp->clk_adjust;
  70                                 popts->cpo_override = pbsp->cpo;
  71                                 popts->write_data_delay =
  72                                         pbsp->write_data_delay;
  73                                 popts->twot_en = pbsp->force_2t;
  74                                 goto found;
  75                         }
  76                         pbsp_highest = pbsp;
  77                 }
  78                 pbsp++;
  79         }
  80
  81         if (pbsp_highest) {
  82                 printf("Error: board specific timing not found "
  83                         "for data rate %lu MT/s!\n"
  84                         "Trying to use the highest speed (%u) parameters\n",
  85                         ddr_freq, pbsp_highest->datarate_mhz_high);
  86                 popts->clk_adjust = pbsp_highest->clk_adjust;
  87                 popts->cpo_override = pbsp_highest->cpo;
  88                 popts->write_data_delay = pbsp_highest->write_data_delay;
  89                 popts->twot_en = pbsp_highest->force_2t;
  90         } else {
  91                 panic("DIMM is not supported by this board");
  92         }
  93
  94 found:
  95         /*
  96          * Factors to consider for half-strength driver enable:
  97          *      - number of DIMMs installed
  98          */
  99         popts->half_strength_driver_enable = 0;
 100         popts->dqs_config = 0;  /* only true DQS signal is used on board */
 101 }