board/freescale/mx53loco/mx53loco.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   3  * Jason Liu <r64343@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/iomux-mx53.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/errno.h>
  17 #include <asm/imx-common/mx5_video.h>
  18 #include <netdev.h>
  19 #include <i2c.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc.h>
  22 #include <asm/gpio.h>
  23 #include <power/pmic.h>
  24 #include <dialog_pmic.h>
  25 #include <fsl_pmic.h>
  26 #include <linux/fb.h>
  27 #include <ipu_pixfmt.h>
  28
  29 #define MX53LOCO_LCD_POWER              IMX_GPIO_NR(3, 24)
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 static uint32_t mx53_dram_size[2];
  34
  35 phys_size_t get_effective_memsize(void)
  36 {
  37         /*
  38          * WARNING: We must override get_effective_memsize() function here
  39          * to report only the size of the first DRAM bank. This is to make
  40          * U-Boot relocator place U-Boot into valid memory, that is, at the
  41          * end of the first DRAM bank. If we did not override this function
  42          * like so, U-Boot would be placed at the address of the first DRAM
  43          * bank + total DRAM size - sizeof(uboot), which in the setup where
  44          * each DRAM bank contains 512MiB of DRAM would result in placing
  45          * U-Boot into invalid memory area close to the end of the first
  46          * DRAM bank.
  47          */
  48         return mx53_dram_size[0];
  49 }
  50
  51 int dram_init(void)
  52 {
  53         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  54         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  55
  56         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  57
  58         return 0;
  59 }
  60
  61 void dram_init_banksize(void)
  62 {
  63         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  64         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  65
  66         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  67         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  68 }
  69
  70 u32 get_board_rev(void)
  71 {
  72         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  73         struct fuse_bank *bank = &iim->bank[0];
  74         struct fuse_bank0_regs *fuse =
  75                 (struct fuse_bank0_regs *)bank->fuse_regs;
  76
  77         int rev = readl(&fuse->gp[6]);
  78
  79         if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
  80                 rev = 0;
  81
  82         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  83 }
  84
  85 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  86                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  87
  88 static void setup_iomux_uart(void)
  89 {
  90         static const iomux_v3_cfg_t uart_pads[] = {
  91                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  92                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  93         };
  94
  95         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  96 }
  97
  98 #ifdef CONFIG_USB_EHCI_MX5
  99 int board_ehci_hcd_init(int port)
 100 {
 101         /* request VBUS power enable pin, GPIO7_8 */
 102         imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
 103         gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
 104         return 0;
 105 }
 106 #endif
 107
 108 static void setup_iomux_fec(void)
 109 {
 110         static const iomux_v3_cfg_t fec_pads[] = {
 111                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
 112                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
 113                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
 114                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 115                                 PAD_CTL_HYS | PAD_CTL_PKE),
 116                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 117                                 PAD_CTL_HYS | PAD_CTL_PKE),
 118                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 119                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 120                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 121                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 122                                 PAD_CTL_HYS | PAD_CTL_PKE),
 123                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 124                                 PAD_CTL_HYS | PAD_CTL_PKE),
 125                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 126                                 PAD_CTL_HYS | PAD_CTL_PKE),
 127         };
 128
 129         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 130 }
 131
 132 #ifdef CONFIG_FSL_ESDHC
 133 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 134         {MMC_SDHC1_BASE_ADDR},
 135         {MMC_SDHC3_BASE_ADDR},
 136 };
 137
 138 int board_mmc_getcd(struct mmc *mmc)
 139 {
 140         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 141         int ret;
 142
 143         imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
 144         gpio_direction_input(IMX_GPIO_NR(3, 11));
 145         imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 146         gpio_direction_input(IMX_GPIO_NR(3, 13));
 147
 148         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 149                 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
 150         else
 151                 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
 152
 153         return ret;
 154 }
 155
 156 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 157                                  PAD_CTL_PUS_100K_UP)
 158 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 159                                  PAD_CTL_DSE_HIGH)
 160
 161 int board_mmc_init(bd_t *bis)
 162 {
 163         static const iomux_v3_cfg_t sd1_pads[] = {
 164                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 165                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 166                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 167                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 168                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 169                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 170                 MX53_PAD_EIM_DA13__GPIO3_13,
 171         };
 172
 173         static const iomux_v3_cfg_t sd2_pads[] = {
 174                 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
 175                                 SD_CMD_PAD_CTRL),
 176                 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
 177                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
 178                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
 179                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
 180                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
 181                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
 182                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
 183                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
 184                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
 185                 MX53_PAD_EIM_DA11__GPIO3_11,
 186         };
 187
 188         u32 index;
 189         s32 status = 0;
 190
 191         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 192         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 193
 194         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 195                 switch (index) {
 196                 case 0:
 197                         imx_iomux_v3_setup_multiple_pads(sd1_pads,
 198                                                          ARRAY_SIZE(sd1_pads));
 199                         break;
 200                 case 1:
 201                         imx_iomux_v3_setup_multiple_pads(sd2_pads,
 202                                                          ARRAY_SIZE(sd2_pads));
 203                         break;
 204                 default:
 205                         printf("Warning: you configured more ESDHC controller"
 206                                 "(%d) as supported by the board(2)\n",
 207                                 CONFIG_SYS_FSL_ESDHC_NUM);
 208                         return status;
 209                 }
 210                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 211         }
 212
 213         return status;
 214 }
 215 #endif
 216
 217 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 218                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 219
 220 static void setup_iomux_i2c(void)
 221 {
 222         static const iomux_v3_cfg_t i2c1_pads[] = {
 223                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
 224                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
 225         };
 226
 227         imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
 228 }
 229
 230 static int power_init(void)
 231 {
 232         unsigned int val;
 233         int ret;
 234         struct pmic *p;
 235
 236         if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
 237                 ret = pmic_dialog_init(I2C_PMIC);
 238                 if (ret)
 239                         return ret;
 240
 241                 p = pmic_get("DIALOG_PMIC");
 242                 if (!p)
 243                         return -ENODEV;
 244
 245                 /* Set VDDA to 1.25V */
 246                 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
 247                 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
 248                 if (ret) {
 249                         printf("Writing to BUCKCORE_REG failed: %d\n", ret);
 250                         return ret;
 251                 }
 252
 253                 pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
 254                 val |= DA9052_SUPPLY_VBCOREGO;
 255                 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
 256                 if (ret) {
 257                         printf("Writing to SUPPLY_REG failed: %d\n", ret);
 258                         return ret;
 259                 }
 260
 261                 /* Set Vcc peripheral to 1.30V */
 262                 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
 263                 if (ret) {
 264                         printf("Writing to BUCKPRO_REG failed: %d\n", ret);
 265                         return ret;
 266                 }
 267
 268                 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
 269                 if (ret) {
 270                         printf("Writing to SUPPLY_REG failed: %d\n", ret);
 271                         return ret;
 272                 }
 273
 274                 return ret;
 275         }
 276
 277         if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
 278                 ret = pmic_init(I2C_0);
 279                 if (ret)
 280                         return ret;
 281
 282                 p = pmic_get("FSL_PMIC");
 283                 if (!p)
 284                         return -ENODEV;
 285
 286                 /* Set VDDGP to 1.25V for 1GHz on SW1 */
 287                 pmic_reg_read(p, REG_SW_0, &val);
 288                 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
 289                 ret = pmic_reg_write(p, REG_SW_0, val);
 290                 if (ret) {
 291                         printf("Writing to REG_SW_0 failed: %d\n", ret);
 292                         return ret;
 293                 }
 294
 295                 /* Set VCC as 1.30V on SW2 */
 296                 pmic_reg_read(p, REG_SW_1, &val);
 297                 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
 298                 ret = pmic_reg_write(p, REG_SW_1, val);
 299                 if (ret) {
 300                         printf("Writing to REG_SW_1 failed: %d\n", ret);
 301                         return ret;
 302                 }
 303
 304                 /* Set global reset timer to 4s */
 305                 pmic_reg_read(p, REG_POWER_CTL2, &val);
 306                 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
 307                 ret = pmic_reg_write(p, REG_POWER_CTL2, val);
 308                 if (ret) {
 309                         printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
 310                         return ret;
 311                 }
 312
 313                 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
 314                 pmic_reg_read(p, REG_MODE_0, &val);
 315                 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
 316                 ret = pmic_reg_write(p, REG_MODE_0, val);
 317                 if (ret) {
 318                         printf("Writing to REG_MODE_0 failed: %d\n", ret);
 319                         return ret;
 320                 }
 321
 322                 /* Set SWBST to 5V in auto mode */
 323                 val = SWBST_AUTO;
 324                 ret = pmic_reg_write(p, SWBST_CTRL, val);
 325                 if (ret) {
 326                         printf("Writing to SWBST_CTRL failed: %d\n", ret);
 327                         return ret;
 328                 }
 329
 330                 return ret;
 331         }
 332
 333         return -1;
 334 }
 335
 336 static void clock_1GHz(void)
 337 {
 338         int ret;
 339         u32 ref_clk = MXC_HCLK;
 340         /*
 341          * After increasing voltage to 1.25V, we can switch
 342          * CPU clock to 1GHz and DDR to 400MHz safely
 343          */
 344         ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
 345         if (ret)
 346                 printf("CPU:   Switch CPU clock to 1GHZ failed\n");
 347
 348         ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
 349         ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
 350         if (ret)
 351                 printf("CPU:   Switch DDR clock to 400MHz failed\n");
 352 }
 353
 354 int board_early_init_f(void)
 355 {
 356         setup_iomux_uart();
 357         setup_iomux_fec();
 358         setup_iomux_lcd();
 359
 360         return 0;
 361 }
 362
 363 #if defined(CONFIG_DISPLAY_CPUINFO)
 364 int print_cpuinfo(void)
 365 {
 366         u32 cpurev;
 367
 368         cpurev = get_cpu_rev();
 369         printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
 370                 (cpurev & 0xFF000) >> 12,
 371                 (cpurev & 0x000F0) >> 4,
 372                 (cpurev & 0x0000F) >> 0,
 373                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 374         printf("Reset cause: %s\n", get_reset_cause());
 375         return 0;
 376 }
 377 #endif
 378
 379 /*
 380  * Do not overwrite the console
 381  * Use always serial for U-Boot console
 382  */
 383 int overwrite_console(void)
 384 {
 385         return 1;
 386 }
 387
 388 int board_init(void)
 389 {
 390         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 391
 392         mxc_set_sata_internal_clock();
 393         setup_iomux_i2c();
 394
 395         return 0;
 396 }
 397
 398 int board_late_init(void)
 399 {
 400         if (!power_init())
 401                 clock_1GHz();
 402         print_cpuinfo();
 403
 404         return 0;
 405 }
 406
 407 int checkboard(void)
 408 {
 409         puts("Board: MX53 LOCO\n");
 410
 411         return 0;
 412 }