board/freescale/mx6qsabreauto/mx6qsabreauto.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <asm/imx-common/boot_mode.h>
  20 #include <asm/imx-common/spi.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <miiphy.h>
  24 #include <netdev.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <i2c.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/imx-common/video.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <pca953x.h>
  31 #include <power/pmic.h>
  32 #include "../common/pfuze.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  41         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46
  47 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  49         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  50
  51 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  52 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  53                         PAD_CTL_SRE_FAST)
  54 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  55
  56 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  57
  58 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
  59         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  60         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  61
  62 #define I2C_PMIC        1
  63
  64 int dram_init(void)
  65 {
  66         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  67
  68         return 0;
  69 }
  70
  71 static iomux_v3_cfg_t const uart4_pads[] = {
  72         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  74 };
  75
  76 static iomux_v3_cfg_t const enet_pads[] = {
  77         MX6_PAD_KEY_COL1__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_KEY_COL2__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92 };
  93
  94 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  95 static struct i2c_pads_info i2c_pad_info1 = {
  96         .scl = {
  97                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  98                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  99                 .gp = IMX_GPIO_NR(2, 30)
 100         },
 101         .sda = {
 102                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 103                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 104                 .gp = IMX_GPIO_NR(4, 13)
 105         }
 106 };
 107
 108 #ifndef CONFIG_SYS_FLASH_CFI
 109 /*
 110  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
 111  * Compass Sensor, Accelerometer, Res Touch
 112  */
 113 static struct i2c_pads_info i2c_pad_info2 = {
 114         .scl = {
 115                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
 116                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 117                 .gp = IMX_GPIO_NR(1, 3)
 118         },
 119         .sda = {
 120                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 121                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 122                 .gp = IMX_GPIO_NR(3, 18)
 123         }
 124 };
 125 #endif
 126
 127 static iomux_v3_cfg_t const i2c3_pads[] = {
 128         MX6_PAD_EIM_A24__GPIO5_IO04,
 129 };
 130
 131 static iomux_v3_cfg_t const port_exp[] = {
 132         MX6_PAD_SD2_DAT0__GPIO1_IO15,
 133 };
 134
 135 /*Define for building port exp gpio, pin starts from 0*/
 136 #define PORTEXP_IO_NR(chip, pin) \
 137         ((chip << 5) + pin)
 138
 139 /*Get the chip addr from a ioexp gpio*/
 140 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
 141         (gpio_nr >> 5)
 142
 143 /*Get the pin number from a ioexp gpio*/
 144 #define PORTEXP_IO_TO_PIN(gpio_nr) \
 145         (gpio_nr & 0x1f)
 146
 147 static int port_exp_direction_output(unsigned gpio, int value)
 148 {
 149         int ret;
 150
 151         i2c_set_bus_num(2);
 152         ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
 153         if (ret)
 154                 return ret;
 155
 156         ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
 157                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 158                 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
 159
 160         if (ret)
 161                 return ret;
 162
 163         ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
 164                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 165                 (value << PORTEXP_IO_TO_PIN(gpio)));
 166
 167         if (ret)
 168                 return ret;
 169
 170         return 0;
 171 }
 172
 173 static iomux_v3_cfg_t const eimnor_pads[] = {
 174         MX6_PAD_EIM_D16__EIM_DATA16     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 175         MX6_PAD_EIM_D17__EIM_DATA17     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 176         MX6_PAD_EIM_D18__EIM_DATA18     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 177         MX6_PAD_EIM_D19__EIM_DATA19     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 178         MX6_PAD_EIM_D20__EIM_DATA20     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 179         MX6_PAD_EIM_D21__EIM_DATA21     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 180         MX6_PAD_EIM_D22__EIM_DATA22     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 181         MX6_PAD_EIM_D23__EIM_DATA23     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 182         MX6_PAD_EIM_D24__EIM_DATA24     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 183         MX6_PAD_EIM_D25__EIM_DATA25     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 184         MX6_PAD_EIM_D26__EIM_DATA26     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 185         MX6_PAD_EIM_D27__EIM_DATA27     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 186         MX6_PAD_EIM_D28__EIM_DATA28     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 187         MX6_PAD_EIM_D29__EIM_DATA29     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 188         MX6_PAD_EIM_D30__EIM_DATA30     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 189         MX6_PAD_EIM_D31__EIM_DATA31     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 190         MX6_PAD_EIM_DA0__EIM_AD00       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 191         MX6_PAD_EIM_DA1__EIM_AD01       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 192         MX6_PAD_EIM_DA2__EIM_AD02       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 193         MX6_PAD_EIM_DA3__EIM_AD03       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 194         MX6_PAD_EIM_DA4__EIM_AD04       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 195         MX6_PAD_EIM_DA5__EIM_AD05       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 196         MX6_PAD_EIM_DA6__EIM_AD06       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 197         MX6_PAD_EIM_DA7__EIM_AD07       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 198         MX6_PAD_EIM_DA8__EIM_AD08       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 199         MX6_PAD_EIM_DA9__EIM_AD09       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 200         MX6_PAD_EIM_DA10__EIM_AD10      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 201         MX6_PAD_EIM_DA11__EIM_AD11      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
 202         MX6_PAD_EIM_DA12__EIM_AD12      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 203         MX6_PAD_EIM_DA13__EIM_AD13      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 204         MX6_PAD_EIM_DA14__EIM_AD14      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 205         MX6_PAD_EIM_DA15__EIM_AD15      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 206         MX6_PAD_EIM_A16__EIM_ADDR16     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 207         MX6_PAD_EIM_A17__EIM_ADDR17     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 208         MX6_PAD_EIM_A18__EIM_ADDR18     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 209         MX6_PAD_EIM_A19__EIM_ADDR19     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 210         MX6_PAD_EIM_A20__EIM_ADDR20     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 211         MX6_PAD_EIM_A21__EIM_ADDR21     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 212         MX6_PAD_EIM_A22__EIM_ADDR22     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 213         MX6_PAD_EIM_A23__EIM_ADDR23     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
 214         MX6_PAD_EIM_OE__EIM_OE_B,
 215         MX6_PAD_EIM_RW__EIM_RW,
 216         MX6_PAD_EIM_CS0__EIM_CS0_B,
 217 };
 218
 219 static void eimnor_cs_setup(void)
 220 {
 221         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 222
 223         writel(0x00020181, &weim_regs->cs0gcr1);
 224         writel(0x00000001, &weim_regs->cs0gcr2);
 225         writel(0x0a020000, &weim_regs->cs0rcr1);
 226         writel(0x0000c000, &weim_regs->cs0rcr2);
 227         writel(0x0804a240, &weim_regs->cs0wcr1);
 228         writel(0x00000120, &weim_regs->wcr);
 229
 230         set_chipselect_size(CS0_128);
 231 }
 232
 233 static void setup_iomux_eimnor(void)
 234 {
 235         imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
 236
 237         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 238
 239         eimnor_cs_setup();
 240 }
 241
 242 static void setup_iomux_enet(void)
 243 {
 244         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 245 }
 246
 247 static iomux_v3_cfg_t const usdhc3_pads[] = {
 248         MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 249         MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 250         MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 251         MX6_PAD_SD3_DAT1__SD3_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 252         MX6_PAD_SD3_DAT2__SD3_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 253         MX6_PAD_SD3_DAT3__SD3_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 254         MX6_PAD_SD3_DAT4__SD3_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 255         MX6_PAD_SD3_DAT5__SD3_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 256         MX6_PAD_SD3_DAT6__SD3_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 257         MX6_PAD_SD3_DAT7__SD3_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 258         MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 259         MX6_PAD_NANDF_CS2__GPIO6_IO15,
 260 };
 261
 262 static void setup_iomux_uart(void)
 263 {
 264         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 265 }
 266
 267 #ifdef CONFIG_FSL_ESDHC
 268 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 269         {USDHC3_BASE_ADDR},
 270 };
 271
 272 int board_mmc_getcd(struct mmc *mmc)
 273 {
 274         gpio_direction_input(IMX_GPIO_NR(6, 15));
 275         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 276 }
 277
 278 int board_mmc_init(bd_t *bis)
 279 {
 280         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 281
 282         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 283         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 284 }
 285 #endif
 286
 287 #ifdef CONFIG_NAND_MXS
 288 static iomux_v3_cfg_t gpmi_pads[] = {
 289         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 290         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 291         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 292         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
 293         MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 294         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 295         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 296         MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 297         MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 298         MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 299         MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 300         MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 301         MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 302         MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 303         MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
 304         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
 305 };
 306
 307 static void setup_gpmi_nand(void)
 308 {
 309         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 310
 311         /* config gpmi nand iomux */
 312         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 313
 314         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 315         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 316         clrbits_le32(&mxc_ccm->CCGR4,
 317                 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 318
 319         /* config gpmi and bch clock to 100 MHz */
 320         clrsetbits_le32(&mxc_ccm->cs2cdr,
 321                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 322                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 323                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 324                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 325                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 326                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 327
 328         /* enable ENFC_CLK_ROOT clock */
 329         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 330
 331         /* enable gpmi and bch clock gating */
 332         setbits_le32(&mxc_ccm->CCGR4,
 333                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 334                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 335                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 336                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 337                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 338
 339         /* enable apbh clock gating */
 340         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 341 }
 342 #endif
 343
 344 int mx6_rgmii_rework(struct phy_device *phydev)
 345 {
 346         unsigned short val;
 347
 348         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 349         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 350         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 351         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 352
 353         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 354         val &= 0xffe3;
 355         val |= 0x18;
 356         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 357
 358         /* introduce tx clock delay */
 359         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 360         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 361         val |= 0x0100;
 362         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 363
 364         return 0;
 365 }
 366
 367 int board_phy_config(struct phy_device *phydev)
 368 {
 369         mx6_rgmii_rework(phydev);
 370
 371         if (phydev->drv->config)
 372                 phydev->drv->config(phydev);
 373
 374         return 0;
 375 }
 376
 377 int board_eth_init(bd_t *bis)
 378 {
 379         setup_iomux_enet();
 380
 381         return cpu_eth_init(bis);
 382 }
 383
 384 #define BOARD_REV_B  0x200
 385 #define BOARD_REV_A  0x100
 386
 387 static int mx6sabre_rev(void)
 388 {
 389         /*
 390          * Get Board ID information from OCOTP_GP1[15:8]
 391          * i.MX6Q ARD RevA: 0x01
 392          * i.MX6Q ARD RevB: 0x02
 393          */
 394         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 395         struct fuse_bank *bank = &ocotp->bank[4];
 396         struct fuse_bank4_regs *fuse =
 397                         (struct fuse_bank4_regs *)bank->fuse_regs;
 398         int reg = readl(&fuse->gp1);
 399         int ret;
 400
 401         switch (reg >> 8 & 0x0F) {
 402         case 0x02:
 403                 ret = BOARD_REV_B;
 404                 break;
 405         case 0x01:
 406         default:
 407                 ret = BOARD_REV_A;
 408                 break;
 409         }
 410
 411         return ret;
 412 }
 413
 414 u32 get_board_rev(void)
 415 {
 416         int rev = mx6sabre_rev();
 417
 418         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 419 }
 420
 421 #if defined(CONFIG_VIDEO_IPUV3)
 422 static void do_enable_hdmi(struct display_info_t const *dev)
 423 {
 424         imx_enable_hdmi_phy();
 425 }
 426
 427 struct display_info_t const displays[] = {{
 428         .bus    = -1,
 429         .addr   = 0,
 430         .pixfmt = IPU_PIX_FMT_RGB24,
 431         .detect = detect_hdmi,
 432         .enable = do_enable_hdmi,
 433         .mode   = {
 434                 .name           = "HDMI",
 435                 .refresh        = 60,
 436                 .xres           = 1024,
 437                 .yres           = 768,
 438                 .pixclock       = 15385,
 439                 .left_margin    = 220,
 440                 .right_margin   = 40,
 441                 .upper_margin   = 21,
 442                 .lower_margin   = 7,
 443                 .hsync_len      = 60,
 444                 .vsync_len      = 10,
 445                 .sync           = FB_SYNC_EXT,
 446                 .vmode          = FB_VMODE_NONINTERLACED,
 447 } } };
 448 size_t display_count = ARRAY_SIZE(displays);
 449
 450 static void setup_display(void)
 451 {
 452         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 453         int reg;
 454
 455         enable_ipu_clock();
 456         imx_setup_hdmi();
 457
 458         reg = readl(&mxc_ccm->chsccdr);
 459         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 460                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 461         writel(reg, &mxc_ccm->chsccdr);
 462 }
 463 #endif /* CONFIG_VIDEO_IPUV3 */
 464
 465 /*
 466  * Do not overwrite the console
 467  * Use always serial for U-Boot console
 468  */
 469 int overwrite_console(void)
 470 {
 471         return 1;
 472 }
 473
 474 int board_early_init_f(void)
 475 {
 476         setup_iomux_uart();
 477 #ifdef CONFIG_VIDEO_IPUV3
 478         setup_display();
 479 #endif
 480
 481 #ifdef CONFIG_NAND_MXS
 482         setup_gpmi_nand();
 483 #endif
 484
 485         return 0;
 486 }
 487
 488 int board_init(void)
 489 {
 490         /* address of boot parameters */
 491         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 492
 493         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 494         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 495         /* I2C 3 Steer */
 496         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 497         imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 498 #ifndef CONFIG_SYS_FLASH_CFI
 499         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 500 #endif
 501         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 502         imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
 503
 504         setup_iomux_eimnor();
 505         return 0;
 506 }
 507
 508 #ifdef CONFIG_MXC_SPI
 509 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 510 {
 511         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 512 }
 513 #endif
 514
 515 int power_init_board(void)
 516 {
 517         struct pmic *p;
 518
 519         p = pfuze_common_init(I2C_PMIC);
 520         if (!p)
 521                 return -ENODEV;
 522
 523         return 0;
 524 }
 525
 526 #ifdef CONFIG_CMD_BMODE
 527 static const struct boot_mode board_boot_modes[] = {
 528         /* 4 bit bus width */
 529         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 530         {NULL,   0},
 531 };
 532 #endif
 533
 534 int board_late_init(void)
 535 {
 536 #ifdef CONFIG_CMD_BMODE
 537         add_board_boot_modes(board_boot_modes);
 538 #endif
 539
 540         return 0;
 541 }
 542
 543 int checkboard(void)
 544 {
 545         int rev = mx6sabre_rev();
 546         char *revname;
 547
 548         switch (rev) {
 549         case BOARD_REV_B:
 550                 revname = "B";
 551                 break;
 552         case BOARD_REV_A:
 553         default:
 554                 revname = "A";
 555                 break;
 556         }
 557
 558         printf("Board: MX6Q-Sabreauto rev%s\n", revname);
 559
 560         return 0;
 561 }
 562
 563 #ifdef CONFIG_USB_EHCI_MX6
 564 #define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
 565 #define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
 566
 567 iomux_v3_cfg_t const usb_otg_pads[] = {
 568         MX6_PAD_ENET_RX_ER__USB_OTG_ID,
 569 };
 570
 571 int board_ehci_hcd_init(int port)
 572 {
 573         switch (port) {
 574         case 0:
 575                 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 576                         ARRAY_SIZE(usb_otg_pads));
 577
 578                 /*
 579                   * Set daisy chain for otg_pin_id on 6q.
 580                  *  For 6dl, this bit is reserved.
 581                  */
 582                 imx_iomux_set_gpr_register(1, 13, 1, 0);
 583                 break;
 584         case 1:
 585                 break;
 586         default:
 587                 printf("MXC USB port %d not yet supported\n", port);
 588                 return -EINVAL;
 589         }
 590         return 0;
 591 }
 592
 593 int board_ehci_power(int port, int on)
 594 {
 595         switch (port) {
 596         case 0:
 597                 if (on)
 598                         port_exp_direction_output(USB_OTG_PWR, 1);
 599                 else
 600                         port_exp_direction_output(USB_OTG_PWR, 0);
 601                 break;
 602         case 1:
 603                 if (on)
 604                         port_exp_direction_output(USB_HOST1_PWR, 1);
 605                 else
 606                         port_exp_direction_output(USB_HOST1_PWR, 0);
 607                 break;
 608         default:
 609                 printf("MXC USB port %d not yet supported\n", port);
 610                 return -EINVAL;
 611         }
 612
 613         return 0;
 614 }
 615 #endif