board/freescale/mx6qsabrelite/mx6qsabrelite.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/arch/mx6q_pins.h>
  29 #include <asm/errno.h>
  30 #include <asm/gpio.h>
  31 #include <asm/imx-common/iomux-v3.h>
  32 #include <asm/imx-common/mxc_i2c.h>
  33 #include <asm/imx-common/boot_mode.h>
  34 #include <mmc.h>
  35 #include <fsl_esdhc.h>
  36 #include <malloc.h>
  37 #include <micrel.h>
  38 #include <miiphy.h>
  39 #include <netdev.h>
  40 #include <linux/fb.h>
  41 #include <ipu_pixfmt.h>
  42 #include <asm/arch/crm_regs.h>
  43 #include <asm/arch/mxc_hdmi.h>
  44 #include <i2c.h>
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  53         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  54         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  60         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  61
  62 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  64
  65 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  66         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  67         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  72
  73         return 0;
  74 }
  75
  76 iomux_v3_cfg_t const uart1_pads[] = {
  77         MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  79 };
  80
  81 iomux_v3_cfg_t const uart2_pads[] = {
  82         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  84 };
  85
  86 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  87
  88 /* I2C1, SGTL5000 */
  89 struct i2c_pads_info i2c_pad_info0 = {
  90         .scl = {
  91                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  92                 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
  93                 .gp = IMX_GPIO_NR(3, 21)
  94         },
  95         .sda = {
  96                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  97                 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
  98                 .gp = IMX_GPIO_NR(3, 28)
  99         }
 100 };
 101
 102 /* I2C2 Camera, MIPI */
 103 struct i2c_pads_info i2c_pad_info1 = {
 104         .scl = {
 105                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 106                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
 107                 .gp = IMX_GPIO_NR(4, 12)
 108         },
 109         .sda = {
 110                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 111                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
 112                 .gp = IMX_GPIO_NR(4, 13)
 113         }
 114 };
 115
 116 /* I2C3, J15 - RGB connector */
 117 struct i2c_pads_info i2c_pad_info2 = {
 118         .scl = {
 119                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 120                 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
 121                 .gp = IMX_GPIO_NR(1, 5)
 122         },
 123         .sda = {
 124                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 125                 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
 126                 .gp = IMX_GPIO_NR(7, 11)
 127         }
 128 };
 129
 130 iomux_v3_cfg_t const usdhc3_pads[] = {
 131         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 138 };
 139
 140 iomux_v3_cfg_t const usdhc4_pads[] = {
 141         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 148 };
 149
 150 iomux_v3_cfg_t const enet_pads1[] = {
 151         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 152         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 153         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 154         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 155         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 157         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 158         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         /* pin 35 - 1 (PHY_AD2) on reset */
 161         MX6_PAD_RGMII_RXC__GPIO_6_30            | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         /* pin 32 - 1 - (MODE0) all */
 163         MX6_PAD_RGMII_RD0__GPIO_6_25            | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         /* pin 31 - 1 - (MODE1) all */
 165         MX6_PAD_RGMII_RD1__GPIO_6_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         /* pin 28 - 1 - (MODE2) all */
 167         MX6_PAD_RGMII_RD2__GPIO_6_28            | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         /* pin 27 - 1 - (MODE3) all */
 169         MX6_PAD_RGMII_RD3__GPIO_6_29            | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 171         MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         /* pin 42 PHY nRST */
 173         MX6_PAD_EIM_D23__GPIO_3_23              | MUX_PAD_CTRL(NO_PAD_CTRL),
 174 };
 175
 176 iomux_v3_cfg_t const enet_pads2[] = {
 177         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 179         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 180         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 181         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 182         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 183 };
 184
 185 /* Button assignments for J14 */
 186 static iomux_v3_cfg_t const button_pads[] = {
 187         /* Menu */
 188         MX6_PAD_NANDF_D1__GPIO_2_1      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 189         /* Back */
 190         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 191         /* Labelled Search (mapped to Power under Android) */
 192         MX6_PAD_NANDF_D3__GPIO_2_3      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 193         /* Home */
 194         MX6_PAD_NANDF_D4__GPIO_2_4      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 195         /* Volume Down */
 196         MX6_PAD_GPIO_19__GPIO_4_5       | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 197         /* Volume Up */
 198         MX6_PAD_GPIO_18__GPIO_7_13      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 199 };
 200
 201 static void setup_iomux_enet(void)
 202 {
 203         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 204         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 205         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 206         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 207         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 208         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 209         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 210         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 211
 212         /* Need delay 10ms according to KSZ9021 spec */
 213         udelay(1000 * 10);
 214         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 215
 216         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 217 }
 218
 219 iomux_v3_cfg_t const usb_pads[] = {
 220         MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 221 };
 222
 223 static void setup_iomux_uart(void)
 224 {
 225         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 226         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 227 }
 228
 229 #ifdef CONFIG_USB_EHCI_MX6
 230 int board_ehci_hcd_init(int port)
 231 {
 232         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 233
 234         /* Reset USB hub */
 235         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 236         mdelay(2);
 237         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 238
 239         return 0;
 240 }
 241 #endif
 242
 243 #ifdef CONFIG_FSL_ESDHC
 244 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 245         {USDHC3_BASE_ADDR},
 246         {USDHC4_BASE_ADDR},
 247 };
 248
 249 int board_mmc_getcd(struct mmc *mmc)
 250 {
 251         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 252         int ret;
 253
 254         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 255                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 256                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 257         } else {
 258                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 259                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 260         }
 261
 262         return ret;
 263 }
 264
 265 int board_mmc_init(bd_t *bis)
 266 {
 267         s32 status = 0;
 268         u32 index = 0;
 269
 270         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 271         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 272
 273         usdhc_cfg[0].max_bus_width = 4;
 274         usdhc_cfg[1].max_bus_width = 4;
 275
 276         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 277                 switch (index) {
 278                 case 0:
 279                         imx_iomux_v3_setup_multiple_pads(
 280                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 281                         break;
 282                 case 1:
 283                         imx_iomux_v3_setup_multiple_pads(
 284                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 285                        break;
 286                default:
 287                         printf("Warning: you configured more USDHC controllers"
 288                                "(%d) then supported by the board (%d)\n",
 289                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 290                         return status;
 291                 }
 292
 293                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 294         }
 295
 296         return status;
 297 }
 298 #endif
 299
 300 #ifdef CONFIG_MXC_SPI
 301 iomux_v3_cfg_t const ecspi1_pads[] = {
 302         /* SS1 */
 303         MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 304         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 305         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 306         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 307 };
 308
 309 void setup_spi(void)
 310 {
 311         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 312                                          ARRAY_SIZE(ecspi1_pads));
 313 }
 314 #endif
 315
 316 int board_phy_config(struct phy_device *phydev)
 317 {
 318         /* min rx data delay */
 319         ksz9021_phy_extended_write(phydev,
 320                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 321         /* min tx data delay */
 322         ksz9021_phy_extended_write(phydev,
 323                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 324         /* max rx/tx clock delay, min rx/tx control */
 325         ksz9021_phy_extended_write(phydev,
 326                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 327         if (phydev->drv->config)
 328                 phydev->drv->config(phydev);
 329
 330         return 0;
 331 }
 332
 333 int board_eth_init(bd_t *bis)
 334 {
 335         uint32_t base = IMX_FEC_BASE;
 336         struct mii_dev *bus = NULL;
 337         struct phy_device *phydev = NULL;
 338         int ret;
 339
 340         setup_iomux_enet();
 341
 342 #ifdef CONFIG_FEC_MXC
 343         bus = fec_get_miibus(base, -1);
 344         if (!bus)
 345                 return 0;
 346         /* scan phy 4,5,6,7 */
 347         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 348         if (!phydev) {
 349                 free(bus);
 350                 return 0;
 351         }
 352         printf("using phy at %d\n", phydev->addr);
 353         ret  = fec_probe(bis, -1, base, bus, phydev);
 354         if (ret) {
 355                 printf("FEC MXC: %s:failed\n", __func__);
 356                 free(phydev);
 357                 free(bus);
 358         }
 359 #endif
 360         return 0;
 361 }
 362
 363 static void setup_buttons(void)
 364 {
 365         imx_iomux_v3_setup_multiple_pads(button_pads,
 366                                          ARRAY_SIZE(button_pads));
 367 }
 368
 369 #ifdef CONFIG_CMD_SATA
 370
 371 int setup_sata(void)
 372 {
 373         struct iomuxc_base_regs *const iomuxc_regs
 374                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 375         int ret = enable_sata_clock();
 376         if (ret)
 377                 return ret;
 378
 379         clrsetbits_le32(&iomuxc_regs->gpr[13],
 380                         IOMUXC_GPR13_SATA_MASK,
 381                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 382                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 383                         |IOMUXC_GPR13_SATA_SPEED_3G
 384                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 385                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 386                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 387                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 388                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 389                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 390
 391         return 0;
 392 }
 393 #endif
 394
 395 #if defined(CONFIG_VIDEO_IPUV3)
 396
 397 static iomux_v3_cfg_t const backlight_pads[] = {
 398         /* Backlight on RGB connector: J15 */
 399         MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 400 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 401
 402         /* Backlight on LVDS connector: J6 */
 403         MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 404 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 405 };
 406
 407 static iomux_v3_cfg_t const rgb_pads[] = {
 408         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 409         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 410         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 411         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 412         MX6_PAD_DI0_PIN4__GPIO_4_20,
 413         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 414         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 415         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 416         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 417         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 418         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 419         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 420         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 421         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 422         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 423         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 424         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 425         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 426         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 427         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 428         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 429         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 430         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 431         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 432         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 433         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 434         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 435         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 436         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 437 };
 438
 439 struct display_info_t {
 440         int     bus;
 441         int     addr;
 442         int     pixfmt;
 443         int     (*detect)(struct display_info_t const *dev);
 444         void    (*enable)(struct display_info_t const *dev);
 445         struct  fb_videomode mode;
 446 };
 447
 448
 449 static int detect_hdmi(struct display_info_t const *dev)
 450 {
 451         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 452         return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
 453 }
 454
 455 static void enable_hdmi(struct display_info_t const *dev)
 456 {
 457         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 458         u8 reg;
 459         printf("%s: setup HDMI monitor\n", __func__);
 460         reg = readb(&hdmi->phy_conf0);
 461         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 462         writeb(reg, &hdmi->phy_conf0);
 463
 464         udelay(3000);
 465         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 466         writeb(reg, &hdmi->phy_conf0);
 467         udelay(3000);
 468         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 469         writeb(reg, &hdmi->phy_conf0);
 470         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 471 }
 472
 473 static int detect_i2c(struct display_info_t const *dev)
 474 {
 475         return ((0 == i2c_set_bus_num(dev->bus))
 476                 &&
 477                 (0 == i2c_probe(dev->addr)));
 478 }
 479
 480 static void enable_lvds(struct display_info_t const *dev)
 481 {
 482         struct iomuxc *iomux = (struct iomuxc *)
 483                                 IOMUXC_BASE_ADDR;
 484         u32 reg = readl(&iomux->gpr[2]);
 485         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 486         writel(reg, &iomux->gpr[2]);
 487         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 488 }
 489
 490 static void enable_rgb(struct display_info_t const *dev)
 491 {
 492         imx_iomux_v3_setup_multiple_pads(
 493                 rgb_pads,
 494                  ARRAY_SIZE(rgb_pads));
 495         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 496 }
 497
 498 static struct display_info_t const displays[] = {{
 499         .bus    = -1,
 500         .addr   = 0,
 501         .pixfmt = IPU_PIX_FMT_RGB24,
 502         .detect = detect_hdmi,
 503         .enable = enable_hdmi,
 504         .mode   = {
 505                 .name           = "HDMI",
 506                 .refresh        = 60,
 507                 .xres           = 1024,
 508                 .yres           = 768,
 509                 .pixclock       = 15385,
 510                 .left_margin    = 220,
 511                 .right_margin   = 40,
 512                 .upper_margin   = 21,
 513                 .lower_margin   = 7,
 514                 .hsync_len      = 60,
 515                 .vsync_len      = 10,
 516                 .sync           = FB_SYNC_EXT,
 517                 .vmode          = FB_VMODE_NONINTERLACED
 518 } }, {
 519         .bus    = 2,
 520         .addr   = 0x4,
 521         .pixfmt = IPU_PIX_FMT_LVDS666,
 522         .detect = detect_i2c,
 523         .enable = enable_lvds,
 524         .mode   = {
 525                 .name           = "Hannstar-XGA",
 526                 .refresh        = 60,
 527                 .xres           = 1024,
 528                 .yres           = 768,
 529                 .pixclock       = 15385,
 530                 .left_margin    = 220,
 531                 .right_margin   = 40,
 532                 .upper_margin   = 21,
 533                 .lower_margin   = 7,
 534                 .hsync_len      = 60,
 535                 .vsync_len      = 10,
 536                 .sync           = FB_SYNC_EXT,
 537                 .vmode          = FB_VMODE_NONINTERLACED
 538 } }, {
 539         .bus    = 2,
 540         .addr   = 0x38,
 541         .pixfmt = IPU_PIX_FMT_LVDS666,
 542         .detect = detect_i2c,
 543         .enable = enable_lvds,
 544         .mode   = {
 545                 .name           = "wsvga-lvds",
 546                 .refresh        = 60,
 547                 .xres           = 1024,
 548                 .yres           = 600,
 549                 .pixclock       = 15385,
 550                 .left_margin    = 220,
 551                 .right_margin   = 40,
 552                 .upper_margin   = 21,
 553                 .lower_margin   = 7,
 554                 .hsync_len      = 60,
 555                 .vsync_len      = 10,
 556                 .sync           = FB_SYNC_EXT,
 557                 .vmode          = FB_VMODE_NONINTERLACED
 558 } }, {
 559         .bus    = 2,
 560         .addr   = 0x48,
 561         .pixfmt = IPU_PIX_FMT_RGB666,
 562         .detect = detect_i2c,
 563         .enable = enable_rgb,
 564         .mode   = {
 565                 .name           = "wvga-rgb",
 566                 .refresh        = 57,
 567                 .xres           = 800,
 568                 .yres           = 480,
 569                 .pixclock       = 37037,
 570                 .left_margin    = 40,
 571                 .right_margin   = 60,
 572                 .upper_margin   = 10,
 573                 .lower_margin   = 10,
 574                 .hsync_len      = 20,
 575                 .vsync_len      = 10,
 576                 .sync           = 0,
 577                 .vmode          = FB_VMODE_NONINTERLACED
 578 } } };
 579
 580 int board_video_skip(void)
 581 {
 582         int i;
 583         int ret;
 584         char const *panel = getenv("panel");
 585         if (!panel) {
 586                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 587                         struct display_info_t const *dev = displays+i;
 588                         if (dev->detect(dev)) {
 589                                 panel = dev->mode.name;
 590                                 printf("auto-detected panel %s\n", panel);
 591                                 break;
 592                         }
 593                 }
 594                 if (!panel) {
 595                         panel = displays[0].mode.name;
 596                         printf("No panel detected: default to %s\n", panel);
 597                 }
 598         } else {
 599                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 600                         if (!strcmp(panel, displays[i].mode.name))
 601                                 break;
 602                 }
 603         }
 604         if (i < ARRAY_SIZE(displays)) {
 605                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 606                                     displays[i].pixfmt);
 607                 if (!ret) {
 608                         displays[i].enable(displays+i);
 609                         printf("Display: %s (%ux%u)\n",
 610                                displays[i].mode.name,
 611                                displays[i].mode.xres,
 612                                displays[i].mode.yres);
 613                 } else
 614                         printf("LCD %s cannot be configured: %d\n",
 615                                displays[i].mode.name, ret);
 616         } else {
 617                 printf("unsupported panel %s\n", panel);
 618                 ret = -EINVAL;
 619         }
 620         return (0 != ret);
 621 }
 622
 623 static void setup_display(void)
 624 {
 625         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 626         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 627         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 628         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 629
 630         int reg;
 631
 632         /* Turn on LDB0,IPU,IPU DI0 clocks */
 633         reg = __raw_readl(&mxc_ccm->CCGR3);
 634         reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
 635                 |MXC_CCM_CCGR3_LDB_DI0_MASK;
 636         writel(reg, &mxc_ccm->CCGR3);
 637
 638         /* Turn on HDMI PHY clock */
 639         reg = __raw_readl(&mxc_ccm->CCGR2);
 640         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
 641                |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 642         writel(reg, &mxc_ccm->CCGR2);
 643
 644         /* clear HDMI PHY reset */
 645         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 646
 647         /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 648         writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 649         writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
 650
 651         /* set LDB0, LDB1 clk select to 011/011 */
 652         reg = readl(&mxc_ccm->cs2cdr);
 653         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 654                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 655         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 656               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 657         writel(reg, &mxc_ccm->cs2cdr);
 658
 659         reg = readl(&mxc_ccm->cscmr2);
 660         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 661         writel(reg, &mxc_ccm->cscmr2);
 662
 663         reg = readl(&mxc_ccm->chsccdr);
 664         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
 665                 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
 666                 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 667         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 668                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 669               |(CHSCCDR_PODF_DIVIDE_BY_3
 670                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 671               |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 672                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 673         writel(reg, &mxc_ccm->chsccdr);
 674
 675         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 676              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 677              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 678              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 679              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 680              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 681              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 682              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 683              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 684         writel(reg, &iomux->gpr[2]);
 685
 686         reg = readl(&iomux->gpr[3]);
 687         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 688             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 689                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 690         writel(reg, &iomux->gpr[3]);
 691
 692         /* backlights off until needed */
 693         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 694                                          ARRAY_SIZE(backlight_pads));
 695         gpio_direction_input(LVDS_BACKLIGHT_GP);
 696         gpio_direction_input(RGB_BACKLIGHT_GP);
 697 }
 698 #endif
 699
 700 int board_early_init_f(void)
 701 {
 702         setup_iomux_uart();
 703         setup_buttons();
 704
 705 #if defined(CONFIG_VIDEO_IPUV3)
 706         setup_display();
 707 #endif
 708         return 0;
 709 }
 710
 711 /*
 712  * Do not overwrite the console
 713  * Use always serial for U-Boot console
 714  */
 715 int overwrite_console(void)
 716 {
 717         return 1;
 718 }
 719
 720 int board_init(void)
 721 {
 722         /* address of boot parameters */
 723         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 724
 725 #ifdef CONFIG_MXC_SPI
 726         setup_spi();
 727 #endif
 728         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 729         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 730         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 731
 732 #ifdef CONFIG_CMD_SATA
 733         setup_sata();
 734 #endif
 735
 736         return 0;
 737 }
 738
 739 int checkboard(void)
 740 {
 741         puts("Board: MX6Q-Sabre Lite\n");
 742
 743         return 0;
 744 }
 745
 746 struct button_key {
 747         char const      *name;
 748         unsigned        gpnum;
 749         char            ident;
 750 };
 751
 752 static struct button_key const buttons[] = {
 753         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 754         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 755         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 756         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 757         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 758         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 759 };
 760
 761 /*
 762  * generate a null-terminated string containing the buttons pressed
 763  * returns number of keys pressed
 764  */
 765 static int read_keys(char *buf)
 766 {
 767         int i, numpressed = 0;
 768         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 769                 if (!gpio_get_value(buttons[i].gpnum))
 770                         buf[numpressed++] = buttons[i].ident;
 771         }
 772         buf[numpressed] = '\0';
 773         return numpressed;
 774 }
 775
 776 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 777 {
 778         char envvalue[ARRAY_SIZE(buttons)+1];
 779         int numpressed = read_keys(envvalue);
 780         setenv("keybd", envvalue);
 781         return numpressed == 0;
 782 }
 783
 784 U_BOOT_CMD(
 785         kbd, 1, 1, do_kbd,
 786         "Tests for keypresses, sets 'keybd' environment variable",
 787         "Returns 0 (true) to shell if key is pressed."
 788 );
 789
 790 #ifdef CONFIG_PREBOOT
 791 static char const kbd_magic_prefix[] = "key_magic";
 792 static char const kbd_command_prefix[] = "key_cmd";
 793
 794 static void preboot_keys(void)
 795 {
 796         int numpressed;
 797         char keypress[ARRAY_SIZE(buttons)+1];
 798         numpressed = read_keys(keypress);
 799         if (numpressed) {
 800                 char *kbd_magic_keys = getenv("magic_keys");
 801                 char *suffix;
 802                 /*
 803                  * loop over all magic keys
 804                  */
 805                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 806                         char *keys;
 807                         char magic[sizeof(kbd_magic_prefix) + 1];
 808                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 809                         keys = getenv(magic);
 810                         if (keys) {
 811                                 if (!strcmp(keys, keypress))
 812                                         break;
 813                         }
 814                 }
 815                 if (*suffix) {
 816                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 817                         char *cmd;
 818                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 819                         cmd = getenv(cmd_name);
 820                         if (cmd) {
 821                                 setenv("preboot", cmd);
 822                                 return;
 823                         }
 824                 }
 825         }
 826 }
 827 #endif
 828
 829 #ifdef CONFIG_CMD_BMODE
 830 static const struct boot_mode board_boot_modes[] = {
 831         /* 4 bit bus width */
 832         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 833         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 834         {NULL,          0},
 835 };
 836 #endif
 837
 838 int misc_init_r(void)
 839 {
 840 #ifdef CONFIG_PREBOOT
 841         preboot_keys();
 842 #endif
 843
 844 #ifdef CONFIG_CMD_BMODE
 845         add_board_boot_modes(board_boot_modes);
 846 #endif
 847         return 0;
 848 }