Merge branch 'master' of git://git.denx.de/u-boot-usb
[karo-tx-uboot.git] / board / freescale / mx6sxsabresd / mx6sxsabresd.c
1 /*
2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
3  *
4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/io.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <linux/sizes.h>
20 #include <common.h>
21 #include <fsl_esdhc.h>
22 #include <mmc.h>
23 #include <i2c.h>
24 #include <miiphy.h>
25 #include <netdev.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
28 #include "../common/pfuze.h"
29 #include <usb.h>
30 #include <usb/ehci-fsl.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
35         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
36         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
37
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
39         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
40         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
41
42 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
43         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
44         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
45         PAD_CTL_ODE)
46
47 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
48         PAD_CTL_SPEED_HIGH   |                                   \
49         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
50
51 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
52         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
53
54 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
55         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
56
57 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
58         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
59         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
60         PAD_CTL_ODE)
61
62 int dram_init(void)
63 {
64         gd->ram_size = PHYS_SDRAM_SIZE;
65
66         return 0;
67 }
68
69 static iomux_v3_cfg_t const uart1_pads[] = {
70         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
71         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
72 };
73
74 static iomux_v3_cfg_t const usdhc2_pads[] = {
75         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 };
82
83 static iomux_v3_cfg_t const usdhc3_pads[] = {
84         MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85         MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86         MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87         MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88         MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89         MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90         MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91         MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92         MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93         MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94
95         /* CD pin */
96         MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
97
98         /* RST_B, used for power reset cycle */
99         MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
100 };
101
102 static iomux_v3_cfg_t const usdhc4_pads[] = {
103         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109         MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
110 };
111
112 static iomux_v3_cfg_t const fec1_pads[] = {
113         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
114         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
115         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
116         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
117         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
118         MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
119         MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
120         MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
121         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
122         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124         MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
125         MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
126         MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
127 };
128
129 static iomux_v3_cfg_t const peri_3v3_pads[] = {
130         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
131 };
132
133 static iomux_v3_cfg_t const phy_control_pads[] = {
134         /* 25MHz Ethernet PHY Clock */
135         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
136
137         /* ENET PHY Power */
138         MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
139
140         /* AR8031 PHY Reset */
141         MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
142 };
143
144 static void setup_iomux_uart(void)
145 {
146         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
147 }
148
149 static int setup_fec(void)
150 {
151         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
152         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
153         int reg;
154
155         /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
156         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
157
158         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
159                                          ARRAY_SIZE(phy_control_pads));
160
161         /* Enable the ENET power, active low */
162         gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
163
164         /* Reset AR8031 PHY */
165         gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
166         udelay(500);
167         gpio_set_value(IMX_GPIO_NR(2, 7), 1);
168
169         reg = readl(&anatop->pll_enet);
170         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
171         writel(reg, &anatop->pll_enet);
172
173         return enable_fec_anatop_clock(ENET_125MHZ);
174 }
175
176 int board_eth_init(bd_t *bis)
177 {
178         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
179         setup_fec();
180
181         return cpu_eth_init(bis);
182 }
183
184 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
185 /* I2C1 for PMIC */
186 static struct i2c_pads_info i2c_pad_info1 = {
187         .scl = {
188                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
189                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
190                 .gp = IMX_GPIO_NR(1, 0),
191         },
192         .sda = {
193                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
194                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
195                 .gp = IMX_GPIO_NR(1, 1),
196         },
197 };
198
199 int power_init_board(void)
200 {
201         struct pmic *p;
202         unsigned int reg;
203
204         p = pfuze_common_init(I2C_PMIC);
205         if (!p)
206                 return -ENODEV;
207
208         /* Enable power of VGEN5 3V3, needed for SD3 */
209         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
210         reg &= ~LDO_VOL_MASK;
211         reg |= (LDOB_3_30V | (1 << LDO_EN));
212         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
213
214         return 0;
215 }
216
217 #ifdef CONFIG_USB_EHCI_MX6
218 #define USB_OTHERREGS_OFFSET    0x800
219 #define UCTRL_PWR_POL           (1 << 9)
220
221 static iomux_v3_cfg_t const usb_otg_pads[] = {
222         /* OGT1 */
223         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
224         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
225         /* OTG2 */
226         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
227 };
228
229 static void setup_usb(void)
230 {
231         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
232                                          ARRAY_SIZE(usb_otg_pads));
233 }
234
235 int board_usb_phy_mode(int port)
236 {
237         if (port == 1)
238                 return USB_INIT_HOST;
239         else
240                 return usb_phy_mode(port);
241 }
242
243 int board_ehci_hcd_init(int port)
244 {
245         u32 *usbnc_usb_ctrl;
246
247         if (port > 1)
248                 return -EINVAL;
249
250         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
251                                  port * 4);
252
253         /* Set Power polarity */
254         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
255
256         return 0;
257 }
258 #endif
259
260 int board_phy_config(struct phy_device *phydev)
261 {
262         /*
263          * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
264          * Phy control debug reg 0
265          */
266         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
267         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
268
269         /* rgmii tx clock delay enable */
270         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
271         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
272
273         if (phydev->drv->config)
274                 phydev->drv->config(phydev);
275
276         return 0;
277 }
278
279 int board_early_init_f(void)
280 {
281         setup_iomux_uart();
282
283         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
284         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
285                                          ARRAY_SIZE(peri_3v3_pads));
286
287         /* Active high for ncp692 */
288         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
289
290 #ifdef CONFIG_USB_EHCI_MX6
291         setup_usb();
292 #endif
293
294         return 0;
295 }
296
297 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
298         {USDHC2_BASE_ADDR, 0, 4},
299         {USDHC3_BASE_ADDR},
300         {USDHC4_BASE_ADDR},
301 };
302
303 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 10)
304 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
305 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 21)
306
307 int board_mmc_getcd(struct mmc *mmc)
308 {
309         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
310         int ret = 0;
311
312         switch (cfg->esdhc_base) {
313         case USDHC2_BASE_ADDR:
314                 ret = 1; /* Assume uSDHC2 is always present */
315                 break;
316         case USDHC3_BASE_ADDR:
317                 ret = !gpio_get_value(USDHC3_CD_GPIO);
318                 break;
319         case USDHC4_BASE_ADDR:
320                 ret = !gpio_get_value(USDHC4_CD_GPIO);
321                 break;
322         }
323
324         return ret;
325 }
326
327 int board_mmc_init(bd_t *bis)
328 {
329         int i, ret;
330
331         /*
332          * According to the board_mmc_init() the following map is done:
333          * (U-boot device node)    (Physical Port)
334          * mmc0                    USDHC2
335          * mmc1                    USDHC3
336          * mmc2                    USDHC4
337          */
338         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
339                 switch (i) {
340                 case 0:
341                         imx_iomux_v3_setup_multiple_pads(
342                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
343                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
344                         break;
345                 case 1:
346                         imx_iomux_v3_setup_multiple_pads(
347                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
348                         gpio_direction_input(USDHC3_CD_GPIO);
349                         gpio_direction_output(USDHC3_PWR_GPIO, 1);
350                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
351                         break;
352                 case 2:
353                         imx_iomux_v3_setup_multiple_pads(
354                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
355                         gpio_direction_input(USDHC4_CD_GPIO);
356                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
357                         break;
358                 default:
359                         printf("Warning: you configured more USDHC controllers"
360                                 "(%d) than supported by the board\n", i + 1);
361                         return -EINVAL;
362                         }
363
364                         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
365                         if (ret) {
366                                 printf("Warning: failed to initialize mmc dev %d\n", i);
367                                 return ret;
368                         }
369         }
370
371         return 0;
372 }
373
374 int board_init(void)
375 {
376         /* Address of boot parameters */
377         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
378
379 #ifdef CONFIG_SYS_I2C_MXC
380         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
381 #endif
382
383         return 0;
384 }
385
386 int board_late_init(void)
387 {
388         return 0;
389 }
390
391 int checkboard(void)
392 {
393         puts("Board: MX6SX SABRE SDB\n");
394
395         return 0;
396 }