board/freescale/mx6sxsabresd/mx6sxsabresd.c

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/io.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <linux/sizes.h>
  20 #include <common.h>
  21 #include <fsl_esdhc.h>
  22 #include <mmc.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze100_pmic.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  32         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  33         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  34
  35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  36         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  37         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  40         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  41         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  42         PAD_CTL_ODE)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  45         PAD_CTL_SPEED_HIGH   |                                   \
  46         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  47
  48 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  49         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  50
  51 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  52         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  53
  54 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  55         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  56         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  57         PAD_CTL_ODE)
  58
  59 int dram_init(void)
  60 {
  61         gd->ram_size = PHYS_SDRAM_SIZE;
  62
  63         return 0;
  64 }
  65
  66 static iomux_v3_cfg_t const uart1_pads[] = {
  67         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  68         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  69 };
  70
  71 static iomux_v3_cfg_t const usdhc2_pads[] = {
  72         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78 };
  79
  80 static iomux_v3_cfg_t const usdhc3_pads[] = {
  81         MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91
  92         /* CD pin */
  93         MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  94
  95         /* RST_B, used for power reset cycle */
  96         MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  97 };
  98
  99 static iomux_v3_cfg_t const usdhc4_pads[] = {
 100         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 107 };
 108
 109 static iomux_v3_cfg_t const fec1_pads[] = {
 110         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 113         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 114         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 115         MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 116         MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 117         MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 118         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124 };
 125
 126 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 127         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 128 };
 129
 130 static iomux_v3_cfg_t const phy_control_pads[] = {
 131         /* 25MHz Ethernet PHY Clock */
 132         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 133
 134         /* ENET PHY Power */
 135         MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
 136
 137         /* AR8031 PHY Reset */
 138         MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
 139 };
 140
 141 static void setup_iomux_uart(void)
 142 {
 143         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 144 }
 145
 146 static int setup_fec(void)
 147 {
 148         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 149         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 150         int reg;
 151
 152         /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
 153         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 154
 155         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 156                                          ARRAY_SIZE(phy_control_pads));
 157
 158         /* Enable the ENET power, active low */
 159         gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
 160
 161         /* Reset AR8031 PHY */
 162         gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
 163         udelay(500);
 164         gpio_set_value(IMX_GPIO_NR(2, 7), 1);
 165
 166         reg = readl(&anatop->pll_enet);
 167         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 168         writel(reg, &anatop->pll_enet);
 169
 170         return enable_fec_anatop_clock(ENET_125MHz);
 171 }
 172
 173 int board_eth_init(bd_t *bis)
 174 {
 175         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 176         setup_fec();
 177
 178         return cpu_eth_init(bis);
 179 }
 180
 181 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 182 /* I2C1 for PMIC */
 183 static struct i2c_pads_info i2c_pad_info1 = {
 184         .scl = {
 185                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
 186                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
 187                 .gp = IMX_GPIO_NR(1, 0),
 188         },
 189         .sda = {
 190                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
 191                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
 192                 .gp = IMX_GPIO_NR(1, 1),
 193         },
 194 };
 195
 196 static int pfuze_init(void)
 197 {
 198         struct pmic *p;
 199         int ret;
 200         unsigned int reg;
 201
 202         ret = power_pfuze100_init(I2C_PMIC);
 203         if (ret)
 204                 return ret;
 205
 206         p = pmic_get("PFUZE100");
 207         ret = pmic_probe(p);
 208         if (ret)
 209                 return ret;
 210
 211         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 212         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 213
 214         /* Set SW1AB standby voltage to 0.975V */
 215         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 216         reg &= ~0x3f;
 217         reg |= 0x1b;
 218         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 219
 220         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 221         pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
 222         reg &= ~0xc0;
 223         reg |= 0x40;
 224         pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
 225
 226         /* Set SW1C standby voltage to 0.975V */
 227         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 228         reg &= ~0x3f;
 229         reg |= 0x1b;
 230         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 231
 232         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 233         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 234         reg &= ~0xc0;
 235         reg |= 0x40;
 236         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 237
 238         /* Enable power of VGEN5 3V3, needed for SD3 */
 239         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 240         reg &= ~0x1F;
 241         reg |= 0x1F;
 242         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 243
 244         return 0;
 245 }
 246
 247 int board_phy_config(struct phy_device *phydev)
 248 {
 249         /*
 250          * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
 251          * Phy control debug reg 0
 252          */
 253         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 254         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 255
 256         /* rgmii tx clock delay enable */
 257         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 258         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 259
 260         if (phydev->drv->config)
 261                 phydev->drv->config(phydev);
 262
 263         return 0;
 264 }
 265
 266 int board_early_init_f(void)
 267 {
 268         setup_iomux_uart();
 269
 270         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 271         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 272                                          ARRAY_SIZE(peri_3v3_pads));
 273
 274         /* Active high for ncp692 */
 275         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 276
 277         return 0;
 278 }
 279
 280 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 281         {USDHC2_BASE_ADDR, 0, 4},
 282         {USDHC3_BASE_ADDR},
 283         {USDHC4_BASE_ADDR},
 284 };
 285
 286 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 10)
 287 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
 288 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 21)
 289
 290 int board_mmc_getcd(struct mmc *mmc)
 291 {
 292         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 293         int ret = 0;
 294
 295         switch (cfg->esdhc_base) {
 296         case USDHC2_BASE_ADDR:
 297                 ret = 1; /* Assume uSDHC2 is always present */
 298                 break;
 299         case USDHC3_BASE_ADDR:
 300                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 301                 break;
 302         case USDHC4_BASE_ADDR:
 303                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 304                 break;
 305         }
 306
 307         return ret;
 308 }
 309
 310 int board_mmc_init(bd_t *bis)
 311 {
 312         int i, ret;
 313
 314         /*
 315          * According to the board_mmc_init() the following map is done:
 316          * (U-boot device node)    (Physical Port)
 317          * mmc0                    USDHC2
 318          * mmc1                    USDHC3
 319          * mmc2                    USDHC4
 320          */
 321         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 322                 switch (i) {
 323                 case 0:
 324                         imx_iomux_v3_setup_multiple_pads(
 325                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 326                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 327                         break;
 328                 case 1:
 329                         imx_iomux_v3_setup_multiple_pads(
 330                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 331                         gpio_direction_input(USDHC3_CD_GPIO);
 332                         gpio_direction_output(USDHC3_PWR_GPIO, 1);
 333                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 334                         break;
 335                 case 2:
 336                         imx_iomux_v3_setup_multiple_pads(
 337                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 338                         gpio_direction_input(USDHC4_CD_GPIO);
 339                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 340                         break;
 341                 default:
 342                         printf("Warning: you configured more USDHC controllers"
 343                                 "(%d) than supported by the board\n", i + 1);
 344                         return -EINVAL;
 345                         }
 346
 347                         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 348                         if (ret) {
 349                                 printf("Warning: failed to initialize mmc dev %d\n", i);
 350                                 return ret;
 351                         }
 352         }
 353
 354         return 0;
 355 }
 356
 357
 358 int board_init(void)
 359 {
 360         /* Address of boot parameters */
 361         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 362
 363 #ifdef CONFIG_SYS_I2C_MXC
 364         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 365 #endif
 366
 367         return 0;
 368 }
 369
 370 int board_late_init(void)
 371 {
 372         pfuze_init();
 373
 374         return 0;
 375 }
 376
 377 int checkboard(void)
 378 {
 379         puts("Board: MX6SX SABRE SDB\n");
 380
 381         return 0;
 382 }