board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <asm/fsl_serdes.h>
  34 #include <miiphy.h>
  35 #include <libfdt.h>
  36 #include <fdt_support.h>
  37 #include <fsl_mdio.h>
  38 #include <tsec.h>
  39 #include <asm/fsl_law.h>
  40 #include <netdev.h>
  41
  42 #include "../common/ngpixis.h"
  43 #include "../common/sgmii_riser.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 int board_early_init_f(void)
  48 {
  49 #ifdef CONFIG_MMC
  50         ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  51
  52         setbits_be32(&gur->pmuxcr,
  53                          (MPC85xx_PMUXCR_SDHC_CD |
  54                          MPC85xx_PMUXCR_SDHC_WP));
  55 #endif
  56
  57         return 0;
  58 }
  59
  60 int checkboard(void)
  61 {
  62         u8 sw;
  63
  64         printf("Board: P2020DS Sys ID: 0x%02x, "
  65                "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  66                 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  67
  68         sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  69         sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  70
  71         if (sw < 0x8)
  72                 /* The lower two bits are the actual vbank number */
  73                 printf("vBank: %d\n", sw & 3);
  74         else
  75                 puts("Promjet\n");
  76
  77         return 0;
  78 }
  79
  80 #if !defined(CONFIG_DDR_SPD)
  81 /*
  82  * Fixed sdram init -- doesn't use serial presence detect.
  83  */
  84
  85 phys_size_t fixed_sdram(void)
  86 {
  87         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  88         uint d_init;
  89
  90         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  91         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  92         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  93         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  94         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  95         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
  96         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  97         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  98         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  99         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 100         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 101         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 102         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 103         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 104         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 105
 106         if (!strcmp("performance", getenv("perf_mode"))) {
 107                 /* Performance Mode Values */
 108
 109                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 110                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 111                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 112                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 113                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 114
 115                 asm("sync;isync");
 116
 117                 udelay(500);
 118
 119                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 120         } else {
 121                 /* Stable Mode Values */
 122
 123                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 124                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 125                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 126                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 127                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 128
 129                 /* ECC will be assumed in stable mode */
 130                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 131                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 132                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 133
 134                 asm("sync;isync");
 135
 136                 udelay(500);
 137
 138                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 139         }
 140
 141 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 142         d_init = 1;
 143         debug("DDR - 1st controller: memory initializing\n");
 144         /*
 145          * Poll until memory is initialized.
 146          * 512 Meg at 400 might hit this 200 times or so.
 147          */
 148         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 149                 udelay(1000);
 150         debug("DDR: memory initialized\n\n");
 151         asm("sync; isync");
 152         udelay(500);
 153 #endif
 154
 155         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 156                          CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
 157                          LAW_TRGT_IF_DDR) < 0) {
 158                 printf("ERROR setting Local Access Windows for DDR\n");
 159                 return 0;
 160         };
 161
 162         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 163 }
 164
 165 #endif
 166
 167 #ifdef CONFIG_PCI
 168 void pci_init_board(void)
 169 {
 170         fsl_pcie_init_board(0);
 171 }
 172 #endif
 173
 174 int board_early_init_r(void)
 175 {
 176         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 177         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 178
 179         /*
 180          * Remap Boot flash + PROMJET region to caching-inhibited
 181          * so that flash can be erased properly.
 182          */
 183
 184         /* Flush d-cache and invalidate i-cache of any FLASH data */
 185         flush_dcache();
 186         invalidate_icache();
 187
 188         /* invalidate existing TLB entry for flash + promjet */
 189         disable_tlb(flash_esel);
 190
 191         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 192                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 193                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 194
 195         return 0;
 196 }
 197
 198 #ifdef CONFIG_TSEC_ENET
 199 int board_eth_init(bd_t *bis)
 200 {
 201         struct fsl_pq_mdio_info mdio_info;
 202         struct tsec_info_struct tsec_info[4];
 203         int num = 0;
 204
 205 #ifdef CONFIG_TSEC1
 206         SET_STD_TSEC_INFO(tsec_info[num], 1);
 207         num++;
 208 #endif
 209 #ifdef CONFIG_TSEC2
 210         SET_STD_TSEC_INFO(tsec_info[num], 2);
 211         if (is_serdes_configured(SGMII_TSEC2)) {
 212                 puts("eTSEC2 is in sgmii mode.\n");
 213                 tsec_info[num].flags |= TSEC_SGMII;
 214         }
 215         num++;
 216 #endif
 217 #ifdef CONFIG_TSEC3
 218         SET_STD_TSEC_INFO(tsec_info[num], 3);
 219         if (is_serdes_configured(SGMII_TSEC3)) {
 220                 puts("eTSEC3 is in sgmii mode.\n");
 221                 tsec_info[num].flags |= TSEC_SGMII;
 222 }
 223         num++;
 224 #endif
 225
 226         if (!num) {
 227                 printf("No TSECs initialized\n");
 228
 229                 return 0;
 230         }
 231
 232 #ifdef CONFIG_FSL_SGMII_RISER
 233         fsl_sgmii_riser_init(tsec_info, num);
 234 #endif
 235
 236         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 237         mdio_info.name = DEFAULT_MII_NAME;
 238
 239         fsl_pq_mdio_init(bis, &mdio_info);
 240
 241         tsec_eth_init(bis, tsec_info, num);
 242
 243         return pci_eth_init(bis);
 244 }
 245 #endif
 246
 247 #if defined(CONFIG_OF_BOARD_SETUP)
 248 void ft_board_setup(void *blob, bd_t *bd)
 249 {
 250         phys_addr_t base;
 251         phys_size_t size;
 252
 253         ft_cpu_setup(blob, bd);
 254
 255         base = getenv_bootm_low();
 256         size = getenv_bootm_size();
 257
 258         fdt_fixup_memory(blob, (u64)base, (u64)size);
 259
 260 #ifdef CONFIG_HAS_FSL_DR_USB
 261         fdt_fixup_dr_usb(blob, bd);
 262 #endif
 263
 264         FT_FSL_PCI_SETUP;
 265
 266 #ifdef CONFIG_FSL_SGMII_RISER
 267         fsl_sgmii_riser_fdt_fixup(blob);
 268 #endif
 269 }
 270 #endif