board/freescale/p3060qds/fixed_ddr.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_ddr_sdram.h>
  11
  12 #define CONFIG_SYS_DDR_TIMING_3_1200    0x01030000
  13 #define CONFIG_SYS_DDR_TIMING_0_1200    0xCC550104
  14 #define CONFIG_SYS_DDR_TIMING_1_1200    0x868FAA45
  15 #define CONFIG_SYS_DDR_TIMING_2_1200    0x0FB8A912
  16 #define CONFIG_SYS_DDR_MODE_1_1200      0x00441A40
  17 #define CONFIG_SYS_DDR_MODE_2_1200      0x00100000
  18 #define CONFIG_SYS_DDR_INTERVAL_1200    0x12480100
  19 #define CONFIG_SYS_DDR_CLK_CTRL_1200    0x02800000
  20
  21 #define CONFIG_SYS_DDR_TIMING_3_1000    0x00020000
  22 #define CONFIG_SYS_DDR_TIMING_0_1000    0xCC440104
  23 #define CONFIG_SYS_DDR_TIMING_1_1000    0x727DF944
  24 #define CONFIG_SYS_DDR_TIMING_2_1000    0x0FB088CF
  25 #define CONFIG_SYS_DDR_MODE_1_1000      0x00441830
  26 #define CONFIG_SYS_DDR_MODE_2_1000      0x00080000
  27 #define CONFIG_SYS_DDR_INTERVAL_1000    0x0F3C0100
  28 #define CONFIG_SYS_DDR_CLK_CTRL_1000    0x02800000
  29
  30 #define CONFIG_SYS_DDR_TIMING_3_900     0x00020000
  31 #define CONFIG_SYS_DDR_TIMING_0_900     0xCC440104
  32 #define CONFIG_SYS_DDR_TIMING_1_900     0x616ba844
  33 #define CONFIG_SYS_DDR_TIMING_2_900     0x0fb088ce
  34 #define CONFIG_SYS_DDR_MODE_1_900       0x00441620
  35 #define CONFIG_SYS_DDR_MODE_2_900       0x00080000
  36 #define CONFIG_SYS_DDR_INTERVAL_900     0x0db60100
  37 #define CONFIG_SYS_DDR_CLK_CTRL_900     0x02800000
  38
  39 #define CONFIG_SYS_DDR_TIMING_3_800     0x00020000
  40 #define CONFIG_SYS_DDR_TIMING_0_800     0xcc330104
  41 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b4744
  42 #define CONFIG_SYS_DDR_TIMING_2_800     0x0fa888cc
  43 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
  44 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
  45 #define CONFIG_SYS_DDR_INTERVAL_800     0x0c300100
  46 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x02800000
  47
  48 #define CONFIG_SYS_DDR_CS0_BNDS         0x000000FF
  49 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
  50 #define CONFIG_SYS_DDR_CS2_BNDS         0x000000FF
  51 #define CONFIG_SYS_DDR_CS3_BNDS         0x000000FF
  52 #define CONFIG_SYS_DDR2_CS0_BNDS        0x000000FF
  53 #define CONFIG_SYS_DDR2_CS1_BNDS        0x00000000
  54 #define CONFIG_SYS_DDR2_CS2_BNDS        0x000000FF
  55 #define CONFIG_SYS_DDR2_CS3_BNDS        0x000000FF
  56 #define CONFIG_SYS_DDR_CS0_CONFIG       0xA0044202
  57 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
  58 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80004202
  59 #define CONFIG_SYS_DDR_CS2_CONFIG       0x00000000
  60 #define CONFIG_SYS_DDR_CS3_CONFIG       0x00000000
  61 #define CONFIG_SYS_DDR2_CS0_CONFIG      0x80044202
  62 #define CONFIG_SYS_DDR2_CS1_CONFIG      0x80004202
  63 #define CONFIG_SYS_DDR2_CS2_CONFIG      0x00000000
  64 #define CONFIG_SYS_DDR2_CS3_CONFIG      0x00000000
  65 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
  66 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
  67 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80004202
  68 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
  69 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
  70 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
  71 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
  72 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
  73 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8675F607
  74 #define CONFIG_SYS_DDR_SDRAM_CFG        0xE7044000
  75 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x24401031
  76 #define CONFIG_SYS_DDR_RCW_1            0x00000000
  77 #define CONFIG_SYS_DDR_RCW_2            0x00000000
  78 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  79
  80 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  81         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  82         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  83         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
  84         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
  85         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  86         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  87         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  88         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
  89         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
  90         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  91         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  92         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  93         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  94         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  95         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  96         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  97         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  98         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  99         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
 100         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 101         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
 102         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 103         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 104         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 105         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 106         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 107         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 108         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 109         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 110 };
 111
 112 fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
 113         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
 114         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
 115         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
 116         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
 117         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
 118         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 119         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
 120         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
 121         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
 122         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
 123         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
 124         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
 125         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
 126         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 127         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 128         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
 129         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
 130         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 131         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
 132         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 133         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
 134         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 135         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 136         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 137         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 138         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 139         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 140         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 141         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 142 };
 143
 144 fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
 145         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
 146         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
 147         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
 148         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
 149         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
 150         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 151         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
 152         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
 153         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
 154         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
 155         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
 156         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
 157         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
 158         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 159         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 160         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
 161         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
 162         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 163         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
 164         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 165         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
 166         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 167         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 168         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 169         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 170         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 171         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 172         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 173         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 174 };
 175
 176 fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
 177         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
 178         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
 179         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
 180         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
 181         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
 182         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 183         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
 184         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
 185         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
 186         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
 187         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
 188         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
 189         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
 190         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 191         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 192         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
 193         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
 194         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 195         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
 196         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 197         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
 198         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 199         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 200         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 201         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 202         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 203         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 204         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 205         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 206 };
 207
 208 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
 209         {750, 850, &ddr_cfg_regs_800},
 210         {850, 950, &ddr_cfg_regs_900},
 211         {950, 1050, &ddr_cfg_regs_1000},
 212         {1050, 1250, &ddr_cfg_regs_1200},
 213         {0, 0, NULL}
 214 };