board/freescale/t1040qds/ddr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <hwconfig.h>
  10 #include <asm/mmu.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <fsl_ddr_dimm_params.h>
  13 #include <asm/fsl_law.h>
  14 #include "ddr.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 void fsl_ddr_board_options(memctl_options_t *popts,
  19                                 dimm_params_t *pdimm,
  20                                 unsigned int ctrl_num)
  21 {
  22         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  23         ulong ddr_freq;
  24
  25         if (ctrl_num > 2) {
  26                 printf("Not supported controller number %d\n", ctrl_num);
  27                 return;
  28         }
  29         if (!pdimm->n_ranks)
  30                 return;
  31
  32         pbsp = udimms[0];
  33
  34         /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
  35          * freqency and n_banks specified in board_specific_parameters table.
  36          */
  37         ddr_freq = get_ddr_freq(0) / 1000000;
  38         while (pbsp->datarate_mhz_high) {
  39                 if (pbsp->n_ranks == pdimm->n_ranks &&
  40                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  41                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  42                                 popts->cpo_override = pbsp->cpo;
  43                                 popts->write_data_delay =
  44                                         pbsp->write_data_delay;
  45                                 popts->clk_adjust = pbsp->clk_adjust;
  46                                 popts->wrlvl_start = pbsp->wrlvl_start;
  47                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  48                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  49                                 popts->twot_en = pbsp->force_2t;
  50                                 goto found;
  51                         }
  52                         pbsp_highest = pbsp;
  53                 }
  54                 pbsp++;
  55         }
  56
  57         if (pbsp_highest) {
  58                 printf("Error: board specific timing not found\n");
  59                 printf("for data rate %lu MT/s\n", ddr_freq);
  60                 printf("Trying to use the highest speed (%u) parameters\n",
  61                        pbsp_highest->datarate_mhz_high);
  62                 popts->cpo_override = pbsp_highest->cpo;
  63                 popts->write_data_delay = pbsp_highest->write_data_delay;
  64                 popts->clk_adjust = pbsp_highest->clk_adjust;
  65                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  66                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  67                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  68                 popts->twot_en = pbsp_highest->force_2t;
  69         } else {
  70                 panic("DIMM is not supported by this board");
  71         }
  72 found:
  73         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  74                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  75                 "wrlvl_ctrl_3 0x%x\n",
  76                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  77                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  78                 pbsp->wrlvl_ctl_3);
  79
  80         /*
  81          * Factors to consider for half-strength driver enable:
  82          *      - number of DIMMs installed
  83          */
  84         popts->half_strength_driver_enable = 0;
  85         /*
  86          * Write leveling override
  87          */
  88         popts->wrlvl_override = 1;
  89         popts->wrlvl_sample = 0xf;
  90
  91         /*
  92          * rtt and rtt_wr override
  93          */
  94         popts->rtt_override = 0;
  95
  96         /* Enable ZQ calibration */
  97         popts->zq_en = 1;
  98
  99         /* DHC_EN =1, ODT = 75 Ohm */
 100         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 101         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 102 }
 103
 104 phys_size_t initdram(int board_type)
 105 {
 106         phys_size_t dram_size;
 107
 108         puts("Initializing....using SPD\n");
 109
 110         dram_size = fsl_ddr_sdram();
 111
 112         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 113         dram_size *= 0x100000;
 114
 115         puts("    DDR: ");
 116         return dram_size;
 117 }