board/freescale/t2080qds/eth_t2080qds.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <netdev.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <malloc.h>
  20 #include <fm_eth.h>
  21 #include <fsl_mdio.h>
  22 #include <miiphy.h>
  23 #include <phy.h>
  24 #include <asm/fsl_dtsec.h>
  25 #include <asm/fsl_serdes.h>
  26 #include "../common/qixis.h"
  27 #include "../common/fman.h"
  28 #include "t2080qds_qixis.h"
  29
  30 #define EMI_NONE        0xFFFFFFFF
  31 #define EMI1_RGMII1     0
  32 #define EMI1_RGMII2     1
  33 #define EMI1_SLOT1      2
  34 #define EMI1_SLOT2      6
  35 #define EMI1_SLOT3      3
  36 #define EMI1_SLOT4      4
  37 #define EMI1_SLOT5      5
  38 #define EMI2            7
  39
  40 static int mdio_mux[NUM_FM_PORTS];
  41
  42 static const char * const mdio_names[] = {
  43         "T2080QDS_MDIO_RGMII1",
  44         "T2080QDS_MDIO_RGMII2",
  45         "T2080QDS_MDIO_SLOT1",
  46         "T2080QDS_MDIO_SLOT3",
  47         "T2080QDS_MDIO_SLOT4",
  48         "T2080QDS_MDIO_SLOT5",
  49         "T2080QDS_MDIO_SLOT2",
  50         "T2080QDS_MDIO_10GC",
  51 };
  52
  53 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  54 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  55
  56 static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
  57 {
  58         return mdio_names[muxval];
  59 }
  60
  61 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  62 {
  63         struct mii_dev *bus;
  64         const char *name = T2080qds_mdio_name_for_muxval(muxval);
  65
  66         if (!name) {
  67                 printf("No bus for muxval %x\n", muxval);
  68                 return NULL;
  69         }
  70
  71         bus = miiphy_get_dev_by_name(name);
  72
  73         if (!bus) {
  74                 printf("No bus by name %s\n", name);
  75                 return NULL;
  76         }
  77
  78         return bus;
  79 }
  80
  81 struct T2080qds_mdio {
  82         u8 muxval;
  83         struct mii_dev *realbus;
  84 };
  85
  86 static void T2080qds_mux_mdio(u8 muxval)
  87 {
  88         u8 brdcfg4;
  89         if (muxval < 7) {
  90                 brdcfg4 = QIXIS_READ(brdcfg[4]);
  91                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  92                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  93                 QIXIS_WRITE(brdcfg[4], brdcfg4);
  94         }
  95 }
  96
  97 static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
  98                                 int regnum)
  99 {
 100         struct T2080qds_mdio *priv = bus->priv;
 101
 102         T2080qds_mux_mdio(priv->muxval);
 103
 104         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 105 }
 106
 107 static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 108                                 int regnum, u16 value)
 109 {
 110         struct T2080qds_mdio *priv = bus->priv;
 111
 112         T2080qds_mux_mdio(priv->muxval);
 113
 114         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 115 }
 116
 117 static int T2080qds_mdio_reset(struct mii_dev *bus)
 118 {
 119         struct T2080qds_mdio *priv = bus->priv;
 120
 121         return priv->realbus->reset(priv->realbus);
 122 }
 123
 124 static int T2080qds_mdio_init(char *realbusname, u8 muxval)
 125 {
 126         struct T2080qds_mdio *pmdio;
 127         struct mii_dev *bus = mdio_alloc();
 128
 129         if (!bus) {
 130                 printf("Failed to allocate T2080QDS MDIO bus\n");
 131                 return -1;
 132         }
 133
 134         pmdio = malloc(sizeof(*pmdio));
 135         if (!pmdio) {
 136                 printf("Failed to allocate T2080QDS private data\n");
 137                 free(bus);
 138                 return -1;
 139         }
 140
 141         bus->read = T2080qds_mdio_read;
 142         bus->write = T2080qds_mdio_write;
 143         bus->reset = T2080qds_mdio_reset;
 144         sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
 145
 146         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 147
 148         if (!pmdio->realbus) {
 149                 printf("No bus with name %s\n", realbusname);
 150                 free(bus);
 151                 free(pmdio);
 152                 return -1;
 153         }
 154
 155         pmdio->muxval = muxval;
 156         bus->priv = pmdio;
 157
 158         return mdio_register(bus);
 159 }
 160
 161 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 162                                 enum fm_port port, int offset)
 163 {
 164         int phy;
 165         char alias[20];
 166         struct fixed_link f_link;
 167         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 168         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 169                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 170
 171         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 172
 173         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 174                 phy = fm_info_get_phy_address(port);
 175                 switch (port) {
 176                 case FM1_DTSEC1:
 177                 case FM1_DTSEC2:
 178                 case FM1_DTSEC9:
 179                 case FM1_DTSEC10:
 180                         sprintf(alias, "phy_sgmii_s3_%x", phy);
 181                         fdt_set_phy_handle(fdt, compat, addr, alias);
 182                         fdt_status_okay_by_alias(fdt, "emi1_slot3");
 183                         break;
 184                 case FM1_DTSEC5:
 185                 case FM1_DTSEC6:
 186                         if (mdio_mux[port] == EMI1_SLOT1) {
 187                                 sprintf(alias, "phy_sgmii_s1_%x", phy);
 188                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 189                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 190                         } else if (mdio_mux[port] == EMI1_SLOT2) {
 191                                 sprintf(alias, "phy_sgmii_s2_%x", phy);
 192                                 fdt_set_phy_handle(fdt, compat, addr, alias);
 193                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 194                         }
 195                         break;
 196                 default:
 197                         break;
 198                 }
 199
 200         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
 201                 switch (srds_s1) {
 202                 case 0x66: /* XFI interface */
 203                 case 0x6b:
 204                 case 0x6c:
 205                 case 0x6d:
 206                 case 0x71:
 207                         f_link.phy_id = port;
 208                         f_link.duplex = 1;
 209                         f_link.link_speed = 10000;
 210                         f_link.pause = 0;
 211                         f_link.asym_pause = 0;
 212                         /* no PHY for XFI */
 213                         fdt_delprop(fdt, offset, "phy-handle");
 214                         fdt_setprop(fdt, offset, "fixed-link", &f_link,
 215                                     sizeof(f_link));
 216                         break;
 217                 default:
 218                         break;
 219                 }
 220         }
 221 }
 222
 223 void fdt_fixup_board_enet(void *fdt)
 224 {
 225         return;
 226 }
 227
 228 /*
 229  * This function reads RCW to check if Serdes1{E,F,G,H} is configured
 230  * as slot 1/2/3 and update the lane_to_slot[] array accordingly
 231  */
 232 static void initialize_lane_to_slot(void)
 233 {
 234         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 235         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 236                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 237
 238         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 239
 240         switch (srds_s1) {
 241         case 0x51:
 242         case 0x5f:
 243         case 0x65:
 244         case 0x6b:
 245         case 0x71:
 246                 lane_to_slot[5] = 2;
 247                 lane_to_slot[6] = 2;
 248                 lane_to_slot[7] = 2;
 249                 break;
 250         case 0xa6:
 251         case 0x8e:
 252         case 0x8f:
 253         case 0x82:
 254         case 0x83:
 255         case 0xd3:
 256         case 0xd9:
 257         case 0xcb:
 258                 lane_to_slot[6] = 2;
 259                 lane_to_slot[7] = 2;
 260                 break;
 261         case 0xda:
 262                 lane_to_slot[4] = 3;
 263                 lane_to_slot[5] = 3;
 264                 lane_to_slot[6] = 3;
 265                 lane_to_slot[7] = 3;
 266                 break;
 267         default:
 268                 break;
 269         }
 270 }
 271
 272 int board_eth_init(bd_t *bis)
 273 {
 274 #if defined(CONFIG_FMAN_ENET)
 275         int i, idx, lane, slot, interface;
 276         struct memac_mdio_info dtsec_mdio_info;
 277         struct memac_mdio_info tgec_mdio_info;
 278         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 279         u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
 280         u32 srds_s1;
 281
 282         srds_s1 = in_be32(&gur->rcwsr[4]) &
 283                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 284         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 285
 286         initialize_lane_to_slot();
 287
 288         /* Initialize the mdio_mux array so we can recognize empty elements */
 289         for (i = 0; i < NUM_FM_PORTS; i++)
 290                 mdio_mux[i] = EMI_NONE;
 291
 292         dtsec_mdio_info.regs =
 293                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
 294
 295         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 296
 297         /* Register the 1G MDIO bus */
 298         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 299
 300         tgec_mdio_info.regs =
 301                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 302         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 303
 304         /* Register the 10G MDIO bus */
 305         fm_memac_mdio_init(bis, &tgec_mdio_info);
 306
 307         /* Register the muxing front-ends to the MDIO buses */
 308         T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
 309         T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
 310         T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 311         T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 312         T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 313         T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 314         T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 315         T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 316
 317         /* Set the two on-board RGMII PHY address */
 318         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
 319         if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
 320                         FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
 321                 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
 322         else
 323                 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
 324
 325         switch (srds_s1) {
 326         case 0x1c:
 327         case 0x95:
 328         case 0xa2:
 329         case 0x94:
 330                 /* SGMII in Slot3 */
 331                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 332                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 333                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 334                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 335                 /* SGMII in Slot2 */
 336                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 337                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 338                 break;
 339         case 0x51:
 340         case 0x5f:
 341         case 0x65:
 342                 /* XAUI/HiGig in Slot3 */
 343                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 344                 /* SGMII in Slot2 */
 345                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 346                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 347                 break;
 348         case 0x66:
 349                 /*
 350                  * XFI does not need a PHY to work, but to avoid U-boot use
 351                  * default PHY address which is zero to a MAC when it found
 352                  * a MAC has no PHY address, we give a PHY address to XFI
 353                  * MAC, and should not use a real XAUI PHY address, since
 354                  * MDIO can access it successfully, and then MDIO thinks
 355                  * the XAUI card is used for the XFI MAC, which will cause
 356                  * error.
 357                  */
 358                 fm_info_set_phy_address(FM1_10GEC1, 4);
 359                 fm_info_set_phy_address(FM1_10GEC2, 5);
 360                 fm_info_set_phy_address(FM1_10GEC3, 6);
 361                 fm_info_set_phy_address(FM1_10GEC4, 7);
 362                 break;
 363         case 0x6b:
 364                 fm_info_set_phy_address(FM1_10GEC1, 4);
 365                 fm_info_set_phy_address(FM1_10GEC2, 5);
 366                 fm_info_set_phy_address(FM1_10GEC3, 6);
 367                 fm_info_set_phy_address(FM1_10GEC4, 7);
 368                 /* SGMII in Slot2 */
 369                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 370                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 371                 break;
 372         case 0x6c:
 373         case 0x6d:
 374                 fm_info_set_phy_address(FM1_10GEC1, 4);
 375                 fm_info_set_phy_address(FM1_10GEC2, 5);
 376                 /* SGMII in Slot3 */
 377                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 378                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 379                 break;
 380         case 0x71:
 381                 /* SGMII in Slot3 */
 382                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 383                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 384                 /* SGMII in Slot2 */
 385                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 386                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 387                 break;
 388         case 0xa6:
 389         case 0x8e:
 390         case 0x8f:
 391         case 0x82:
 392         case 0x83:
 393                 /* SGMII in Slot3 */
 394                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 395                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 396                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 397                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 398                 /* SGMII in Slot2 */
 399                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 400                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 401                 break;
 402         case 0xa4:
 403         case 0x96:
 404         case 0x8a:
 405                 /* SGMII in Slot3 */
 406                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 407                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 408                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 409                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 410                 break;
 411         case 0xd9:
 412         case 0xd3:
 413         case 0xcb:
 414                 /* SGMII in Slot3 */
 415                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 416                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 417                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 418                 /* SGMII in Slot2 */
 419                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 420                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 421                 break;
 422         default:
 423                 break;
 424         }
 425
 426         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 427                 idx = i - FM1_DTSEC1;
 428                 interface = fm_info_get_enet_if(i);
 429                 switch (interface) {
 430                 case PHY_INTERFACE_MODE_SGMII:
 431                         lane = serdes_get_first_lane(FSL_SRDS_1,
 432                                         SGMII_FM1_DTSEC1 + idx);
 433                         if (lane < 0)
 434                                 break;
 435                         slot = lane_to_slot[lane];
 436                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 437                               idx + 1, slot);
 438                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 439                                 fm_disable_port(i);
 440
 441                         switch (slot) {
 442                         case 1:
 443                                 mdio_mux[i] = EMI1_SLOT1;
 444                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 445                                                  mdio_mux[i]));
 446                                 break;
 447                         case 2:
 448                                 mdio_mux[i] = EMI1_SLOT2;
 449                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 450                                                  mdio_mux[i]));
 451                                 break;
 452                         case 3:
 453                                 mdio_mux[i] = EMI1_SLOT3;
 454                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 455                                                 mdio_mux[i]));
 456                                 break;
 457                         }
 458                         break;
 459                 case PHY_INTERFACE_MODE_RGMII:
 460                         if (i == FM1_DTSEC3)
 461                                 mdio_mux[i] = EMI1_RGMII1;
 462                         else if (i == FM1_DTSEC4 || FM1_DTSEC10)
 463                                 mdio_mux[i] = EMI1_RGMII2;
 464                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 465                         break;
 466                 default:
 467                         break;
 468                 }
 469         }
 470
 471         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 472                 idx = i - FM1_10GEC1;
 473                 switch (fm_info_get_enet_if(i)) {
 474                 case PHY_INTERFACE_MODE_XGMII:
 475                         if (srds_s1 == 0x51) {
 476                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 477                                                 XAUI_FM1_MAC9 + idx);
 478                         } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
 479                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 480                                                 HIGIG_FM1_MAC9 + idx);
 481                         } else {
 482                                 if (i == FM1_10GEC1 || i == FM1_10GEC2)
 483                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 484                                                 XFI_FM1_MAC9 + idx);
 485                                 else
 486                                         lane = serdes_get_first_lane(FSL_SRDS_1,
 487                                                 XFI_FM1_MAC1 + idx);
 488                         }
 489
 490                         if (lane < 0)
 491                                 break;
 492                         mdio_mux[i] = EMI2;
 493                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 494
 495                         if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
 496                             (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 497                             (srds_s1 == 0x71)) {
 498                                 /* As XFI is in cage intead of a slot, so
 499                                  * ensure doesn't disable the corresponding port
 500                                  */
 501                                 break;
 502                         }
 503
 504                         slot = lane_to_slot[lane];
 505                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 506                                 fm_disable_port(i);
 507                         break;
 508                 default:
 509                         break;
 510                 }
 511         }
 512
 513         cpu_eth_init(bis);
 514 #endif /* CONFIG_FMAN_ENET */
 515
 516         return pci_eth_init(bis);
 517 }