board/freescale/t4qds/eth.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <netdev.h>
  26 #include <asm/mmu.h>
  27 #include <asm/processor.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_law.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/fsl_serdes.h>
  33 #include <asm/fsl_portals.h>
  34 #include <asm/fsl_liodn.h>
  35 #include <malloc.h>
  36 #include <fm_eth.h>
  37 #include <fsl_mdio.h>
  38 #include <miiphy.h>
  39 #include <phy.h>
  40 #include <asm/fsl_dtsec.h>
  41 #include <asm/fsl_serdes.h>
  42 #include "../common/qixis.h"
  43 #include "../common/fman.h"
  44
  45 #include "t4240qds_qixis.h"
  46
  47 #define EMI_NONE        0xFFFFFFFF
  48 #define EMI1_RGMII      0
  49 #define EMI1_SLOT1      1
  50 #define EMI1_SLOT2      2
  51 #define EMI1_SLOT3      3
  52 #define EMI1_SLOT4      4
  53 #define EMI1_SLOT5      5
  54 #define EMI1_SLOT7      7
  55 #define EMI2            8
  56 /* Slot6 and Slot8 do not have EMI connections */
  57
  58 static int mdio_mux[NUM_FM_PORTS];
  59
  60 static const char *mdio_names[] = {
  61         "T4240QDS_MDIO0",
  62         "T4240QDS_MDIO1",
  63         "T4240QDS_MDIO2",
  64         "T4240QDS_MDIO3",
  65         "T4240QDS_MDIO4",
  66         "T4240QDS_MDIO5",
  67         "NULL",
  68         "T4240QDS_MDIO7",
  69         "T4240QDS_10GC",
  70 };
  71
  72 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  73 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  74 static u8 slot_qsgmii_phyaddr[5][4] = {
  75         {0, 0, 0, 0},/* not used, to make index match slot No. */
  76         {0, 1, 2, 3},
  77         {4, 5, 6, 7},
  78         {8, 9, 0xa, 0xb},
  79         {0xc, 0xd, 0xe, 0xf},
  80 };
  81 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  82
  83 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  84 {
  85         return mdio_names[muxval];
  86 }
  87
  88 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  89 {
  90         struct mii_dev *bus;
  91         const char *name = t4240qds_mdio_name_for_muxval(muxval);
  92
  93         if (!name) {
  94                 printf("No bus for muxval %x\n", muxval);
  95                 return NULL;
  96         }
  97
  98         bus = miiphy_get_dev_by_name(name);
  99
 100         if (!bus) {
 101                 printf("No bus by name %s\n", name);
 102                 return NULL;
 103         }
 104
 105         return bus;
 106 }
 107
 108 struct t4240qds_mdio {
 109         u8 muxval;
 110         struct mii_dev *realbus;
 111 };
 112
 113 static void t4240qds_mux_mdio(u8 muxval)
 114 {
 115         u8 brdcfg4;
 116         if ((muxval < 6) || (muxval == 7)) {
 117                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 118                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 119                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 120                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 121         }
 122 }
 123
 124 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 125                                 int regnum)
 126 {
 127         struct t4240qds_mdio *priv = bus->priv;
 128
 129         t4240qds_mux_mdio(priv->muxval);
 130
 131         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 132 }
 133
 134 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 135                                 int regnum, u16 value)
 136 {
 137         struct t4240qds_mdio *priv = bus->priv;
 138
 139         t4240qds_mux_mdio(priv->muxval);
 140
 141         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 142 }
 143
 144 static int t4240qds_mdio_reset(struct mii_dev *bus)
 145 {
 146         struct t4240qds_mdio *priv = bus->priv;
 147
 148         return priv->realbus->reset(priv->realbus);
 149 }
 150
 151 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 152 {
 153         struct t4240qds_mdio *pmdio;
 154         struct mii_dev *bus = mdio_alloc();
 155
 156         if (!bus) {
 157                 printf("Failed to allocate T4240QDS MDIO bus\n");
 158                 return -1;
 159         }
 160
 161         pmdio = malloc(sizeof(*pmdio));
 162         if (!pmdio) {
 163                 printf("Failed to allocate T4240QDS private data\n");
 164                 free(bus);
 165                 return -1;
 166         }
 167
 168         bus->read = t4240qds_mdio_read;
 169         bus->write = t4240qds_mdio_write;
 170         bus->reset = t4240qds_mdio_reset;
 171         sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
 172
 173         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 174
 175         if (!pmdio->realbus) {
 176                 printf("No bus with name %s\n", realbusname);
 177                 free(bus);
 178                 free(pmdio);
 179                 return -1;
 180         }
 181
 182         pmdio->muxval = muxval;
 183         bus->priv = pmdio;
 184
 185         return mdio_register(bus);
 186 }
 187
 188 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 189                                 enum fm_port port, int offset)
 190 {
 191         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 192                 switch (port) {
 193                 case FM1_DTSEC1:
 194                         if (qsgmiiphy_fix[port])
 195                                 fdt_set_phy_handle(blob, prop, pa,
 196                                                    "sgmii_phy21");
 197                         break;
 198                 case FM1_DTSEC2:
 199                         if (qsgmiiphy_fix[port])
 200                                 fdt_set_phy_handle(blob, prop, pa,
 201                                                    "sgmii_phy22");
 202                         break;
 203                 case FM1_DTSEC3:
 204                         if (qsgmiiphy_fix[port])
 205                                 fdt_set_phy_handle(blob, prop, pa,
 206                                                    "sgmii_phy23");
 207                         break;
 208                 case FM1_DTSEC4:
 209                         if (qsgmiiphy_fix[port])
 210                                 fdt_set_phy_handle(blob, prop, pa,
 211                                                    "sgmii_phy24");
 212                         break;
 213                 case FM1_DTSEC6:
 214                         if (qsgmiiphy_fix[port])
 215                                 fdt_set_phy_handle(blob, prop, pa,
 216                                                    "sgmii_phy12");
 217                         break;
 218                 case FM1_DTSEC9:
 219                         if (qsgmiiphy_fix[port])
 220                                 fdt_set_phy_handle(blob, prop, pa,
 221                                                    "sgmii_phy14");
 222                         else
 223                                 fdt_set_phy_handle(blob, prop, pa,
 224                                                    "phy_sgmii4");
 225                         break;
 226                 case FM1_DTSEC10:
 227                         if (qsgmiiphy_fix[port])
 228                                 fdt_set_phy_handle(blob, prop, pa,
 229                                                    "sgmii_phy13");
 230                         else
 231                                 fdt_set_phy_handle(blob, prop, pa,
 232                                                    "phy_sgmii3");
 233                         break;
 234                 case FM2_DTSEC1:
 235                         if (qsgmiiphy_fix[port])
 236                                 fdt_set_phy_handle(blob, prop, pa,
 237                                                    "sgmii_phy41");
 238                         break;
 239                 case FM2_DTSEC2:
 240                         if (qsgmiiphy_fix[port])
 241                                 fdt_set_phy_handle(blob, prop, pa,
 242                                                    "sgmii_phy42");
 243                         break;
 244                 case FM2_DTSEC3:
 245                         if (qsgmiiphy_fix[port])
 246                                 fdt_set_phy_handle(blob, prop, pa,
 247                                                    "sgmii_phy43");
 248                         break;
 249                 case FM2_DTSEC4:
 250                         if (qsgmiiphy_fix[port])
 251                                 fdt_set_phy_handle(blob, prop, pa,
 252                                                    "sgmii_phy44");
 253                         break;
 254                 case FM2_DTSEC6:
 255                         if (qsgmiiphy_fix[port])
 256                                 fdt_set_phy_handle(blob, prop, pa,
 257                                                    "sgmii_phy32");
 258                         break;
 259                 case FM2_DTSEC9:
 260                         if (qsgmiiphy_fix[port])
 261                                 fdt_set_phy_handle(blob, prop, pa,
 262                                                    "sgmii_phy34");
 263                         else
 264                                 fdt_set_phy_handle(blob, prop, pa,
 265                                                    "phy_sgmii12");
 266                         break;
 267                 case FM2_DTSEC10:
 268                         if (qsgmiiphy_fix[port])
 269                                 fdt_set_phy_handle(blob, prop, pa,
 270                                                    "sgmii_phy33");
 271                         else
 272                                 fdt_set_phy_handle(blob, prop, pa,
 273                                                    "phy_sgmii11");
 274                         break;
 275                 default:
 276                         break;
 277                 }
 278         }
 279 }
 280
 281 void fdt_fixup_board_enet(void *fdt)
 282 {
 283         int i;
 284         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 285         u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 286
 287         prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 288         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 289                 switch (fm_info_get_enet_if(i)) {
 290                 case PHY_INTERFACE_MODE_SGMII:
 291                         switch (mdio_mux[i]) {
 292                         case EMI1_SLOT1:
 293                                 fdt_status_okay_by_alias(fdt, "emi1_slot1");
 294                                 break;
 295                         case EMI1_SLOT2:
 296                                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 297                                 break;
 298                         case EMI1_SLOT3:
 299                                 fdt_status_okay_by_alias(fdt, "emi1_slot3");
 300                                 break;
 301                         case EMI1_SLOT4:
 302                                 fdt_status_okay_by_alias(fdt, "emi1_slot4");
 303                                 break;
 304                         default:
 305                                 break;
 306                         }
 307                         break;
 308                 case PHY_INTERFACE_MODE_XGMII:
 309                         /* check if it's XFI interface for 10g */
 310                         if ((prtcl2 == 56) || (prtcl2 == 57)) {
 311                                 fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
 312                                 break;
 313                         }
 314                         switch (i) {
 315                         case FM1_10GEC1:
 316                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
 317                                 break;
 318                         case FM1_10GEC2:
 319                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
 320                                 break;
 321                         case FM2_10GEC1:
 322                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
 323                                 break;
 324                         case FM2_10GEC2:
 325                                 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
 326                                 break;
 327                         default:
 328                                 break;
 329                         }
 330                         break;
 331                 default:
 332                         break;
 333                 }
 334         }
 335 }
 336
 337 static void initialize_qsgmiiphy_fix(void)
 338 {
 339         int i;
 340         unsigned short reg;
 341
 342         for (i = 1; i <= 4; i++) {
 343                 /*
 344                  * Try to read if a SGMII card is used, we do it slot by slot.
 345                  * if a SGMII PHY address is valid on a slot, then we mark
 346                  * all ports on the slot, then fix the PHY address for the
 347                  * marked port when doing dtb fixup.
 348                  */
 349                 if (miiphy_read(mdio_names[i],
 350                                 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
 351                         debug("Slot%d PHY ID register 2 read failed\n", i);
 352                         continue;
 353                 }
 354
 355                 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
 356
 357                 if (reg == 0xFFFF) {
 358                         /* No physical device present at this address */
 359                         continue;
 360                 }
 361
 362                 switch (i) {
 363                 case 1:
 364                         qsgmiiphy_fix[FM1_DTSEC5] = 1;
 365                         qsgmiiphy_fix[FM1_DTSEC6] = 1;
 366                         qsgmiiphy_fix[FM1_DTSEC9] = 1;
 367                         qsgmiiphy_fix[FM1_DTSEC10] = 1;
 368                         slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 369                         slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 370                         slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 371                         slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 372                         break;
 373                 case 2:
 374                         qsgmiiphy_fix[FM1_DTSEC1] = 1;
 375                         qsgmiiphy_fix[FM1_DTSEC2] = 1;
 376                         qsgmiiphy_fix[FM1_DTSEC3] = 1;
 377                         qsgmiiphy_fix[FM1_DTSEC4] = 1;
 378                         slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 379                         slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 380                         slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 381                         slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 382                         break;
 383                 case 3:
 384                         qsgmiiphy_fix[FM2_DTSEC5] = 1;
 385                         qsgmiiphy_fix[FM2_DTSEC6] = 1;
 386                         qsgmiiphy_fix[FM2_DTSEC9] = 1;
 387                         qsgmiiphy_fix[FM2_DTSEC10] = 1;
 388                         slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 389                         slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 390                         slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 391                         slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 392                         break;
 393                 case 4:
 394                         qsgmiiphy_fix[FM2_DTSEC1] = 1;
 395                         qsgmiiphy_fix[FM2_DTSEC2] = 1;
 396                         qsgmiiphy_fix[FM2_DTSEC3] = 1;
 397                         qsgmiiphy_fix[FM2_DTSEC4] = 1;
 398                         slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
 399                         slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
 400                         slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
 401                         slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
 402                         break;
 403                 default:
 404                         break;
 405                 }
 406         }
 407 }
 408
 409 int board_eth_init(bd_t *bis)
 410 {
 411 #if defined(CONFIG_FMAN_ENET)
 412         int i, idx, lane, slot;
 413         struct memac_mdio_info dtsec_mdio_info;
 414         struct memac_mdio_info tgec_mdio_info;
 415         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 416         u32 srds_prtcl_s1, srds_prtcl_s2;
 417
 418         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 419                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 420         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 421         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 422                                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 423         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 424
 425         /* Initialize the mdio_mux array so we can recognize empty elements */
 426         for (i = 0; i < NUM_FM_PORTS; i++)
 427                 mdio_mux[i] = EMI_NONE;
 428
 429         dtsec_mdio_info.regs =
 430                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
 431
 432         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 433
 434         /* Register the 1G MDIO bus */
 435         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 436
 437         tgec_mdio_info.regs =
 438                 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
 439         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 440
 441         /* Register the 10G MDIO bus */
 442         fm_memac_mdio_init(bis, &tgec_mdio_info);
 443
 444         /* Register the muxing front-ends to the MDIO buses */
 445         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
 446         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 447         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 448         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 449         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 450         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 451         t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 452         t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 453
 454         initialize_qsgmiiphy_fix();
 455
 456         switch (srds_prtcl_s1) {
 457         case 1:
 458         case 2:
 459         case 4:
 460                 /* XAUI/HiGig in Slot1 and Slot2 */
 461                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 462                 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 463                 break;
 464         case 28:
 465         case 36:
 466                 /* SGMII in Slot1 and Slot2 */
 467                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 468                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 469                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 470                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 471                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 472                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 473                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 474                         fm_info_set_phy_address(FM1_DTSEC9,
 475                                                 slot_qsgmii_phyaddr[1][3]);
 476                         fm_info_set_phy_address(FM1_DTSEC10,
 477                                                 slot_qsgmii_phyaddr[1][2]);
 478                 }
 479                 break;
 480         case 38:
 481                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 482                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 483                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 484                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 485                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 486                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 487                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 488                         fm_info_set_phy_address(FM1_DTSEC9,
 489                                                 slot_qsgmii_phyaddr[1][3]);
 490                         fm_info_set_phy_address(FM1_DTSEC10,
 491                                                 slot_qsgmii_phyaddr[1][2]);
 492                 }
 493                 break;
 494         case 40:
 495         case 46:
 496         case 48:
 497                 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 498                 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 499                 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 500                         fm_info_set_phy_address(FM1_DTSEC10,
 501                                                 slot_qsgmii_phyaddr[1][3]);
 502                         fm_info_set_phy_address(FM1_DTSEC9,
 503                                                 slot_qsgmii_phyaddr[1][2]);
 504                 }
 505                 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 506                 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
 507                 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
 508                 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 509                 break;
 510         default:
 511                 puts("Invalid SerDes1 protocol for T4240QDS\n");
 512                 break;
 513         }
 514
 515         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 516                 idx = i - FM1_DTSEC1;
 517                 switch (fm_info_get_enet_if(i)) {
 518                 case PHY_INTERFACE_MODE_SGMII:
 519                         lane = serdes_get_first_lane(FSL_SRDS_1,
 520                                                 SGMII_FM1_DTSEC1 + idx);
 521                         if (lane < 0)
 522                                 break;
 523                         slot = lane_to_slot_fsm1[lane];
 524                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 525                                 idx + 1, slot);
 526                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 527                                 fm_disable_port(i);
 528                         switch (slot) {
 529                         case 1:
 530                                 mdio_mux[i] = EMI1_SLOT1;
 531                                 fm_info_set_mdio(i,
 532                                         mii_dev_for_muxval(mdio_mux[i]));
 533                                 break;
 534                         case 2:
 535                                 mdio_mux[i] = EMI1_SLOT2;
 536                                 fm_info_set_mdio(i,
 537                                         mii_dev_for_muxval(mdio_mux[i]));
 538                                 break;
 539                         };
 540                         break;
 541                 case PHY_INTERFACE_MODE_RGMII:
 542                         /* FM1 DTSEC5 routes to RGMII with EC2 */
 543                         debug("FM1@DTSEC%u is RGMII at address %u\n",
 544                                 idx + 1, 2);
 545                         if (i == FM1_DTSEC5)
 546                                 fm_info_set_phy_address(i, 2);
 547                         mdio_mux[i] = EMI1_RGMII;
 548                         fm_info_set_mdio(i,
 549                                 mii_dev_for_muxval(mdio_mux[i]));
 550                         break;
 551                 default:
 552                         break;
 553                 }
 554         }
 555
 556         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 557                 idx = i - FM1_10GEC1;
 558                 switch (fm_info_get_enet_if(i)) {
 559                 case PHY_INTERFACE_MODE_XGMII:
 560                         lane = serdes_get_first_lane(FSL_SRDS_1,
 561                                                 XAUI_FM1_MAC9 + idx);
 562                         if (lane < 0)
 563                                 break;
 564                         slot = lane_to_slot_fsm1[lane];
 565                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 566                                 fm_disable_port(i);
 567                         mdio_mux[i] = EMI2;
 568                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 569                         break;
 570                 default:
 571                         break;
 572                 }
 573         }
 574
 575 #if (CONFIG_SYS_NUM_FMAN == 2)
 576         switch (srds_prtcl_s2) {
 577         case 1:
 578         case 2:
 579         case 4:
 580                 /* XAUI/HiGig in Slot3 and Slot4 */
 581                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 582                 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 583                 break;
 584         case 7:
 585         case 13:
 586         case 14:
 587         case 16:
 588         case 22:
 589         case 23:
 590         case 25:
 591         case 26:
 592                 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
 593                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 594                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 595                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 596                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 597                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 598                 break;
 599         case 28:
 600         case 36:
 601                 /* SGMII in Slot3 and Slot4 */
 602                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 603                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 604                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 605                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 606                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 607                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 608                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 609                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 610                 break;
 611         case 38:
 612                 /* QSGMII in Slot3 and Slot4 */
 613                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 614                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 615                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 616                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 617                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 618                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 619                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 620                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 621                 break;
 622         case 40:
 623         case 46:
 624         case 48:
 625                 /* SGMII in Slot3 */
 626                 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 627                 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
 628                 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 629                 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 630                 /* QSGMII in Slot4 */
 631                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 632                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 633                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 634                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 635                 break;
 636         case 50:
 637         case 52:
 638         case 54:
 639                 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 640                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 641                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 642                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 643                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 644                 break;
 645         case 56:
 646         case 57:
 647                 /* XFI in Slot3, SGMII in Slot4 */
 648                 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
 649                 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
 650                 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 651                 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 652                 break;
 653         default:
 654                 puts("Invalid SerDes2 protocol for T4240QDS\n");
 655                 break;
 656         }
 657
 658         for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 659                 idx = i - FM2_DTSEC1;
 660                 switch (fm_info_get_enet_if(i)) {
 661                 case PHY_INTERFACE_MODE_SGMII:
 662                         lane = serdes_get_first_lane(FSL_SRDS_2,
 663                                                 SGMII_FM2_DTSEC1 + idx);
 664                         if (lane < 0)
 665                                 break;
 666                         slot = lane_to_slot_fsm2[lane];
 667                         debug("FM2@DTSEC%u expects SGMII in slot %u\n",
 668                                 idx + 1, slot);
 669                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 670                                 fm_disable_port(i);
 671                         switch (slot) {
 672                         case 3:
 673                                 mdio_mux[i] = EMI1_SLOT3;
 674                                 fm_info_set_mdio(i,
 675                                         mii_dev_for_muxval(mdio_mux[i]));
 676                                 break;
 677                         case 4:
 678                                 mdio_mux[i] = EMI1_SLOT4;
 679                                 fm_info_set_mdio(i,
 680                                         mii_dev_for_muxval(mdio_mux[i]));
 681                                 break;
 682                         };
 683                         break;
 684                 case PHY_INTERFACE_MODE_RGMII:
 685                         /*
 686                          * If DTSEC5 is RGMII, then it's routed via via EC1 to
 687                          * the first on-board RGMII port.  If DTSEC6 is RGMII,
 688                          * then it's routed via via EC2 to the second on-board
 689                          * RGMII port.
 690                          */
 691                         debug("FM2@DTSEC%u is RGMII at address %u\n",
 692                                 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
 693                         fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
 694                         mdio_mux[i] = EMI1_RGMII;
 695                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 696                         break;
 697                 default:
 698                         break;
 699                 }
 700         }
 701
 702         for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
 703                 idx = i - FM2_10GEC1;
 704                 switch (fm_info_get_enet_if(i)) {
 705                 case PHY_INTERFACE_MODE_XGMII:
 706                         lane = serdes_get_first_lane(FSL_SRDS_2,
 707                                                 XAUI_FM2_MAC9 + idx);
 708                         if (lane < 0)
 709                                 break;
 710                         slot = lane_to_slot_fsm2[lane];
 711                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 712                                 fm_disable_port(i);
 713                         mdio_mux[i] = EMI2;
 714                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 715                         break;
 716                 default:
 717                         break;
 718                 }
 719         }
 720 #endif /* CONFIG_SYS_NUM_FMAN */
 721
 722         cpu_eth_init(bis);
 723 #endif /* CONFIG_FMAN_ENET */
 724
 725         return pci_eth_init(bis);
 726 }