board/freescale/vf610twr/vf610twr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux-vf610.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/clock.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <miiphy.h>
  16 #include <netdev.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  21                         PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
  22
  23 #define ESDHC_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  24                         PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
  25
  26 #define ENET_PAD_CTRL   (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
  27                         PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
  28
  29 void setup_iomux_ddr(void)
  30 {
  31         static const iomux_v3_cfg_t ddr_pads[] = {
  32                 VF610_PAD_DDR_A15__DDR_A_15,
  33                 VF610_PAD_DDR_A15__DDR_A_15,
  34                 VF610_PAD_DDR_A14__DDR_A_14,
  35                 VF610_PAD_DDR_A13__DDR_A_13,
  36                 VF610_PAD_DDR_A12__DDR_A_12,
  37                 VF610_PAD_DDR_A11__DDR_A_11,
  38                 VF610_PAD_DDR_A10__DDR_A_10,
  39                 VF610_PAD_DDR_A9__DDR_A_9,
  40                 VF610_PAD_DDR_A8__DDR_A_8,
  41                 VF610_PAD_DDR_A7__DDR_A_7,
  42                 VF610_PAD_DDR_A6__DDR_A_6,
  43                 VF610_PAD_DDR_A5__DDR_A_5,
  44                 VF610_PAD_DDR_A4__DDR_A_4,
  45                 VF610_PAD_DDR_A3__DDR_A_3,
  46                 VF610_PAD_DDR_A2__DDR_A_2,
  47                 VF610_PAD_DDR_A1__DDR_A_1,
  48                 VF610_PAD_DDR_BA2__DDR_BA_2,
  49                 VF610_PAD_DDR_BA1__DDR_BA_1,
  50                 VF610_PAD_DDR_BA0__DDR_BA_0,
  51                 VF610_PAD_DDR_CAS__DDR_CAS_B,
  52                 VF610_PAD_DDR_CKE__DDR_CKE_0,
  53                 VF610_PAD_DDR_CLK__DDR_CLK_0,
  54                 VF610_PAD_DDR_CS__DDR_CS_B_0,
  55                 VF610_PAD_DDR_D15__DDR_D_15,
  56                 VF610_PAD_DDR_D14__DDR_D_14,
  57                 VF610_PAD_DDR_D13__DDR_D_13,
  58                 VF610_PAD_DDR_D12__DDR_D_12,
  59                 VF610_PAD_DDR_D11__DDR_D_11,
  60                 VF610_PAD_DDR_D10__DDR_D_10,
  61                 VF610_PAD_DDR_D9__DDR_D_9,
  62                 VF610_PAD_DDR_D8__DDR_D_8,
  63                 VF610_PAD_DDR_D7__DDR_D_7,
  64                 VF610_PAD_DDR_D6__DDR_D_6,
  65                 VF610_PAD_DDR_D5__DDR_D_5,
  66                 VF610_PAD_DDR_D4__DDR_D_4,
  67                 VF610_PAD_DDR_D3__DDR_D_3,
  68                 VF610_PAD_DDR_D2__DDR_D_2,
  69                 VF610_PAD_DDR_D1__DDR_D_1,
  70                 VF610_PAD_DDR_D0__DDR_D_0,
  71                 VF610_PAD_DDR_DQM1__DDR_DQM_1,
  72                 VF610_PAD_DDR_DQM0__DDR_DQM_0,
  73                 VF610_PAD_DDR_DQS1__DDR_DQS_1,
  74                 VF610_PAD_DDR_DQS0__DDR_DQS_0,
  75                 VF610_PAD_DDR_RAS__DDR_RAS_B,
  76                 VF610_PAD_DDR_WE__DDR_WE_B,
  77                 VF610_PAD_DDR_ODT1__DDR_ODT_0,
  78                 VF610_PAD_DDR_ODT0__DDR_ODT_1,
  79         };
  80
  81         imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
  82 }
  83
  84 void ddr_phy_init(void)
  85 {
  86         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
  87
  88         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
  89         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
  90         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
  91         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
  92
  93         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
  94         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
  95         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
  96         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
  97
  98         writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
  99         writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
 100         writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
 101         writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
 102
 103         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
 104         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
 105         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
 106         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
 107
 108         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
 109         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
 110         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
 111         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
 112
 113         writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
 114                 &ddrmr->phy[50]);
 115 }
 116
 117 void ddr_ctrl_init(void)
 118 {
 119         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 120
 121         writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
 122         writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
 123         writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
 124
 125         writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
 126         writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
 127         writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
 128                 DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
 129         writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
 130                 DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
 131         writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
 132         writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
 133                 &ddrmr->cr[17]);
 134         writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
 135
 136         writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
 137         writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
 138                 DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
 139
 140         writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
 141         writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
 142         writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
 143
 144         writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
 145         writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
 146         writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
 147         writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
 148
 149         writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
 150         writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
 151         writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
 152         writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
 153
 154         writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
 155         writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
 156                 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
 157
 158         writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
 159         writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
 160                 &ddrmr->cr[48]);
 161
 162         writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
 163         writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
 164         writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 165
 166         writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
 167         writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
 168
 169         writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
 170                 DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
 171         writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
 172                 DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
 173                 &ddrmr->cr[74]);
 174         writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
 175                 DDRMC_CR75_PLEN, &ddrmr->cr[75]);
 176         writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
 177                 DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
 178         writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
 179                 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
 180         writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
 181         writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
 182
 183         writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 184
 185         writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
 186                 &ddrmr->cr[87]);
 187         writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
 188         writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
 189
 190         writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
 191         writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
 192
 193         writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
 194         writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
 195         writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
 196
 197         writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
 198                 &ddrmr->cr[117]);
 199         writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
 200                 &ddrmr->cr[118]);
 201
 202         writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
 203                 &ddrmr->cr[120]);
 204         writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
 205                 &ddrmr->cr[121]);
 206         writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
 207                 DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
 208         writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
 209                 &ddrmr->cr[123]);
 210         writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
 211
 212         writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
 213         writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
 214                 &ddrmr->cr[132]);
 215         writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
 216                 DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
 217                 &ddrmr->cr[139]);
 218
 219         writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
 220                 DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
 221         writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
 222                 &ddrmr->cr[155]);
 223         writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
 224
 225         ddr_phy_init();
 226
 227         writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 228
 229         udelay(200);
 230 }
 231
 232 int dram_init(void)
 233 {
 234         setup_iomux_ddr();
 235
 236         ddr_ctrl_init();
 237         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 238
 239         return 0;
 240 }
 241
 242 static void setup_iomux_uart(void)
 243 {
 244         static const iomux_v3_cfg_t uart1_pads[] = {
 245                 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
 246                 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
 247         };
 248
 249         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 250 }
 251
 252 static void setup_iomux_enet(void)
 253 {
 254         static const iomux_v3_cfg_t enet0_pads[] = {
 255                 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
 256                 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
 257                 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
 258                 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
 259                 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
 260                 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
 261                 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
 262                 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
 263                 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
 264                 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
 265         };
 266
 267         imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 268 }
 269
 270 #ifdef CONFIG_FSL_ESDHC
 271 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 272         {ESDHC1_BASE_ADDR},
 273 };
 274
 275 int board_mmc_getcd(struct mmc *mmc)
 276 {
 277         /* eSDHC1 is always present */
 278         return 1;
 279 }
 280
 281 int board_mmc_init(bd_t *bis)
 282 {
 283         static const iomux_v3_cfg_t esdhc1_pads[] = {
 284                 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
 285                 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
 286                 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
 287                 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
 288                 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
 289                 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
 290         };
 291
 292         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 293
 294         imx_iomux_v3_setup_multiple_pads(
 295                 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
 296
 297         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 298 }
 299 #endif
 300
 301 static void clock_init(void)
 302 {
 303         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 304         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 305
 306         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 307                 CCM_CCGR0_UART1_CTRL_MASK);
 308         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 309                 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 310         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 311                 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 312                 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 313                 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
 314         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 315                 CCM_CCGR3_ANADIG_CTRL_MASK);
 316         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 317                 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 318                 CCM_CCGR4_GPC_CTRL_MASK);
 319         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 320                 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 321         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 322                 CCM_CCGR7_SDHC1_CTRL_MASK);
 323         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 324                 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 325
 326         clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 327                 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
 328         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 329                 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 330
 331         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 332                 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 333         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 334                 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
 335                 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
 336                 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
 337                 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 338                 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 339                 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 340         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 341                 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 342                 CCM_CACRR_ARM_CLK_DIV(0));
 343         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 344                 CCM_CSCMR1_ESDHC1_CLK_SEL(3));
 345         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 346                 CCM_CSCDR1_RMII_CLK_EN);
 347         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 348                 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
 349         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 350                 CCM_CSCMR2_RMII_CLK_SEL(0));
 351 }
 352
 353 static void mscm_init(void)
 354 {
 355         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 356         int i;
 357
 358         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 359                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 360 }
 361
 362 int board_phy_config(struct phy_device *phydev)
 363 {
 364         if (phydev->drv->config)
 365                 phydev->drv->config(phydev);
 366
 367         return 0;
 368 }
 369
 370 int board_early_init_f(void)
 371 {
 372         clock_init();
 373         mscm_init();
 374
 375         setup_iomux_uart();
 376         setup_iomux_enet();
 377
 378         return 0;
 379 }
 380
 381 int board_init(void)
 382 {
 383         /* address of boot parameters */
 384         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 385
 386         return 0;
 387 }
 388
 389 int checkboard(void)
 390 {
 391         puts("Board: vf610twr\n");
 392
 393         return 0;
 394 }