board/freescale/vf610twr/vf610twr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #include <common.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/iomux-vf610.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/arch/clock.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <miiphy.h>
  29 #include <netdev.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  34                         PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
  35
  36 #define ESDHC_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  37                         PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
  38
  39 #define ENET_PAD_CTRL   (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
  40                         PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
  41
  42 void setup_iomux_ddr(void)
  43 {
  44         static const iomux_v3_cfg_t ddr_pads[] = {
  45                 VF610_PAD_DDR_A15__DDR_A_15,
  46                 VF610_PAD_DDR_A15__DDR_A_15,
  47                 VF610_PAD_DDR_A14__DDR_A_14,
  48                 VF610_PAD_DDR_A13__DDR_A_13,
  49                 VF610_PAD_DDR_A12__DDR_A_12,
  50                 VF610_PAD_DDR_A11__DDR_A_11,
  51                 VF610_PAD_DDR_A10__DDR_A_10,
  52                 VF610_PAD_DDR_A9__DDR_A_9,
  53                 VF610_PAD_DDR_A8__DDR_A_8,
  54                 VF610_PAD_DDR_A7__DDR_A_7,
  55                 VF610_PAD_DDR_A6__DDR_A_6,
  56                 VF610_PAD_DDR_A5__DDR_A_5,
  57                 VF610_PAD_DDR_A4__DDR_A_4,
  58                 VF610_PAD_DDR_A3__DDR_A_3,
  59                 VF610_PAD_DDR_A2__DDR_A_2,
  60                 VF610_PAD_DDR_A1__DDR_A_1,
  61                 VF610_PAD_DDR_BA2__DDR_BA_2,
  62                 VF610_PAD_DDR_BA1__DDR_BA_1,
  63                 VF610_PAD_DDR_BA0__DDR_BA_0,
  64                 VF610_PAD_DDR_CAS__DDR_CAS_B,
  65                 VF610_PAD_DDR_CKE__DDR_CKE_0,
  66                 VF610_PAD_DDR_CLK__DDR_CLK_0,
  67                 VF610_PAD_DDR_CS__DDR_CS_B_0,
  68                 VF610_PAD_DDR_D15__DDR_D_15,
  69                 VF610_PAD_DDR_D14__DDR_D_14,
  70                 VF610_PAD_DDR_D13__DDR_D_13,
  71                 VF610_PAD_DDR_D12__DDR_D_12,
  72                 VF610_PAD_DDR_D11__DDR_D_11,
  73                 VF610_PAD_DDR_D10__DDR_D_10,
  74                 VF610_PAD_DDR_D9__DDR_D_9,
  75                 VF610_PAD_DDR_D8__DDR_D_8,
  76                 VF610_PAD_DDR_D7__DDR_D_7,
  77                 VF610_PAD_DDR_D6__DDR_D_6,
  78                 VF610_PAD_DDR_D5__DDR_D_5,
  79                 VF610_PAD_DDR_D4__DDR_D_4,
  80                 VF610_PAD_DDR_D3__DDR_D_3,
  81                 VF610_PAD_DDR_D2__DDR_D_2,
  82                 VF610_PAD_DDR_D1__DDR_D_1,
  83                 VF610_PAD_DDR_D0__DDR_D_0,
  84                 VF610_PAD_DDR_DQM1__DDR_DQM_1,
  85                 VF610_PAD_DDR_DQM0__DDR_DQM_0,
  86                 VF610_PAD_DDR_DQS1__DDR_DQS_1,
  87                 VF610_PAD_DDR_DQS0__DDR_DQS_0,
  88                 VF610_PAD_DDR_RAS__DDR_RAS_B,
  89                 VF610_PAD_DDR_WE__DDR_WE_B,
  90                 VF610_PAD_DDR_ODT1__DDR_ODT_0,
  91                 VF610_PAD_DDR_ODT0__DDR_ODT_1,
  92         };
  93
  94         imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
  95 }
  96
  97 void ddr_phy_init(void)
  98 {
  99         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 100
 101         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
 102         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
 103         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
 104         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
 105
 106         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
 107         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
 108         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
 109         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
 110
 111         writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
 112         writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
 113         writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
 114         writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
 115
 116         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
 117         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
 118         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
 119         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
 120
 121         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
 122         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
 123         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
 124         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
 125
 126         writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
 127                 &ddrmr->phy[50]);
 128 }
 129
 130 void ddr_ctrl_init(void)
 131 {
 132         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 133
 134         writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
 135         writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
 136         writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
 137
 138         writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
 139         writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
 140         writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
 141                 DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
 142         writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
 143                 DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
 144         writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
 145         writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
 146                 &ddrmr->cr[17]);
 147         writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
 148
 149         writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
 150         writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
 151                 DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
 152
 153         writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
 154         writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
 155         writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
 156
 157         writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
 158         writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
 159         writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
 160         writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
 161
 162         writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
 163         writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
 164         writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
 165         writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
 166
 167         writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
 168         writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
 169                 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
 170
 171         writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
 172         writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
 173                 &ddrmr->cr[48]);
 174
 175         writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
 176         writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
 177         writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 178
 179         writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
 180         writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
 181
 182         writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
 183                 DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
 184         writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
 185                 DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
 186                 &ddrmr->cr[74]);
 187         writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
 188                 DDRMC_CR75_PLEN, &ddrmr->cr[75]);
 189         writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
 190                 DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
 191         writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
 192                 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
 193         writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
 194         writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
 195
 196         writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 197
 198         writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
 199                 &ddrmr->cr[87]);
 200         writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
 201         writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
 202
 203         writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
 204         writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
 205
 206         writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
 207         writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
 208         writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
 209
 210         writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
 211                 &ddrmr->cr[117]);
 212         writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
 213                 &ddrmr->cr[118]);
 214
 215         writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
 216                 &ddrmr->cr[120]);
 217         writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
 218                 &ddrmr->cr[121]);
 219         writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
 220                 DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
 221         writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
 222                 &ddrmr->cr[123]);
 223         writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
 224
 225         writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
 226         writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
 227                 &ddrmr->cr[132]);
 228         writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
 229                 DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
 230                 &ddrmr->cr[139]);
 231
 232         writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
 233                 DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
 234         writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
 235                 &ddrmr->cr[155]);
 236         writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
 237
 238         ddr_phy_init();
 239
 240         writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 241
 242         udelay(200);
 243 }
 244
 245 int dram_init(void)
 246 {
 247         setup_iomux_ddr();
 248
 249         ddr_ctrl_init();
 250         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 251
 252         return 0;
 253 }
 254
 255 static void setup_iomux_uart(void)
 256 {
 257         static const iomux_v3_cfg_t uart1_pads[] = {
 258                 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
 259                 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
 260         };
 261
 262         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 263 }
 264
 265 static void setup_iomux_enet(void)
 266 {
 267         static const iomux_v3_cfg_t enet0_pads[] = {
 268                 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
 269                 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
 270                 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
 271                 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
 272                 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
 273                 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
 274                 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
 275                 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
 276                 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
 277                 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
 278         };
 279
 280         imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 281 }
 282
 283 #ifdef CONFIG_FSL_ESDHC
 284 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 285         {ESDHC1_BASE_ADDR},
 286 };
 287
 288 int board_mmc_getcd(struct mmc *mmc)
 289 {
 290         /* eSDHC1 is always present */
 291         return 1;
 292 }
 293
 294 int board_mmc_init(bd_t *bis)
 295 {
 296         static const iomux_v3_cfg_t esdhc1_pads[] = {
 297                 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
 298                 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
 299                 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
 300                 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
 301                 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
 302                 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
 303         };
 304         s32 status = 0;
 305
 306         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 307
 308         imx_iomux_v3_setup_multiple_pads(
 309                 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
 310
 311         status |= fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 312
 313         return status;
 314 }
 315 #endif
 316
 317 static void clock_init(void)
 318 {
 319         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 320         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 321
 322         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 323                 CCM_CCGR0_UART1_CTRL_MASK);
 324         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 325                 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 326         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 327                 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 328                 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 329                 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
 330         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 331                 CCM_CCGR3_ANADIG_CTRL_MASK);
 332         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 333                 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 334                 CCM_CCGR4_GPC_CTRL_MASK);
 335         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 336                 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 337         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 338                 CCM_CCGR7_SDHC1_CTRL_MASK);
 339         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 340                 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 341
 342         clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 343                 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
 344         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 345                 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 346
 347         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 348                 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 349         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 350                 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
 351                 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
 352                 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
 353                 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 354                 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 355                 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 356         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 357                 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 358                 CCM_CACRR_ARM_CLK_DIV(0));
 359         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 360                 CCM_CSCMR1_ESDHC1_CLK_SEL(3));
 361         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 362                 CCM_CSCDR1_RMII_CLK_EN);
 363         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 364                 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
 365         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 366                 CCM_CSCMR2_RMII_CLK_SEL(0));
 367 }
 368
 369 static void mscm_init(void)
 370 {
 371         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 372         int i;
 373
 374         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 375                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 376 }
 377
 378 int board_phy_config(struct phy_device *phydev)
 379 {
 380         if (phydev->drv->config)
 381                 phydev->drv->config(phydev);
 382
 383         return 0;
 384 }
 385
 386 int board_early_init_f(void)
 387 {
 388         clock_init();
 389         mscm_init();
 390
 391         setup_iomux_uart();
 392         setup_iomux_enet();
 393
 394         return 0;
 395 }
 396
 397 int board_init(void)
 398 {
 399         /* address of boot parameters */
 400         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 401
 402         return 0;
 403 }
 404
 405 int checkboard(void)
 406 {
 407         puts("Board: vf610twr\n");
 408
 409         return 0;
 410 }