board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/video.h>
  24 #include <jffs2/load_kernel.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <linux/ctype.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <mmc.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "ventana_eeprom.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO's common to all baseboards */
  47 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  48 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  49 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  50 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  51 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  52
  53 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  54         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  55         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  59         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  63         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  64
  65 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  66         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  67         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  68
  69 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  70         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  71         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  72
  73 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  74         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  75         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  76
  77 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  78         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  79         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  80
  81 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  82
  83
  84 /*
  85  * EEPROM board info struct populated by read_eeprom so that we only have to
  86  * read it once.
  87  */
  88 struct ventana_board_info ventana_info;
  89
  90 int board_type;
  91
  92 /* UART1: Function varies per baseboard */
  93 iomux_v3_cfg_t const uart1_pads[] = {
  94         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  95         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  96 };
  97
  98 /* UART2: Serial Console */
  99 iomux_v3_cfg_t const uart2_pads[] = {
 100         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 101         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 102 };
 103
 104 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 105
 106 /* I2C1: GSC */
 107 struct i2c_pads_info mx6q_i2c_pad_info0 = {
 108         .scl = {
 109                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 110                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 111                 .gp = IMX_GPIO_NR(3, 21)
 112         },
 113         .sda = {
 114                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 115                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 116                 .gp = IMX_GPIO_NR(3, 28)
 117         }
 118 };
 119 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 120         .scl = {
 121                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 122                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 123                 .gp = IMX_GPIO_NR(3, 21)
 124         },
 125         .sda = {
 126                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 127                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 128                 .gp = IMX_GPIO_NR(3, 28)
 129         }
 130 };
 131
 132 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 133 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 134         .scl = {
 135                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 136                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 137                 .gp = IMX_GPIO_NR(4, 12)
 138         },
 139         .sda = {
 140                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 141                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 142                 .gp = IMX_GPIO_NR(4, 13)
 143         }
 144 };
 145 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 146         .scl = {
 147                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 148                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 149                 .gp = IMX_GPIO_NR(4, 12)
 150         },
 151         .sda = {
 152                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 153                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 154                 .gp = IMX_GPIO_NR(4, 13)
 155         }
 156 };
 157
 158 /* I2C3: Misc/Expansion */
 159 struct i2c_pads_info mx6q_i2c_pad_info2 = {
 160         .scl = {
 161                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 162                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 163                 .gp = IMX_GPIO_NR(1, 3)
 164         },
 165         .sda = {
 166                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 167                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 168                 .gp = IMX_GPIO_NR(1, 6)
 169         }
 170 };
 171 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 172         .scl = {
 173                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 174                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 175                 .gp = IMX_GPIO_NR(1, 3)
 176         },
 177         .sda = {
 178                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 179                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 180                 .gp = IMX_GPIO_NR(1, 6)
 181         }
 182 };
 183
 184 /* MMC */
 185 iomux_v3_cfg_t const usdhc3_pads[] = {
 186         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 187         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 188         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 190         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         /* CD */
 193         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 194 };
 195
 196 /* ENET */
 197 iomux_v3_cfg_t const enet_pads[] = {
 198         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 199         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 200         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 206                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 208                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 210         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 212         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 215                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         /* PHY nRST */
 217         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 218 };
 219
 220 /* NAND */
 221 iomux_v3_cfg_t const nfc_pads[] = {
 222         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 223         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 224         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237 };
 238
 239 #ifdef CONFIG_CMD_NAND
 240 static void setup_gpmi_nand(void)
 241 {
 242         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 243
 244         /* config gpmi nand iomux */
 245         SETUP_IOMUX_PADS(nfc_pads);
 246
 247         /* config gpmi and bch clock to 100 MHz */
 248         clrsetbits_le32(&mxc_ccm->cs2cdr,
 249                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 250                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 251                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 252                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 253                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 254                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 255
 256         /* enable gpmi and bch clock gating */
 257         setbits_le32(&mxc_ccm->CCGR4,
 258                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 259                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 260                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 261                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 262                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 263
 264         /* enable apbh clock gating */
 265         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 266 }
 267 #endif
 268
 269 static void setup_iomux_enet(void)
 270 {
 271         SETUP_IOMUX_PADS(enet_pads);
 272
 273         /* toggle PHY_RST# */
 274         gpio_direction_output(GP_PHY_RST, 0);
 275         mdelay(2);
 276         gpio_set_value(GP_PHY_RST, 1);
 277 }
 278
 279 static void setup_iomux_uart(void)
 280 {
 281         SETUP_IOMUX_PADS(uart1_pads);
 282         SETUP_IOMUX_PADS(uart2_pads);
 283 }
 284
 285 #ifdef CONFIG_USB_EHCI_MX6
 286 iomux_v3_cfg_t const usb_pads[] = {
 287         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 288         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 289         /* OTG PWR */
 290         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 291 };
 292
 293 int board_ehci_hcd_init(int port)
 294 {
 295         struct ventana_board_info *info = &ventana_info;
 296
 297         SETUP_IOMUX_PADS(usb_pads);
 298
 299         /* Reset USB HUB (present on GW54xx/GW53xx) */
 300         switch (info->model[3]) {
 301         case '3': /* GW53xx */
 302                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 303                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 304                 mdelay(2);
 305                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 306                 break;
 307         case '4': /* GW54xx */
 308                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 309                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 310                 mdelay(2);
 311                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 312                 break;
 313         }
 314
 315         return 0;
 316 }
 317
 318 int board_ehci_power(int port, int on)
 319 {
 320         if (port)
 321                 return 0;
 322         gpio_set_value(GP_USB_OTG_PWR, on);
 323         return 0;
 324 }
 325 #endif /* CONFIG_USB_EHCI_MX6 */
 326
 327 #ifdef CONFIG_FSL_ESDHC
 328 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 329
 330 int board_mmc_getcd(struct mmc *mmc)
 331 {
 332         /* Card Detect */
 333         gpio_direction_input(GP_SD3_CD);
 334         return !gpio_get_value(GP_SD3_CD);
 335 }
 336
 337 int board_mmc_init(bd_t *bis)
 338 {
 339         /* Only one USDHC controller on Ventana */
 340         SETUP_IOMUX_PADS(usdhc3_pads);
 341         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 342         usdhc_cfg.max_bus_width = 4;
 343
 344         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 345 }
 346 #endif /* CONFIG_FSL_ESDHC */
 347
 348 #ifdef CONFIG_MXC_SPI
 349 iomux_v3_cfg_t const ecspi1_pads[] = {
 350         /* SS1 */
 351         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 352         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 353         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 354         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 355 };
 356
 357 static void setup_spi(void)
 358 {
 359         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 360         SETUP_IOMUX_PADS(ecspi1_pads);
 361 }
 362 #endif
 363
 364 /* configure eth0 PHY board-specific LED behavior */
 365 int board_phy_config(struct phy_device *phydev)
 366 {
 367         unsigned short val;
 368
 369         /* Marvel 88E1510 */
 370         if (phydev->phy_id == 0x1410dd1) {
 371                 /*
 372                  * Page 3, Register 16: LED[2:0] Function Control Register
 373                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 374                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 375                  */
 376                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 377                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 378                 val &= 0xff00;
 379                 val |= 0x0017;
 380                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 381                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 382         }
 383
 384         if (phydev->drv->config)
 385                 phydev->drv->config(phydev);
 386
 387         return 0;
 388 }
 389
 390 int board_eth_init(bd_t *bis)
 391 {
 392         setup_iomux_enet();
 393
 394 #ifdef CONFIG_FEC_MXC
 395         cpu_eth_init(bis);
 396 #endif
 397
 398 #ifdef CONFIG_CI_UDC
 399         /* For otg ethernet*/
 400         usb_eth_initialize(bis);
 401 #endif
 402
 403         return 0;
 404 }
 405
 406 #if defined(CONFIG_VIDEO_IPUV3)
 407
 408 static void enable_hdmi(struct display_info_t const *dev)
 409 {
 410         imx_enable_hdmi_phy();
 411 }
 412
 413 static int detect_i2c(struct display_info_t const *dev)
 414 {
 415         return i2c_set_bus_num(dev->bus) == 0 &&
 416                 i2c_probe(dev->addr) == 0;
 417 }
 418
 419 static void enable_lvds(struct display_info_t const *dev)
 420 {
 421         struct iomuxc *iomux = (struct iomuxc *)
 422                                 IOMUXC_BASE_ADDR;
 423
 424         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 425         u32 reg = readl(&iomux->gpr[2]);
 426         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 427         writel(reg, &iomux->gpr[2]);
 428
 429         /* Enable Backlight */
 430         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 431         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 432 }
 433
 434 struct display_info_t const displays[] = {{
 435         /* HDMI Output */
 436         .bus    = -1,
 437         .addr   = 0,
 438         .pixfmt = IPU_PIX_FMT_RGB24,
 439         .detect = detect_hdmi,
 440         .enable = enable_hdmi,
 441         .mode   = {
 442                 .name           = "HDMI",
 443                 .refresh        = 60,
 444                 .xres           = 1024,
 445                 .yres           = 768,
 446                 .pixclock       = 15385,
 447                 .left_margin    = 220,
 448                 .right_margin   = 40,
 449                 .upper_margin   = 21,
 450                 .lower_margin   = 7,
 451                 .hsync_len      = 60,
 452                 .vsync_len      = 10,
 453                 .sync           = FB_SYNC_EXT,
 454                 .vmode          = FB_VMODE_NONINTERLACED
 455 } }, {
 456         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 457         .bus    = 2,
 458         .addr   = 0x4,
 459         .pixfmt = IPU_PIX_FMT_LVDS666,
 460         .detect = detect_i2c,
 461         .enable = enable_lvds,
 462         .mode   = {
 463                 .name           = "Hannstar-XGA",
 464                 .refresh        = 60,
 465                 .xres           = 1024,
 466                 .yres           = 768,
 467                 .pixclock       = 15385,
 468                 .left_margin    = 220,
 469                 .right_margin   = 40,
 470                 .upper_margin   = 21,
 471                 .lower_margin   = 7,
 472                 .hsync_len      = 60,
 473                 .vsync_len      = 10,
 474                 .sync           = FB_SYNC_EXT,
 475                 .vmode          = FB_VMODE_NONINTERLACED
 476 } } };
 477 size_t display_count = ARRAY_SIZE(displays);
 478
 479 static void setup_display(void)
 480 {
 481         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 482         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 483         int reg;
 484
 485         enable_ipu_clock();
 486         imx_setup_hdmi();
 487         /* Turn on LDB0,IPU,IPU DI0 clocks */
 488         reg = __raw_readl(&mxc_ccm->CCGR3);
 489         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 490         writel(reg, &mxc_ccm->CCGR3);
 491
 492         /* set LDB0, LDB1 clk select to 011/011 */
 493         reg = readl(&mxc_ccm->cs2cdr);
 494         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 495                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 496         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 497               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 498         writel(reg, &mxc_ccm->cs2cdr);
 499
 500         reg = readl(&mxc_ccm->cscmr2);
 501         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 502         writel(reg, &mxc_ccm->cscmr2);
 503
 504         reg = readl(&mxc_ccm->chsccdr);
 505         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 506                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 507         writel(reg, &mxc_ccm->chsccdr);
 508
 509         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 510              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 511              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 512              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 513              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 514              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 515              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 516              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 517              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 518         writel(reg, &iomux->gpr[2]);
 519
 520         reg = readl(&iomux->gpr[3]);
 521         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 522             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 523                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 524         writel(reg, &iomux->gpr[3]);
 525
 526         /* Backlight CABEN on LVDS connector */
 527         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 528         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 529 }
 530 #endif /* CONFIG_VIDEO_IPUV3 */
 531
 532 /*
 533  * Baseboard specific GPIO
 534  */
 535
 536 /* common to add baseboards */
 537 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 538         /* MSATA_EN */
 539         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 540         /* RS232_EN# */
 541         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 542 };
 543
 544 /* prototype */
 545 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 546         /* PANLEDG# */
 547         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 548         /* PANLEDR# */
 549         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 550         /* LOCLED# */
 551         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 552         /* RS485_EN */
 553         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 554         /* IOEXP_PWREN# */
 555         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 556         /* IOEXP_IRQ# */
 557         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 558         /* VID_EN */
 559         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 560         /* DIOI2C_DIS# */
 561         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 562         /* PCICK_SSON */
 563         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 564         /* PCI_RST# */
 565         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 566 };
 567
 568 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 569         /* PANLEDG# */
 570         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 571         /* PANLEDR# */
 572         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 573         /* IOEXP_PWREN# */
 574         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 575         /* IOEXP_IRQ# */
 576         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 577
 578         /* GPS_SHDN */
 579         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 580         /* VID_PWR */
 581         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 582         /* PCI_RST# */
 583         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 584         /* PCIESKT_WDIS# */
 585         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 586 };
 587
 588 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 589         /* PANLEDG# */
 590         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 591         /* PANLEDR# */
 592         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 593         /* IOEXP_PWREN# */
 594         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 595         /* IOEXP_IRQ# */
 596         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 597
 598         /* MX6_LOCLED# */
 599         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 600         /* GPS_SHDN */
 601         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 602         /* USBOTG_SEL */
 603         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 604         /* VID_PWR */
 605         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 606         /* PCI_RST# */
 607         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 608         /* PCIESKT_WDIS# */
 609         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 610 };
 611
 612 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 613         /* PANLEDG# */
 614         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 615         /* PANLEDR# */
 616         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 617         /* IOEXP_PWREN# */
 618         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 619         /* IOEXP_IRQ# */
 620         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 621         /* DIOI2C_DIS# */
 622         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 623
 624         /* MX6_LOCLED# */
 625         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 626         /* GPS_SHDN */
 627         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 628         /* VID_EN */
 629         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 630         /* PCI_RST# */
 631         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 632         /* PCIESKT_WDIS# */
 633         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 634 };
 635
 636 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 637         /* PANLEDG# */
 638         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 639         /* PANLEDR# */
 640         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 641         /* MX6_LOCLED# */
 642         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 643         /* MIPI_DIO */
 644         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 645         /* RS485_EN */
 646         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 647         /* IOEXP_PWREN# */
 648         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 649         /* IOEXP_IRQ# */
 650         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 651         /* DIOI2C_DIS# */
 652         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 653         /* PCICK_SSON */
 654         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 655         /* PCI_RST# */
 656         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 657         /* VID_EN */
 658         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 659         /* PCIESKT_WDIS# */
 660         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 661 };
 662
 663 /*
 664  * each baseboard has 4 user configurable Digital IO lines which can
 665  * be pinmuxed as a GPIO or in some cases a PWM
 666  */
 667 struct dio_cfg {
 668         iomux_v3_cfg_t gpio_padmux[2];
 669         unsigned gpio_param;
 670         iomux_v3_cfg_t pwm_padmux[2];
 671         unsigned pwm_param;
 672 };
 673
 674 struct ventana {
 675         /* pinmux */
 676         iomux_v3_cfg_t const *gpio_pads;
 677         int num_pads;
 678         /* DIO pinmux/val */
 679         struct dio_cfg dio_cfg[4];
 680         /* various gpios (0 if non-existent) */
 681         int leds[3];
 682         int pcie_rst;
 683         int mezz_pwren;
 684         int mezz_irq;
 685         int rs485en;
 686         int gps_shdn;
 687         int vidin_en;
 688         int dioi2c_en;
 689         int pcie_sson;
 690         int usb_sel;
 691         int wdis;
 692 };
 693
 694 struct ventana gpio_cfg[] = {
 695         /* GW5400proto */
 696         {
 697                 .gpio_pads = gw54xx_gpio_pads,
 698                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 699                 .dio_cfg = {
 700                         {
 701                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 702                                 IMX_GPIO_NR(1, 9),
 703                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 704                                 1
 705                         },
 706                         {
 707                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 708                                 IMX_GPIO_NR(1, 19),
 709                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 710                                 2
 711                         },
 712                         {
 713                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 714                                 IMX_GPIO_NR(2, 9),
 715                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 716                                 3
 717                         },
 718                         {
 719                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 720                                 IMX_GPIO_NR(2, 10),
 721                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 722                                 4
 723                         },
 724                 },
 725                 .leds = {
 726                         IMX_GPIO_NR(4, 6),
 727                         IMX_GPIO_NR(4, 10),
 728                         IMX_GPIO_NR(4, 15),
 729                 },
 730                 .pcie_rst = IMX_GPIO_NR(1, 29),
 731                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 732                 .mezz_irq = IMX_GPIO_NR(4, 9),
 733                 .rs485en = IMX_GPIO_NR(3, 24),
 734                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 735                 .pcie_sson = IMX_GPIO_NR(1, 20),
 736         },
 737
 738         /* GW51xx */
 739         {
 740                 .gpio_pads = gw51xx_gpio_pads,
 741                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 742                 .dio_cfg = {
 743                         {
 744                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 745                                 IMX_GPIO_NR(1, 16),
 746                                 { 0, 0 },
 747                                 0
 748                         },
 749                         {
 750                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 751                                 IMX_GPIO_NR(1, 19),
 752                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 753                                 2
 754                         },
 755                         {
 756                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 757                                 IMX_GPIO_NR(1, 17),
 758                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 759                                 3
 760                         },
 761                         {
 762                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 763                                 IMX_GPIO_NR(1, 18),
 764                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 765                                 4
 766                         },
 767                 },
 768                 .leds = {
 769                         IMX_GPIO_NR(4, 6),
 770                         IMX_GPIO_NR(4, 10),
 771                 },
 772                 .pcie_rst = IMX_GPIO_NR(1, 0),
 773                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 774                 .mezz_irq = IMX_GPIO_NR(2, 18),
 775                 .gps_shdn = IMX_GPIO_NR(1, 2),
 776                 .vidin_en = IMX_GPIO_NR(5, 20),
 777                 .wdis = IMX_GPIO_NR(7, 12),
 778         },
 779
 780         /* GW52xx */
 781         {
 782                 .gpio_pads = gw52xx_gpio_pads,
 783                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 784                 .dio_cfg = {
 785                         {
 786                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 787                                 IMX_GPIO_NR(1, 16),
 788                                 { 0, 0 },
 789                                 0
 790                         },
 791                         {
 792                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 793                                 IMX_GPIO_NR(1, 19),
 794                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 795                                 2
 796                         },
 797                         {
 798                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 799                                 IMX_GPIO_NR(1, 17),
 800                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 801                                 3
 802                         },
 803                         {
 804                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 805                                 IMX_GPIO_NR(1, 20),
 806                                 { 0, 0 },
 807                                 0
 808                         },
 809                 },
 810                 .leds = {
 811                         IMX_GPIO_NR(4, 6),
 812                         IMX_GPIO_NR(4, 7),
 813                         IMX_GPIO_NR(4, 15),
 814                 },
 815                 .pcie_rst = IMX_GPIO_NR(1, 29),
 816                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 817                 .mezz_irq = IMX_GPIO_NR(2, 18),
 818                 .gps_shdn = IMX_GPIO_NR(1, 27),
 819                 .vidin_en = IMX_GPIO_NR(3, 31),
 820                 .usb_sel = IMX_GPIO_NR(1, 2),
 821                 .wdis = IMX_GPIO_NR(7, 12),
 822         },
 823
 824         /* GW53xx */
 825         {
 826                 .gpio_pads = gw53xx_gpio_pads,
 827                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 828                 .dio_cfg = {
 829                         {
 830                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 831                                 IMX_GPIO_NR(1, 16),
 832                                 { 0, 0 },
 833                                 0
 834                         },
 835                         {
 836                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 837                                 IMX_GPIO_NR(1, 19),
 838                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 839                                 2
 840                         },
 841                         {
 842                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 843                                 IMX_GPIO_NR(1, 17),
 844                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 845                                 3
 846                         },
 847                         {
 848                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 849                                 IMX_GPIO_NR(1, 20),
 850                                 { 0, 0 },
 851                                 0
 852                         },
 853                 },
 854                 .leds = {
 855                         IMX_GPIO_NR(4, 6),
 856                         IMX_GPIO_NR(4, 7),
 857                         IMX_GPIO_NR(4, 15),
 858                 },
 859                 .pcie_rst = IMX_GPIO_NR(1, 29),
 860                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 861                 .mezz_irq = IMX_GPIO_NR(2, 18),
 862                 .gps_shdn = IMX_GPIO_NR(1, 27),
 863                 .vidin_en = IMX_GPIO_NR(3, 31),
 864                 .wdis = IMX_GPIO_NR(7, 12),
 865         },
 866
 867         /* GW54xx */
 868         {
 869                 .gpio_pads = gw54xx_gpio_pads,
 870                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 871                 .dio_cfg = {
 872                         {
 873                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 874                                 IMX_GPIO_NR(1, 9),
 875                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 876                                 1
 877                         },
 878                         {
 879                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 880                                 IMX_GPIO_NR(1, 19),
 881                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 882                                 2
 883                         },
 884                         {
 885                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 886                                 IMX_GPIO_NR(2, 9),
 887                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 888                                 3
 889                         },
 890                         {
 891                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 892                                 IMX_GPIO_NR(2, 10),
 893                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 894                                 4
 895                         },
 896                 },
 897                 .leds = {
 898                         IMX_GPIO_NR(4, 6),
 899                         IMX_GPIO_NR(4, 7),
 900                         IMX_GPIO_NR(4, 15),
 901                 },
 902                 .pcie_rst = IMX_GPIO_NR(1, 29),
 903                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 904                 .mezz_irq = IMX_GPIO_NR(2, 18),
 905                 .rs485en = IMX_GPIO_NR(7, 1),
 906                 .vidin_en = IMX_GPIO_NR(3, 31),
 907                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 908                 .pcie_sson = IMX_GPIO_NR(1, 20),
 909                 .wdis = IMX_GPIO_NR(5, 17),
 910         },
 911 };
 912
 913 /* setup board specific PMIC */
 914 int power_init_board(void)
 915 {
 916         struct pmic *p;
 917         u32 reg;
 918
 919         /* configure PFUZE100 PMIC */
 920         if (board_type == GW54xx || board_type == GW54proto) {
 921                 power_pfuze100_init(CONFIG_I2C_PMIC);
 922                 p = pmic_get("PFUZE100");
 923                 if (p && !pmic_probe(p)) {
 924                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 925                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 926
 927                         /* Set VGEN1 to 1.5V and enable */
 928                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
 929                         reg &= ~(LDO_VOL_MASK);
 930                         reg |= (LDOA_1_50V | LDO_EN);
 931                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
 932
 933                         /* Set SWBST to 5.0V and enable */
 934                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
 935                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
 936                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
 937                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
 938                 }
 939         }
 940
 941         /* configure LTC3676 PMIC */
 942         else {
 943                 power_ltc3676_init(CONFIG_I2C_PMIC);
 944                 p = pmic_get("LTC3676_PMIC");
 945                 if (p && !pmic_probe(p)) {
 946                         puts("PMIC:  LTC3676\n");
 947                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
 948                         if (is_cpu_type(MXC_CPU_MX6Q)) {
 949                                 /* mask PGOOD during SW1 transition */
 950                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 951                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
 952                                 /* set SW1 (VDD_SOC) to 1259mV */
 953                                 reg = 0x1d;
 954                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
 955
 956                                 /* mask PGOOD during SW3 transition */
 957                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 958                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
 959                                 /*set SW3 (VDD_ARM) to 1259mV */
 960                                 reg = 0x1d;
 961                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
 962                         }
 963                 }
 964         }
 965
 966         return 0;
 967 }
 968
 969 /* setup GPIO pinmux and default configuration per baseboard */
 970 static void setup_board_gpio(int board)
 971 {
 972         struct ventana_board_info *info = &ventana_info;
 973         const char *s;
 974         char arg[10];
 975         size_t len;
 976         int i;
 977         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
 978
 979         if (board >= GW_UNKNOWN)
 980                 return;
 981
 982         /* RS232_EN# */
 983         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 984
 985         /* MSATA Enable */
 986         if (is_cpu_type(MXC_CPU_MX6Q) &&
 987             test_bit(EECONFIG_SATA, info->config)) {
 988                 gpio_direction_output(GP_MSATA_SEL,
 989                                       (hwconfig("msata")) ?  1 : 0);
 990         } else {
 991                 gpio_direction_output(GP_MSATA_SEL, 0);
 992         }
 993
 994 #if !defined(CONFIG_CMD_PCI)
 995         /* assert PCI_RST# (released by OS when clock is valid) */
 996         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
 997 #endif
 998
 999         /* turn off (active-high) user LED's */
1000         for (i = 0; i < 4; i++) {
1001                 if (gpio_cfg[board].leds[i])
1002                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1003         }
1004
1005         /* Expansion Mezzanine IO */
1006         gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1007         gpio_direction_input(gpio_cfg[board].mezz_irq);
1008
1009         /* RS485 Transmit Enable */
1010         if (gpio_cfg[board].rs485en)
1011                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1012
1013         /* GPS_SHDN */
1014         if (gpio_cfg[board].gps_shdn)
1015                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1016
1017         /* Analog video codec power enable */
1018         if (gpio_cfg[board].vidin_en)
1019                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1020
1021         /* DIOI2C_DIS# */
1022         if (gpio_cfg[board].dioi2c_en)
1023                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1024
1025         /* PCICK_SSON: disable spread-spectrum clock */
1026         if (gpio_cfg[board].pcie_sson)
1027                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1028
1029         /* USBOTG Select (PCISKT or FrontPanel) */
1030         if (gpio_cfg[board].usb_sel)
1031                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1032
1033         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1034         if (gpio_cfg[board].wdis)
1035                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1036
1037         /*
1038          * Configure DIO pinmux/padctl registers
1039          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1040          */
1041         for (i = 0; i < 4; i++) {
1042                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1043                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1044                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1045
1046                 sprintf(arg, "dio%d", i);
1047                 if (!hwconfig(arg))
1048                         continue;
1049                 s = hwconfig_subarg(arg, "padctrl", &len);
1050                 if (s) {
1051                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1052                                             & 0x1ffff) | MUX_MODE_SION;
1053                 }
1054                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1055                         if (!quiet) {
1056                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1057                                        (cfg->gpio_param/32)+1,
1058                                        cfg->gpio_param%32,
1059                                        cfg->gpio_param);
1060                         }
1061                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1062                                                ctrl);
1063                         gpio_direction_input(cfg->gpio_param);
1064                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1065                            cfg->pwm_padmux) {
1066                         if (!quiet)
1067                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1068                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1069                                                MUX_PAD_CTRL(ctrl));
1070                 }
1071         }
1072
1073         if (!quiet) {
1074                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1075                     (test_bit(EECONFIG_SATA, info->config))) {
1076                         printf("MSATA: %s\n", (hwconfig("msata") ?
1077                                "enabled" : "disabled"));
1078                 }
1079                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1080                        "enabled" : "disabled");
1081         }
1082 }
1083
1084 #if defined(CONFIG_CMD_PCI)
1085 int imx6_pcie_toggle_reset(void)
1086 {
1087         if (board_type < GW_UNKNOWN) {
1088                 uint pin = gpio_cfg[board_type].pcie_rst;
1089                 gpio_direction_output(pin, 0);
1090                 mdelay(50);
1091                 gpio_direction_output(pin, 1);
1092         }
1093         return 0;
1094 }
1095 #endif /* CONFIG_CMD_PCI */
1096
1097 #ifdef CONFIG_SERIAL_TAG
1098 /*
1099  * called when setting up ATAGS before booting kernel
1100  * populate serialnum from the following (in order of priority):
1101  *   serial# env var
1102  *   eeprom
1103  */
1104 void get_board_serial(struct tag_serialnr *serialnr)
1105 {
1106         char *serial = getenv("serial#");
1107
1108         if (serial) {
1109                 serialnr->high = 0;
1110                 serialnr->low = simple_strtoul(serial, NULL, 10);
1111         } else if (ventana_info.model[0]) {
1112                 serialnr->high = 0;
1113                 serialnr->low = ventana_info.serial;
1114         } else {
1115                 serialnr->high = 0;
1116                 serialnr->low = 0;
1117         }
1118 }
1119 #endif
1120
1121 /*
1122  * Board Support
1123  */
1124
1125 /* called from SPL board_init_f() */
1126 int board_early_init_f(void)
1127 {
1128         setup_iomux_uart();
1129         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1130
1131 #if defined(CONFIG_VIDEO_IPUV3)
1132         setup_display();
1133 #endif
1134         return 0;
1135 }
1136
1137 int dram_init(void)
1138 {
1139         gd->ram_size = imx_ddr_size();
1140         return 0;
1141 }
1142
1143 int board_init(void)
1144 {
1145         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1146
1147         clrsetbits_le32(&iomuxc_regs->gpr[1],
1148                         IOMUXC_GPR1_OTG_ID_MASK,
1149                         IOMUXC_GPR1_OTG_ID_GPIO1);
1150
1151         /* address of linux boot parameters */
1152         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1153
1154 #ifdef CONFIG_CMD_NAND
1155         setup_gpmi_nand();
1156 #endif
1157 #ifdef CONFIG_MXC_SPI
1158         setup_spi();
1159 #endif
1160         if (is_cpu_type(MXC_CPU_MX6Q)) {
1161                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1162                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1163                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1164         } else {
1165                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1166                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1167                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1168         }
1169
1170 #ifdef CONFIG_CMD_SATA
1171         setup_sata();
1172 #endif
1173         /* read Gateworks EEPROM into global struct (used later) */
1174         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1175
1176         /* board-specifc GPIO iomux */
1177         SETUP_IOMUX_PADS(gw_gpio_pads);
1178         if (board_type < GW_UNKNOWN) {
1179                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1180                 int count = gpio_cfg[board_type].num_pads;
1181
1182                 imx_iomux_v3_setup_multiple_pads(p, count);
1183         }
1184
1185         return 0;
1186 }
1187
1188 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1189 /*
1190  * called during late init (after relocation and after board_init())
1191  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1192  * EEPROM read.
1193  */
1194 int checkboard(void)
1195 {
1196         struct ventana_board_info *info = &ventana_info;
1197         unsigned char buf[4];
1198         const char *p;
1199         int quiet; /* Quiet or minimal output mode */
1200
1201         quiet = 0;
1202         p = getenv("quiet");
1203         if (p)
1204                 quiet = simple_strtol(p, NULL, 10);
1205         else
1206                 setenv("quiet", "0");
1207
1208         puts("\nGateworks Corporation Copyright 2014\n");
1209         if (info->model[0]) {
1210                 printf("Model: %s\n", info->model);
1211                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1212                        info->mfgdate[0], info->mfgdate[1],
1213                        info->mfgdate[2], info->mfgdate[3]);
1214                 printf("Serial:%d\n", info->serial);
1215         } else {
1216                 puts("Invalid EEPROM - board will not function fully\n");
1217         }
1218         if (quiet)
1219                 return 0;
1220
1221         /* Display GSC firmware revision/CRC/status */
1222         i2c_set_bus_num(CONFIG_I2C_GSC);
1223         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1224                 printf("GSC:   v%d", buf[0]);
1225                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1226                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1227                         printf(" 0x%02x", buf[0]); /* irq status */
1228                 }
1229                 puts("\n");
1230         }
1231         /* Display RTC */
1232         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1233                 printf("RTC:   %d\n",
1234                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1235         }
1236
1237         return 0;
1238 }
1239 #endif
1240
1241 #ifdef CONFIG_CMD_BMODE
1242 /*
1243  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1244  * see Table 8-11 and Table 5-9
1245  *  BOOT_CFG1[7] = 1 (boot from NAND)
1246  *  BOOT_CFG1[5] = 0 - raw NAND
1247  *  BOOT_CFG1[4] = 0 - default pad settings
1248  *  BOOT_CFG1[3:2] = 00 - devices = 1
1249  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1250  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1251  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1252  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1253  */
1254 static const struct boot_mode board_boot_modes[] = {
1255         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1256         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1257         { NULL, 0 },
1258 };
1259 #endif
1260
1261 /* late init */
1262 int misc_init_r(void)
1263 {
1264         struct ventana_board_info *info = &ventana_info;
1265         unsigned char reg;
1266
1267         /* set env vars based on EEPROM data */
1268         if (ventana_info.model[0]) {
1269                 char str[16], fdt[36];
1270                 char *p;
1271                 const char *cputype = "";
1272                 int i;
1273
1274                 /*
1275                  * FDT name will be prefixed with CPU type.  Three versions
1276                  * will be created each increasingly generic and bootloader
1277                  * env scripts will try loading each from most specific to
1278                  * least.
1279                  */
1280                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1281                     is_cpu_type(MXC_CPU_MX6D))
1282                         cputype = "imx6q";
1283                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1284                          is_cpu_type(MXC_CPU_MX6SOLO))
1285                         cputype = "imx6dl";
1286                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1287                         setenv("flash_layout", "large");
1288                 else
1289                         setenv("flash_layout", "normal");
1290                 memset(str, 0, sizeof(str));
1291                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1292                         str[i] = tolower(info->model[i]);
1293                 if (!getenv("model"))
1294                         setenv("model", str);
1295                 if (!getenv("fdt_file")) {
1296                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1297                         setenv("fdt_file", fdt);
1298                 }
1299                 p = strchr(str, '-');
1300                 if (p) {
1301                         *p++ = 0;
1302
1303                         setenv("model_base", str);
1304                         if (!getenv("fdt_file1")) {
1305                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1306                                 setenv("fdt_file1", fdt);
1307                         }
1308                         str[4] = 'x';
1309                         str[5] = 'x';
1310                         str[6] = 0;
1311                         if (!getenv("fdt_file2")) {
1312                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1313                                 setenv("fdt_file2", fdt);
1314                         }
1315                 }
1316
1317                 /* initialize env from EEPROM */
1318                 if (test_bit(EECONFIG_ETH0, info->config) &&
1319                     !getenv("ethaddr")) {
1320                         eth_setenv_enetaddr("ethaddr", info->mac0);
1321                 }
1322                 if (test_bit(EECONFIG_ETH1, info->config) &&
1323                     !getenv("eth1addr")) {
1324                         eth_setenv_enetaddr("eth1addr", info->mac1);
1325                 }
1326
1327                 /* board serial-number */
1328                 sprintf(str, "%6d", info->serial);
1329                 setenv("serial#", str);
1330         }
1331
1332
1333         /* setup baseboard specific GPIO pinmux and config */
1334         setup_board_gpio(board_type);
1335
1336 #ifdef CONFIG_CMD_BMODE
1337         add_board_boot_modes(board_boot_modes);
1338 #endif
1339
1340         /*
1341          *  The Gateworks System Controller implements a boot
1342          *  watchdog (always enabled) as a workaround for IMX6 boot related
1343          *  errata such as:
1344          *    ERR005768 - no fix
1345          *    ERR006282 - fixed in silicon r1.3
1346          *    ERR007117 - fixed in silicon r1.3
1347          *    ERR007220 - fixed in silicon r1.3
1348          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1349          *
1350          * Disable the boot watchdog and display/clear the timeout flag if set
1351          */
1352         i2c_set_bus_num(CONFIG_I2C_GSC);
1353         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1354                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1355                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1356                         puts("Error: could not disable GSC Watchdog\n");
1357         } else {
1358                 puts("Error: could not disable GSC Watchdog\n");
1359         }
1360         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1361                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1362                         puts("GSC boot watchdog timeout detected\n");
1363                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1364                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1365                 }
1366         }
1367
1368         return 0;
1369 }
1370
1371 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1372
1373 /*
1374  * called prior to booting kernel or by 'fdt boardsetup' command
1375  *
1376  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1377  *  - mtd partitions based on mtdparts/mtdids env
1378  *  - system-serial (board serial num from EEPROM)
1379  *  - board (full model from EEPROM)
1380  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1381  */
1382 void ft_board_setup(void *blob, bd_t *bd)
1383 {
1384         struct ventana_board_info *info = &ventana_info;
1385         struct ventana_eeprom_config *cfg;
1386         struct node_info nodes[] = {
1387                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1388                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1389         };
1390         const char *model = getenv("model");
1391
1392         if (getenv("fdt_noauto")) {
1393                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1394                 return;
1395         }
1396
1397         /* Update partition nodes using info from mtdparts env var */
1398         puts("   Updating MTD partitions...\n");
1399         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1400
1401         if (!model) {
1402                 puts("invalid board info: Leaving FDT fully enabled\n");
1403                 return;
1404         }
1405         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1406
1407         /* board serial number */
1408         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1409                     strlen(getenv("serial#")) + 1);
1410
1411         /* board (model contains model from device-tree) */
1412         fdt_setprop(blob, 0, "board", info->model,
1413                     strlen((const char *)info->model) + 1);
1414
1415         /*
1416          * Peripheral Config:
1417          *  remove nodes by alias path if EEPROM config tells us the
1418          *  peripheral is not loaded on the board.
1419          */
1420         if (getenv("fdt_noconfig")) {
1421                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1422                 return;
1423         }
1424         cfg = econfig;
1425         while (cfg->name) {
1426                 if (!test_bit(cfg->bit, info->config)) {
1427                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1428                                                cfg->dtalias : cfg->name);
1429                 }
1430                 cfg++;
1431         }
1432 }
1433 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1434