board/gateworks/gw_ventana/gw_ventana_spl.c

   1 /*
   2  * Copyright (C) 2014 Gateworks Corporation
   3  * Author: Tim Harvey <tharvey@gateworks.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <i2c.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-ddr.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/imx-common/boot_mode.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/imx-common/mxc_i2c.h>
  18 #include <spl.h>
  19
  20 #include "ventana_eeprom.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  25 #define I2C_GSC                 0
  26 #define GSC_EEPROM_ADDR         0x51
  27 #define GSC_EEPROM_DDR_SIZE     0x2B    /* enum (512,1024,2048) MB */
  28 #define GSC_EEPROM_DDR_WIDTH    0x2D    /* enum (32,64) bit */
  29 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  30         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  31         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  32 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  33 #define CONFIG_SYS_I2C_SPEED    100000
  34
  35 /* I2C1: GSC */
  36 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
  37         .scl = {
  38                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  39                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
  40                 .gp = IMX_GPIO_NR(3, 21)
  41         },
  42         .sda = {
  43                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  44                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
  45                 .gp = IMX_GPIO_NR(3, 28)
  46         }
  47 };
  48 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
  49         .scl = {
  50                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
  51                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
  52                 .gp = IMX_GPIO_NR(3, 21)
  53         },
  54         .sda = {
  55                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
  56                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
  57                 .gp = IMX_GPIO_NR(3, 28)
  58         }
  59 };
  60
  61 static void i2c_setup_iomux(void)
  62 {
  63         if (is_cpu_type(MXC_CPU_MX6Q))
  64                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
  65         else
  66                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
  67 }
  68
  69 /* configure MX6Q/DUAL mmdc DDR io registers */
  70 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  71         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  72         .dram_sdclk_0 = 0x00020030,
  73         .dram_sdclk_1 = 0x00020030,
  74         .dram_cas = 0x00020030,
  75         .dram_ras = 0x00020030,
  76         .dram_reset = 0x00020030,
  77         /* SDCKE[0:1]: 100k pull-up */
  78         .dram_sdcke0 = 0x00003000,
  79         .dram_sdcke1 = 0x00003000,
  80         /* SDBA2: pull-up disabled */
  81         .dram_sdba2 = 0x00000000,
  82         /* SDODT[0:1]: 100k pull-up, 40 ohm */
  83         .dram_sdodt0 = 0x00003030,
  84         .dram_sdodt1 = 0x00003030,
  85         /* SDQS[0:7]: Differential input, 40 ohm */
  86         .dram_sdqs0 = 0x00000030,
  87         .dram_sdqs1 = 0x00000030,
  88         .dram_sdqs2 = 0x00000030,
  89         .dram_sdqs3 = 0x00000030,
  90         .dram_sdqs4 = 0x00000030,
  91         .dram_sdqs5 = 0x00000030,
  92         .dram_sdqs6 = 0x00000030,
  93         .dram_sdqs7 = 0x00000030,
  94
  95         /* DQM[0:7]: Differential input, 40 ohm */
  96         .dram_dqm0 = 0x00020030,
  97         .dram_dqm1 = 0x00020030,
  98         .dram_dqm2 = 0x00020030,
  99         .dram_dqm3 = 0x00020030,
 100         .dram_dqm4 = 0x00020030,
 101         .dram_dqm5 = 0x00020030,
 102         .dram_dqm6 = 0x00020030,
 103         .dram_dqm7 = 0x00020030,
 104 };
 105
 106 /* configure MX6Q/DUAL mmdc GRP io registers */
 107 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 108         /* DDR3 */
 109         .grp_ddr_type = 0x000c0000,
 110         .grp_ddrmode_ctl = 0x00020000,
 111         /* disable DDR pullups */
 112         .grp_ddrpke = 0x00000000,
 113         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 114         .grp_addds = 0x00000030,
 115         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 116         .grp_ctlds = 0x00000030,
 117         /* DATA[00:63]: Differential input, 40 ohm */
 118         .grp_ddrmode = 0x00020000,
 119         .grp_b0ds = 0x00000030,
 120         .grp_b1ds = 0x00000030,
 121         .grp_b2ds = 0x00000030,
 122         .grp_b3ds = 0x00000030,
 123         .grp_b4ds = 0x00000030,
 124         .grp_b5ds = 0x00000030,
 125         .grp_b6ds = 0x00000030,
 126         .grp_b7ds = 0x00000030,
 127 };
 128
 129 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 130 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 131         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 132         .dram_sdclk_0 = 0x00020030,
 133         .dram_sdclk_1 = 0x00020030,
 134         .dram_cas = 0x00020030,
 135         .dram_ras = 0x00020030,
 136         .dram_reset = 0x00020030,
 137         /* SDCKE[0:1]: 100k pull-up */
 138         .dram_sdcke0 = 0x00003000,
 139         .dram_sdcke1 = 0x00003000,
 140         /* SDBA2: pull-up disabled */
 141         .dram_sdba2 = 0x00000000,
 142         /* SDODT[0:1]: 100k pull-up, 40 ohm */
 143         .dram_sdodt0 = 0x00003030,
 144         .dram_sdodt1 = 0x00003030,
 145         /* SDQS[0:7]: Differential input, 40 ohm */
 146         .dram_sdqs0 = 0x00000030,
 147         .dram_sdqs1 = 0x00000030,
 148         .dram_sdqs2 = 0x00000030,
 149         .dram_sdqs3 = 0x00000030,
 150         .dram_sdqs4 = 0x00000030,
 151         .dram_sdqs5 = 0x00000030,
 152         .dram_sdqs6 = 0x00000030,
 153         .dram_sdqs7 = 0x00000030,
 154
 155         /* DQM[0:7]: Differential input, 40 ohm */
 156         .dram_dqm0 = 0x00020030,
 157         .dram_dqm1 = 0x00020030,
 158         .dram_dqm2 = 0x00020030,
 159         .dram_dqm3 = 0x00020030,
 160         .dram_dqm4 = 0x00020030,
 161         .dram_dqm5 = 0x00020030,
 162         .dram_dqm6 = 0x00020030,
 163         .dram_dqm7 = 0x00020030,
 164 };
 165
 166 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 167 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 168         /* DDR3 */
 169         .grp_ddr_type = 0x000c0000,
 170         /* SDQS[0:7]: Differential input, 40 ohm */
 171         .grp_ddrmode_ctl = 0x00020000,
 172         /* disable DDR pullups */
 173         .grp_ddrpke = 0x00000000,
 174         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
 175         .grp_addds = 0x00000030,
 176         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
 177         .grp_ctlds = 0x00000030,
 178         /* DATA[00:63]: Differential input, 40 ohm */
 179         .grp_ddrmode = 0x00020000,
 180         .grp_b0ds = 0x00000030,
 181         .grp_b1ds = 0x00000030,
 182         .grp_b2ds = 0x00000030,
 183         .grp_b3ds = 0x00000030,
 184         .grp_b4ds = 0x00000030,
 185         .grp_b5ds = 0x00000030,
 186         .grp_b6ds = 0x00000030,
 187         .grp_b7ds = 0x00000030,
 188 };
 189
 190 /* MT41K128M16JT-125 */
 191 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 192         .mem_speed = 1600,
 193         .density = 2,
 194         .width = 16,
 195         .banks = 8,
 196         .rowaddr = 14,
 197         .coladdr = 10,
 198         .pagesz = 2,
 199         .trcd = 1375,
 200         .trcmin = 4875,
 201         .trasmin = 3500,
 202 };
 203
 204 /* GW54xx specific calibration */
 205 static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = {
 206         /* write leveling calibration determine */
 207         .p0_mpwldectrl0 = 0x00190018,
 208         .p0_mpwldectrl1 = 0x0021001D,
 209         .p1_mpwldectrl0 = 0x00160027,
 210         .p1_mpwldectrl1 = 0x0012001E,
 211         /* Read DQS Gating calibration */
 212         .p0_mpdgctrl0 = 0x43370346,
 213         .p0_mpdgctrl1 = 0x032A0321,
 214         .p1_mpdgctrl0 = 0x433A034D,
 215         .p1_mpdgctrl1 = 0x032F0235,
 216         /* Read Calibration: DQS delay relative to DQ read access */
 217         .p0_mprddlctl = 0x3C313539,
 218         .p1_mprddlctl = 0x37333140,
 219         /* Write Calibration: DQ/DM delay relative to DQS write access */
 220         .p0_mpwrdlctl = 0x37393C38,
 221         .p1_mpwrdlctl = 0x42334538,
 222 };
 223
 224 /* GW53xx specific calibration */
 225 static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = {
 226         /* write leveling calibration determine */
 227         .p0_mpwldectrl0 = 0x00160013,
 228         .p0_mpwldectrl1 = 0x00090024,
 229         .p1_mpwldectrl0 = 0x001F0018,
 230         .p1_mpwldectrl1 = 0x000C001C,
 231         /* Read DQS Gating calibration */
 232         .p0_mpdgctrl0 = 0x433A034C,
 233         .p0_mpdgctrl1 = 0x0336032F,
 234         .p1_mpdgctrl0 = 0x4343034A,
 235         .p1_mpdgctrl1 = 0x03370222,
 236         /* Read Calibration: DQS delay relative to DQ read access */
 237         .p0_mprddlctl = 0x3F343638,
 238         .p1_mprddlctl = 0x38373442,
 239         /* Write Calibration: DQ/DM delay relative to DQS write access */
 240         .p0_mpwrdlctl = 0x343A3E39,
 241         .p1_mpwrdlctl = 0x44344239,
 242 };
 243 static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
 244         /* write leveling calibration determine */
 245         .p0_mpwldectrl0 = 0x003C003C,
 246         .p0_mpwldectrl1 = 0x00330038,
 247         .p1_mpwldectrl0 = 0x001F002A,
 248         .p1_mpwldectrl1 = 0x0022003F,
 249         /* Read DQS Gating calibration */
 250         .p0_mpdgctrl0 = 0x42410244,
 251         .p0_mpdgctrl1 = 0x022D022D,
 252         .p1_mpdgctrl0 = 0x4234023A,
 253         .p1_mpdgctrl1 = 0x021C0228,
 254         /* Read Calibration: DQS delay relative to DQ read access */
 255         .p0_mprddlctl = 0x484A4C4B,
 256         .p1_mprddlctl = 0x4B4D4E4B,
 257         /* Write Calibration: DQ/DM delay relative to DQS write access */
 258         .p0_mpwrdlctl = 0x33342B32,
 259         .p1_mpwrdlctl = 0x3933332B,
 260 };
 261
 262 /* GW52xx specific calibration */
 263 static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = {
 264         /* write leveling calibration determine */
 265         .p0_mpwldectrl0 = 0x0040003F,
 266         .p0_mpwldectrl1 = 0x00370037,
 267         /* Read DQS Gating calibration */
 268         .p0_mpdgctrl0 = 0x42420244,
 269         .p0_mpdgctrl1 = 0x022F022F,
 270         /* Read Calibration: DQS delay relative to DQ read access */
 271         .p0_mprddlctl = 0x49464B4A,
 272         /* Write Calibration: DQ/DM delay relative to DQS write access */
 273         .p0_mpwrdlctl = 0x32362C32,
 274 };
 275
 276 /* GW51xx specific calibration */
 277 static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = {
 278         /* write leveling calibration determine */
 279         .p0_mpwldectrl0 = 0x00150016,
 280         .p0_mpwldectrl1 = 0x001F0017,
 281         /* Read DQS Gating calibration */
 282         .p0_mpdgctrl0 = 0x433D034D,
 283         .p0_mpdgctrl1 = 0x033D032F,
 284         /* Read Calibration: DQS delay relative to DQ read access */
 285         .p0_mprddlctl = 0x3F313639,
 286         /* Write Calibration: DQ/DM delay relative to DQS write access */
 287         .p0_mpwrdlctl = 0x33393F36,
 288 };
 289
 290 static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = {
 291         /* write leveling calibration determine */
 292         .p0_mpwldectrl0 = 0x003D003F,
 293         .p0_mpwldectrl1 = 0x002F0038,
 294         /* Read DQS Gating calibration */
 295         .p0_mpdgctrl0 = 0x423A023A,
 296         .p0_mpdgctrl1 = 0x022A0228,
 297         /* Read Calibration: DQS delay relative to DQ read access */
 298         .p0_mprddlctl = 0x48494C4C,
 299         /* Write Calibration: DQ/DM delay relative to DQS write access */
 300         .p0_mpwrdlctl = 0x34352D31,
 301 };
 302
 303 static void spl_dram_init(int width, int size, int board_model)
 304 {
 305         struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
 306         struct mx6_mmdc_calibration *calib;
 307         struct mx6_ddr_sysinfo sysinfo = {
 308                 /* width of data bus:0=16,1=32,2=64 */
 309                 .dsize = width/32,
 310                 /* config for full 4GB range so that get_mem_size() works */
 311                 .cs_density = 32, /* 32Gb per CS */
 312                 /* single chip select */
 313                 .ncs = 1,
 314                 .cs1_mirror = 0,
 315                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 316 #ifdef RTT_NOM_120OHM
 317                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 318 #else
 319                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 320 #endif
 321                 .walat = 1,     /* Write additional latency */
 322                 .ralat = 5,     /* Read additional latency */
 323                 .mif3_mode = 3, /* Command prediction working mode */
 324                 .bi_on = 1,     /* Bank interleaving enabled */
 325                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 326                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 327         };
 328
 329         /*
 330          * MMDC Calibration requires the following data:
 331          *   mx6_mmdc_calibration - board-specific calibration (routing delays)
 332          *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
 333          *   mx6_ddr_cfg - chip specific timing/layout details
 334          */
 335         switch (board_model) {
 336         default:
 337         case GW51xx:
 338                 if (is_cpu_type(MXC_CPU_MX6Q))
 339                         calib = &gw51xxq_mmdc_calib;
 340                 else
 341                         calib = &gw51xxdl_mmdc_calib;
 342                 break;
 343         case GW52xx:
 344                 calib = &gw52xxdl_mmdc_calib;
 345                 break;
 346         case GW53xx:
 347                 if (is_cpu_type(MXC_CPU_MX6Q))
 348                         calib = &gw53xxq_mmdc_calib;
 349                 else
 350                         calib = &gw53xxdl_mmdc_calib;
 351                 break;
 352         case GW54xx:
 353                 calib = &gw54xxq_mmdc_calib;
 354                 break;
 355         }
 356
 357         if (is_cpu_type(MXC_CPU_MX6Q))
 358                 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
 359                                  &mx6dq_grp_ioregs);
 360         else
 361                 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
 362                                   &mx6sdl_grp_ioregs);
 363         mx6_dram_cfg(&sysinfo, calib, mem);
 364 }
 365
 366 /*
 367  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 368  * - we have a stack and a place to store GD, both in SRAM
 369  * - no variable global data is available
 370  */
 371 void board_init_f(ulong dummy)
 372 {
 373         struct ventana_board_info ventana_info;
 374         int board_model;
 375
 376         /*
 377          * Zero out global data:
 378          *  - this shoudl be done by crt0.S
 379          *  - failure to zero it will cause i2c_setup to fail
 380          */
 381         memset((void *)gd, 0, sizeof(struct global_data));
 382
 383         /* setup AIPS and disable watchdog */
 384         arch_cpu_init();
 385
 386         /* iomux and setup of i2c */
 387         board_early_init_f();
 388         i2c_setup_iomux();
 389
 390         /* setup GP timer */
 391         timer_init();
 392
 393         /* UART clocks enabled and gd valid - init serial console */
 394         preloader_console_init();
 395
 396         /* read/validate EEPROM info to determine board model and SDRAM cfg */
 397         board_model = read_eeprom(I2C_GSC, &ventana_info);
 398
 399         /* provide some some default: 32bit 128MB */
 400         if (GW_UNKNOWN == board_model) {
 401                 ventana_info.sdram_width = 2;
 402                 ventana_info.sdram_size = 3;
 403         }
 404
 405         /* configure MMDC for SDRAM width/size and per-model calibration */
 406         spl_dram_init(8 << ventana_info.sdram_width,
 407                       16 << ventana_info.sdram_size,
 408                       board_model);
 409
 410         /* Clear the BSS. */
 411         memset(__bss_start, 0, __bss_end - __bss_start);
 412
 413         /* load/boot image from boot device */
 414         board_init_r(NULL, 0);
 415 }
 416
 417 void reset_cpu(ulong addr)
 418 {
 419 }