board/gdsys/405ep/dlvision-10g.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/ppc4xx-gpio.h>
  29
  30 #include <gdsys_fpga.h>
  31
  32 #include "../common/osd.h"
  33
  34 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  35 #define LATCH2_MC2_PRESENT_N 0x0080
  36
  37 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
  38
  39 enum {
  40         UNITTYPE_VIDEO_USER = 0,
  41         UNITTYPE_MAIN_USER = 1,
  42         UNITTYPE_VIDEO_SERVER = 2,
  43         UNITTYPE_MAIN_SERVER = 3,
  44 };
  45
  46 enum {
  47         HWVER_101 = 0,
  48         HWVER_110 = 1,
  49 };
  50
  51 enum {
  52         AUDIO_NONE = 0,
  53         AUDIO_TX = 1,
  54         AUDIO_RX = 2,
  55         AUDIO_RXTX = 3,
  56 };
  57
  58 enum {
  59         SYSCLK_156250 = 2,
  60 };
  61
  62 enum {
  63         RAM_NONE = 0,
  64         RAM_DDR2_32 = 1,
  65         RAM_DDR2_64 = 2,
  66 };
  67
  68 static unsigned int get_hwver(void)
  69 {
  70         u16 latch3 = in_le16((void *)LATCH3_BASE);
  71
  72         return latch3 & 0x0003;
  73 }
  74
  75 static unsigned int get_mc2_present(void)
  76 {
  77         u16 latch2 = in_le16((void *)LATCH2_BASE);
  78
  79         return !(latch2 & LATCH2_MC2_PRESENT_N);
  80 }
  81
  82 static void print_fpga_info(unsigned dev)
  83 {
  84         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
  85         u16 versions = in_le16(&fpga->versions);
  86         u16 fpga_version = in_le16(&fpga->fpga_version);
  87         u16 fpga_features = in_le16(&fpga->fpga_features);
  88         unsigned unit_type;
  89         unsigned hardware_version;
  90         unsigned feature_rs232;
  91         unsigned feature_audio;
  92         unsigned feature_sysclock;
  93         unsigned feature_ramconfig;
  94         unsigned feature_carrier_speed;
  95         unsigned feature_carriers;
  96         unsigned feature_video_channels;
  97         int fpga_state = get_fpga_state(dev);
  98
  99         printf("FPGA%d: ", dev);
 100
 101         hardware_version = versions & 0x000f;
 102
 103         if (fpga_state
 104             && !((hardware_version == HWVER_101)
 105                  && (fpga_state == FPGA_STATE_DONE_FAILED))) {
 106                 puts("not available\n");
 107                 print_fpga_state(dev);
 108                 return;
 109         }
 110
 111         unit_type = (versions >> 4) & 0x000f;
 112         hardware_version = versions & 0x000f;
 113         feature_rs232 = fpga_features & (1<<11);
 114         feature_audio = (fpga_features >> 9) & 0x0003;
 115         feature_sysclock = (fpga_features >> 7) & 0x0003;
 116         feature_ramconfig = (fpga_features >> 5) & 0x0003;
 117         feature_carrier_speed = fpga_features & (1<<4);
 118         feature_carriers = (fpga_features >> 2) & 0x0003;
 119         feature_video_channels = fpga_features & 0x0003;
 120
 121         switch (unit_type) {
 122         case UNITTYPE_VIDEO_USER:
 123                 printf("Videochannel Userside");
 124                 break;
 125
 126         case UNITTYPE_MAIN_USER:
 127                 printf("Mainchannel Userside");
 128                 break;
 129
 130         case UNITTYPE_VIDEO_SERVER:
 131                 printf("Videochannel Serverside");
 132                 break;
 133
 134         case UNITTYPE_MAIN_SERVER:
 135                 printf("Mainchannel Serverside");
 136                 break;
 137
 138         default:
 139                 printf("UnitType %d(not supported)", unit_type);
 140                 break;
 141         }
 142
 143         switch (hardware_version) {
 144         case HWVER_101:
 145                 printf(" HW-Ver 1.01\n");
 146                 break;
 147
 148         case HWVER_110:
 149                 printf(" HW-Ver 1.10\n");
 150                 break;
 151
 152         default:
 153                 printf(" HW-Ver %d(not supported)\n",
 154                        hardware_version);
 155                 break;
 156         }
 157
 158         printf("       FPGA V %d.%02d, features:",
 159                 fpga_version / 100, fpga_version % 100);
 160
 161         printf(" %sRS232", feature_rs232 ? "" : "no ");
 162
 163         switch (feature_audio) {
 164         case AUDIO_NONE:
 165                 printf(", no audio");
 166                 break;
 167
 168         case AUDIO_TX:
 169                 printf(", audio tx");
 170                 break;
 171
 172         case AUDIO_RX:
 173                 printf(", audio rx");
 174                 break;
 175
 176         case AUDIO_RXTX:
 177                 printf(", audio rx+tx");
 178                 break;
 179
 180         default:
 181                 printf(", audio %d(not supported)", feature_audio);
 182                 break;
 183         }
 184
 185         switch (feature_sysclock) {
 186         case SYSCLK_156250:
 187                 printf(", clock 156.25 MHz");
 188                 break;
 189
 190         default:
 191                 printf(", clock %d(not supported)", feature_sysclock);
 192                 break;
 193         }
 194
 195         puts(",\n       ");
 196
 197         switch (feature_ramconfig) {
 198         case RAM_NONE:
 199                 printf("no RAM");
 200                 break;
 201
 202         case RAM_DDR2_32:
 203                 printf("RAM 32 bit DDR2");
 204                 break;
 205
 206         case RAM_DDR2_64:
 207                 printf("RAM 64 bit DDR2");
 208                 break;
 209
 210         default:
 211                 printf("RAM %d(not supported)", feature_ramconfig);
 212                 break;
 213         }
 214
 215         printf(", %d carrier(s) %s", feature_carriers,
 216                 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
 217
 218         printf(", %d video channel(s)\n", feature_video_channels);
 219 }
 220
 221 /*
 222  * Check Board Identity:
 223  */
 224 int checkboard(void)
 225 {
 226         char buf[64];
 227         int i = getenv_f("serial#", buf, sizeof(buf));
 228
 229         printf("Board: ");
 230
 231         printf("DLVision 10G");
 232
 233         if (i > 0) {
 234                 puts(", serial# ");
 235                 puts(buf);
 236         }
 237
 238         puts("\n");
 239
 240         print_fpga_info(0);
 241         if (get_mc2_present())
 242                 print_fpga_info(1);
 243
 244         return 0;
 245 }
 246
 247 int last_stage_init(void)
 248 {
 249         ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 250         u16 versions = in_le16(&fpga->versions);
 251
 252         if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
 253                 return 0;
 254
 255         if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
 256                 osd_probe(0);
 257
 258         if (get_mc2_present() &&
 259             (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
 260                 osd_probe(1);
 261
 262         return 0;
 263 }