board/gdsys/405ep/io.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13
  14 #include <dtt.h>
  15 #include <miiphy.h>
  16
  17 #include "405ep.h"
  18 #include <gdsys_fpga.h>
  19
  20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  23
  24 #define PHYREG_CONTROL                          0
  25 #define PHYREG_PAGE_ADDRESS                     22
  26 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1    16
  27 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2    26
  28
  29 enum {
  30         UNITTYPE_CCD_SWITCH = 1,
  31 };
  32
  33 enum {
  34         HWVER_100 = 0,
  35         HWVER_110 = 1,
  36         HWVER_121 = 2,
  37         HWVER_122 = 3,
  38 };
  39
  40 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  41
  42 int misc_init_r(void)
  43 {
  44         /* startup fans */
  45         dtt_init();
  46
  47         return 0;
  48 }
  49
  50 int configure_gbit_phy(unsigned char addr)
  51 {
  52         unsigned short value;
  53
  54         /* select page 2 */
  55         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  56                 PHYREG_PAGE_ADDRESS, 0x0002))
  57                 goto err_out;
  58         /* disable SGMII autonegotiation */
  59         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  60                 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
  61                 goto err_out;
  62         /* select page 0 */
  63         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  64                 PHYREG_PAGE_ADDRESS, 0x0000))
  65                 goto err_out;
  66         /* switch from powerdown to normal operation */
  67         if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  68                 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
  69                 goto err_out;
  70         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  71                 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
  72                 goto err_out;
  73         /* reset phy so settings take effect */
  74         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  75                 PHYREG_CONTROL, 0x9140))
  76                 goto err_out;
  77
  78         return 0;
  79
  80 err_out:
  81         printf("Error writing to the PHY addr=%02x\n", addr);
  82         return -1;
  83 }
  84
  85 /*
  86  * Check Board Identity:
  87  */
  88 int checkboard(void)
  89 {
  90         char *s = getenv("serial#");
  91
  92         puts("Board: CATCenter Io");
  93
  94         if (s != NULL) {
  95                 puts(", serial# ");
  96                 puts(s);
  97         }
  98
  99         puts("\n");
 100
 101         return 0;
 102 }
 103
 104 static void print_fpga_info(void)
 105 {
 106         u16 versions;
 107         u16 fpga_version;
 108         u16 fpga_features;
 109         unsigned unit_type;
 110         unsigned hardware_version;
 111         unsigned feature_channels;
 112         unsigned feature_expansion;
 113
 114         FPGA_GET_REG(0, versions, &versions);
 115         FPGA_GET_REG(0, fpga_version, &fpga_version);
 116         FPGA_GET_REG(0, fpga_features, &fpga_features);
 117
 118         unit_type = (versions & 0xf000) >> 12;
 119         hardware_version = versions & 0x000f;
 120         feature_channels = fpga_features & 0x007f;
 121         feature_expansion = fpga_features & (1<<15);
 122
 123         puts("FPGA:  ");
 124
 125         switch (unit_type) {
 126         case UNITTYPE_CCD_SWITCH:
 127                 printf("CCD-Switch");
 128                 break;
 129
 130         default:
 131                 printf("UnitType %d(not supported)", unit_type);
 132                 break;
 133         }
 134
 135         switch (hardware_version) {
 136         case HWVER_100:
 137                 printf(" HW-Ver 1.00\n");
 138                 break;
 139
 140         case HWVER_110:
 141                 printf(" HW-Ver 1.10\n");
 142                 break;
 143
 144         case HWVER_121:
 145                 printf(" HW-Ver 1.21\n");
 146                 break;
 147
 148         case HWVER_122:
 149                 printf(" HW-Ver 1.22\n");
 150                 break;
 151
 152         default:
 153                 printf(" HW-Ver %d(not supported)\n",
 154                        hardware_version);
 155                 break;
 156         }
 157
 158         printf("       FPGA V %d.%02d, features:",
 159                 fpga_version / 100, fpga_version % 100);
 160
 161         printf(" %d channel(s)", feature_channels);
 162
 163         printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
 164 }
 165
 166 /*
 167  * setup Gbit PHYs
 168  */
 169 int last_stage_init(void)
 170 {
 171         unsigned int k;
 172
 173         print_fpga_info();
 174
 175         miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
 176                 bb_miiphy_read, bb_miiphy_write);
 177
 178         for (k = 0; k < 32; ++k)
 179                 configure_gbit_phy(k);
 180
 181         /* take fpga serdes blocks out of reset */
 182         FPGA_SET_REG(0, quad_serdes_reset, 0);
 183
 184         return 0;
 185 }
 186
 187 void gd405ep_init(void)
 188 {
 189 }
 190
 191 void gd405ep_set_fpga_reset(unsigned state)
 192 {
 193         if (state) {
 194                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 195                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 196         } else {
 197                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 198                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 199         }
 200 }
 201
 202 void gd405ep_setup_hw(void)
 203 {
 204         /*
 205          * set "startup-finished"-gpios
 206          */
 207         gpio_write_bit(21, 0);
 208         gpio_write_bit(22, 1);
 209 }
 210
 211 int gd405ep_get_fpga_done(unsigned fpga)
 212 {
 213         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 214 }