board/gumstix/pepper/board.c

   1 /*
   2  * Board functions for Gumstix Pepper and AM335x-based boards
   3  *
   4  * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
   5  * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <spl.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/omap.h>
  16 #include <asm/arch/ddr_defs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc_host_def.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/mem.h>
  22 #include <asm/io.h>
  23 #include <asm/emif.h>
  24 #include <asm/gpio.h>
  25 #include <i2c.h>
  26 #include <miiphy.h>
  27 #include <cpsw.h>
  28 #include <power/tps65217.h>
  29 #include <environment.h>
  30 #include <watchdog.h>
  31 #include "board.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #ifdef CONFIG_SPL_BUILD
  36 static const struct ddr_data ddr2_data = {
  37         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  38         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  39         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  40 };
  41
  42 static const struct cmd_control ddr2_cmd_ctrl_data = {
  43         .cmd0csratio = MT47H128M16RT25E_RATIO,
  44
  45         .cmd1csratio = MT47H128M16RT25E_RATIO,
  46
  47         .cmd2csratio = MT47H128M16RT25E_RATIO,
  48 };
  49
  50 static const struct emif_regs ddr2_emif_reg_data = {
  51         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  52         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  53         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  54         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  55         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  56         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  57 };
  58
  59 #ifdef CONFIG_SPL_OS_BOOT
  60 int spl_start_uboot(void)
  61 {
  62         /* break into full u-boot on 'c' */
  63         return serial_tstc() && serial_getc() == 'c';
  64 }
  65 #endif
  66
  67 #define OSC     (V_OSCK/1000000)
  68 const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
  69
  70 const struct dpll_params *get_dpll_ddr_params(void)
  71 {
  72         return &dpll_ddr;
  73 }
  74
  75 void set_uart_mux_conf(void)
  76 {
  77         enable_uart0_pin_mux();
  78 }
  79
  80 void set_mux_conf_regs(void)
  81 {
  82         enable_board_pin_mux();
  83 }
  84
  85 const struct ctrl_ioregs ioregs = {
  86         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
  87         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
  88         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
  89         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
  90         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
  91 };
  92
  93 void sdram_init(void)
  94 {
  95         config_ddr(266, &ioregs, &ddr2_data,
  96                    &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  97 }
  98 #endif
  99
 100 int board_init(void)
 101 {
 102 #if defined(CONFIG_HW_WATCHDOG)
 103         hw_watchdog_init();
 104 #endif
 105
 106         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 107         gpmc_init();
 108
 109         return 0;
 110 }
 111
 112 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 113         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 114 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 115
 116 static void cpsw_control(int enabled)
 117 {
 118         /* VTP can be added here */
 119
 120         return;
 121 }
 122
 123 static struct cpsw_slave_data cpsw_slaves[] = {
 124         {
 125                 .slave_reg_ofs  = 0x208,
 126                 .sliver_reg_ofs = 0xd80,
 127                 .phy_addr       = 0,
 128                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 129         },
 130 };
 131
 132 static struct cpsw_platform_data cpsw_data = {
 133         .mdio_base              = CPSW_MDIO_BASE,
 134         .cpsw_base              = CPSW_BASE,
 135         .mdio_div               = 0xff,
 136         .channels               = 8,
 137         .cpdma_reg_ofs          = 0x800,
 138         .slaves                 = 1,
 139         .slave_data             = cpsw_slaves,
 140         .ale_reg_ofs            = 0xd00,
 141         .ale_entries            = 1024,
 142         .host_port_reg_ofs      = 0x108,
 143         .hw_stats_reg_ofs       = 0x900,
 144         .bd_ram_ofs             = 0x2000,
 145         .mac_control            = (1 << 5),
 146         .control                = cpsw_control,
 147         .host_port_num          = 0,
 148         .version                = CPSW_CTRL_VERSION_2,
 149 };
 150
 151 int board_eth_init(bd_t *bis)
 152 {
 153         int rv, n = 0;
 154         uint8_t mac_addr[6];
 155         uint32_t mac_hi, mac_lo;
 156         const char *devname;
 157
 158         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 159                 /* try reading mac address from efuse */
 160                 mac_lo = readl(&cdev->macid0l);
 161                 mac_hi = readl(&cdev->macid0h);
 162                 mac_addr[0] = mac_hi & 0xFF;
 163                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 164                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 165                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 166                 mac_addr[4] = mac_lo & 0xFF;
 167                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 168                 if (is_valid_ethaddr(mac_addr))
 169                         eth_setenv_enetaddr("ethaddr", mac_addr);
 170         }
 171
 172         writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 173
 174         rv = cpsw_register(&cpsw_data);
 175         if (rv < 0)
 176                 printf("Error %d registering CPSW switch\n", rv);
 177         else
 178                 n += rv;
 179
 180         /*
 181          *
 182          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 183          * operating points.  So we must set the TX clock delay feature
 184          * in the KSZ9021 PHY.  Since we only support a single ethernet
 185          * device in U-Boot, we only do this for the current instance.
 186          */
 187         devname = miiphy_get_current_dev();
 188         /* max rx/tx clock delay, min rx/tx control delay */
 189         miiphy_write(devname, 0x0, 0x0b, 0x8104);
 190         miiphy_write(devname, 0x0, 0xc, 0xa0a0);
 191
 192         /* min rx data delay */
 193         miiphy_write(devname, 0x0, 0x0b, 0x8105);
 194         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 195
 196         /* min tx data delay */
 197         miiphy_write(devname, 0x0, 0x0b, 0x8106);
 198         miiphy_write(devname, 0x0, 0x0c, 0x0000);
 199
 200         return n;
 201 }
 202 #endif