board/isee/igep0033/board.c

   1 /*
   2  * Board functions for IGEP COM AQUILA based boards
   3  *
   4  * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <spl.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/ddr_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc_host_def.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22 #include <asm/gpio.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26 #include "board.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  31
  32 #ifdef CONFIG_SPL_BUILD
  33 static const struct ddr_data ddr3_data = {
  34         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  35         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  36         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  37         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  38         .datadldiff0 = PHY_DLL_LOCK_DIFF,
  39 };
  40
  41 static const struct cmd_control ddr3_cmd_ctrl_data = {
  42         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  43         .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  44         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  45
  46         .cmd1csratio = K4B2G1646EBIH9_RATIO,
  47         .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  48         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  49
  50         .cmd2csratio = K4B2G1646EBIH9_RATIO,
  51         .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  52         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  53 };
  54
  55 static struct emif_regs ddr3_emif_reg_data = {
  56         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  57         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  58         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  59         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  60         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  61         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  62         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  63 };
  64
  65 #define OSC    (V_OSCK/1000000)
  66 const struct dpll_params dpll_ddr = {
  67                 400, OSC-1, 1, -1, -1, -1, -1};
  68
  69 const struct dpll_params *get_dpll_ddr_params(void)
  70 {
  71         return &dpll_ddr;
  72 }
  73
  74 void set_uart_mux_conf(void)
  75 {
  76         enable_uart0_pin_mux();
  77 }
  78
  79 void set_mux_conf_regs(void)
  80 {
  81         enable_board_pin_mux();
  82 }
  83
  84 void sdram_init(void)
  85 {
  86         config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
  87                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  88 }
  89 #endif
  90
  91 /*
  92  * Basic board specific setup.  Pinmux has been handled already.
  93  */
  94 int board_init(void)
  95 {
  96         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  97
  98         gpmc_init();
  99
 100         return 0;
 101 }
 102
 103 #if defined(CONFIG_DRIVER_TI_CPSW)
 104 static void cpsw_control(int enabled)
 105 {
 106         /* VTP can be added here */
 107
 108         return;
 109 }
 110
 111 static struct cpsw_slave_data cpsw_slaves[] = {
 112         {
 113                 .slave_reg_ofs  = 0x208,
 114                 .sliver_reg_ofs = 0xd80,
 115                 .phy_id         = 0,
 116                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 117         },
 118 };
 119
 120 static struct cpsw_platform_data cpsw_data = {
 121         .mdio_base              = CPSW_MDIO_BASE,
 122         .cpsw_base              = CPSW_BASE,
 123         .mdio_div               = 0xff,
 124         .channels               = 8,
 125         .cpdma_reg_ofs          = 0x800,
 126         .slaves                 = 1,
 127         .slave_data             = cpsw_slaves,
 128         .ale_reg_ofs            = 0xd00,
 129         .ale_entries            = 1024,
 130         .host_port_reg_ofs      = 0x108,
 131         .hw_stats_reg_ofs       = 0x900,
 132         .bd_ram_ofs             = 0x2000,
 133         .mac_control            = (1 << 5),
 134         .control                = cpsw_control,
 135         .host_port_num          = 0,
 136         .version                = CPSW_CTRL_VERSION_2,
 137 };
 138
 139 int board_eth_init(bd_t *bis)
 140 {
 141         int rv, ret = 0;
 142         uint8_t mac_addr[6];
 143         uint32_t mac_hi, mac_lo;
 144
 145         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 146                 /* try reading mac address from efuse */
 147                 mac_lo = readl(&cdev->macid0l);
 148                 mac_hi = readl(&cdev->macid0h);
 149                 mac_addr[0] = mac_hi & 0xFF;
 150                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 151                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 152                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 153                 mac_addr[4] = mac_lo & 0xFF;
 154                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 155                 if (is_valid_ether_addr(mac_addr))
 156                         eth_setenv_enetaddr("ethaddr", mac_addr);
 157         }
 158
 159         writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
 160                &cdev->miisel);
 161
 162         rv = cpsw_register(&cpsw_data);
 163         if (rv < 0)
 164                 printf("Error %d registering CPSW switch\n", rv);
 165         else
 166                 ret += rv;
 167
 168         return ret;
 169 }
 170 #endif