board/karo/tk71/tk71.c

   1 /*
   2  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   3  * on behalf of DENX Software Engineering GmbH
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21  * MA 02110-1301 USA
  22  */
  23
  24 #include <common.h>
  25 #include <miiphy.h>
  26 #include <asm/arch/cpu.h>
  27 #include <asm/arch/kirkwood.h>
  28 #include <asm/arch/mpp.h>
  29 #include <asm/io.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define TK71_OE_LOW                     (~0)
  34 #define TK71_OE_HIGH                    (~0)
  35 #define TK71_OE_VAL_LOW                 (0)
  36 #define TK71_OE_VAL_HIGH                (0)
  37
  38 int board_early_init_f(void)
  39 {
  40         /*
  41          * default gpio configuration
  42          * There are maximum 64 gpios controlled through 2 sets of registers
  43          * the  below configuration configures mainly initial LED status
  44          */
  45         kw_config_gpio(TK71_OE_VAL_LOW,
  46                         TK71_OE_VAL_HIGH,
  47                         TK71_OE_LOW, TK71_OE_HIGH);
  48
  49         /* Multi-Purpose Pins Functionality configuration */
  50         u32 kwmpp_config[] = {
  51                 MPP0_NF_IO2,
  52                 MPP1_NF_IO3,
  53                 MPP2_NF_IO4,
  54                 MPP3_NF_IO5,
  55                 MPP4_NF_IO6,
  56                 MPP5_NF_IO7,
  57                 MPP6_SYSRST_OUTn,
  58                 MPP7_GPO,
  59                 MPP8_TW_SDA,
  60                 MPP9_TW_SCK,
  61                 MPP10_UART0_TXD,
  62                 MPP11_UART0_RXD,
  63                 MPP12_SD_CLK,
  64                 MPP13_SD_CMD,
  65                 MPP14_SD_D0,
  66                 MPP15_SD_D1,
  67                 MPP16_SD_D2,
  68                 MPP17_SD_D3,
  69                 MPP18_NF_IO0,
  70                 MPP19_NF_IO1,
  71                 MPP20_GE1_0,
  72                 MPP21_GE1_1,
  73                 MPP22_GE1_2,
  74                 MPP23_GE1_3,
  75                 MPP24_GE1_4,
  76                 MPP25_GE1_5,
  77                 MPP26_GE1_6,
  78                 MPP27_GE1_7,
  79                 MPP28_GPIO,
  80                 MPP29_GPIO,
  81                 MPP30_GE1_10,
  82                 MPP31_GE1_11,
  83                 MPP32_GE1_12,
  84                 MPP33_GE1_13,
  85                 MPP34_GPIO,
  86                 MPP35_GPIO,
  87                 MPP36_GPIO,
  88                 MPP37_GPIO,
  89                 MPP38_GPIO,
  90                 MPP39_GPIO,
  91                 MPP40_GPIO,
  92                 MPP41_GPIO,
  93                 MPP42_GPIO,
  94                 MPP43_GPIO,
  95                 MPP44_GPIO,
  96                 MPP45_GPIO,
  97                 MPP46_GPIO,
  98                 MPP47_GPIO,
  99                 MPP48_GPIO,
 100                 MPP49_GPIO,
 101                 0
 102         };
 103         kirkwood_mpp_conf(kwmpp_config, NULL);
 104
 105         return 0;
 106 }
 107
 108 int dram_init(void)
 109 {
 110         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 111                                     PHYS_SDRAM_1_SIZE);
 112         return 0;
 113 }
 114
 115 int board_init(void)
 116 {
 117         /*
 118          * arch number of board
 119          */
 120         gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 121
 122         /* adress of boot parameters */
 123         gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 124
 125         return 0;
 126 }
 127
 128 #ifdef CONFIG_CMD_NET
 129
 130 #define MV88E1116_MAC_CTRL2_REG         21
 131 #define MV88E1116_PGADR_REG             22
 132 #define MV88E1116_RGMII_TXTM_CTRL       (1 << 4)
 133 #define MV88E1116_RGMII_RXTM_CTRL       (1 << 5)
 134
 135 static void mv_phy_88e1118_init(char *name)
 136 {
 137         u16 reg;
 138         u16 devadr;
 139
 140         if (miiphy_set_current_dev(name))
 141                 return;
 142
 143         /* command to read PHY dev address */
 144         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 145                 printf("Err..%s could not read PHY dev address\n",
 146                         __func__);
 147                 return;
 148         }
 149
 150         /*
 151          * Enable RGMII delay on Tx and Rx for CPU port
 152          * Ref: sec 4.7.2 of chip datasheet
 153          */
 154         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 155         miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
 156         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 157         miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
 158         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 159
 160         /* reset the phy */
 161         miiphy_reset(name, devadr);
 162
 163         printf("88E1118 Initialized on %s\n", name);
 164 }
 165
 166 /* Configure and enable Switch and PHY */
 167 void reset_phy(void)
 168 {
 169         /* configure and initialize PHY */
 170         mv_phy_88e1118_init("egiga0");
 171
 172 }
 173 #endif