2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
23 #include <fdt_support.h>
27 #include <linux/list.h>
31 #include <asm/arch/iomux-mx28.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/imx-regs.h>
34 #include <asm/arch/sys_proto.h>
36 #include "../common/karo.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 #define MXS_GPIO_NR(p, o) (((p) << 5) | (o))
42 #define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31
43 #define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30
44 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
46 #define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27
47 #define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20
48 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
49 #define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19
50 #define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18
52 #define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10
54 static const struct gpio tx28_gpios[] = {
55 { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
56 { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
57 { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
58 { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
59 { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
62 static const iomux_cfg_t tx28_pads[] = {
64 #if CONFIG_CONS_INDEX == 0
65 MX28_PAD_AUART0_RX__DUART_CTS,
66 MX28_PAD_AUART0_TX__DUART_RTS,
67 MX28_PAD_AUART0_CTS__DUART_RX,
68 MX28_PAD_AUART0_RTS__DUART_TX,
69 #elif CONFIG_CONS_INDEX == 1
70 MX28_PAD_AUART1_RX__AUART1_RX,
71 MX28_PAD_AUART1_TX__AUART1_TX,
72 MX28_PAD_AUART1_CTS__AUART1_CTS,
73 MX28_PAD_AUART1_RTS__AUART1_RTS,
74 #elif CONFIG_CONS_INDEX == 2
75 MX28_PAD_AUART3_RX__AUART3_RX,
76 MX28_PAD_AUART3_TX__AUART3_TX,
77 MX28_PAD_AUART3_CTS__AUART3_CTS,
78 MX28_PAD_AUART3_RTS__AUART3_RTS,
80 /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
81 MX28_PAD_I2C0_SCL__I2C0_SCL,
82 MX28_PAD_I2C0_SDA__I2C0_SDA,
85 MX28_PAD_SPDIF__GPIO_3_27,
86 MX28_PAD_JTAG_RTCK__GPIO_4_20,
88 /* USBOTG VBUSEN, OC, ID */
89 MX28_PAD_GPMI_CE2N__GPIO_0_18,
90 MX28_PAD_GPMI_CE3N__GPIO_0_19,
91 MX28_PAD_PWM2__GPIO_3_18,
98 /* provide at least _some_ sort of randomness */
103 static inline void random_init(void)
105 struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
109 for (i = 0; i < MAX_LOOPS; i++) {
110 unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds);
112 seed = get_timer(usec + random + seed);
118 int board_early_init_f(void)
122 /* IO0 clock at 480MHz */
123 mxs_set_ioclk(MXC_IOCLK0, 480000);
124 /* IO1 clock at 480MHz */
125 mxs_set_ioclk(MXC_IOCLK1, 480000);
127 /* SSP0 clock at 96MHz */
128 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
129 /* SSP2 clock at 96MHz */
130 mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
132 gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
133 mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
139 /* Address of boot parameters */
140 #ifdef CONFIG_OF_LIBFDT
141 gd->bd->bi_arch_number = -1;
143 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
149 return mxs_dram_init();
152 #ifdef CONFIG_CMD_MMC
153 static int tx28_mmc_wp(int dev_no)
158 int board_mmc_init(bd_t *bis)
160 return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
162 #endif /* CONFIG_CMD_MMC */
164 #ifdef CONFIG_FEC_MXC
165 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
167 #ifdef CONFIG_FEC_MXC_MULTI
168 #define FEC_MAX_IDX 1
170 #define FEC_MAX_IDX 0
176 static int fec_get_mac_addr(int index)
179 struct mxs_ocotp_regs *ocotp_regs =
180 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
181 u32 *cust = &ocotp_regs->hw_ocotp_cust0;
183 char env_name[] = "eth.addr";
187 if (index < 0 || index > FEC_MAX_IDX)
190 /* set this bit to open the OTP banks for reading */
191 writel(OCOTP_CTRL_RD_BANK_OPEN,
192 &ocotp_regs->hw_ocotp_ctrl_set);
194 /* wait until OTP contents are readable */
195 while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
201 for (i = 0; i < sizeof(mac); i++) {
202 int shift = 24 - i % 4 * 8;
205 val = readl(&cust[index * 8 + i]);
206 mac[i] = val >> shift;
208 if (!is_valid_ether_addr(mac))
212 snprintf(env_name, sizeof(env_name), "ethaddr");
214 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
216 eth_setenv_enetaddr(env_name, mac);
219 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
221 static const iomux_cfg_t tx28_fec_pads[] = {
222 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
223 MX28_PAD_ENET0_RXD0__ENET0_RXD0,
224 MX28_PAD_ENET0_RXD1__ENET0_RXD1,
227 int board_eth_init(bd_t *bis)
231 /* Reset the external phy */
232 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
234 /* Power on the external phy */
235 gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
237 /* Pull strap pins to high */
238 gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
239 gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
240 gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
241 gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
244 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
247 mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
249 ret = cpu_eth_init(bis);
251 printf("cpu_eth_init() failed: %d\n", ret);
255 ret = fec_get_mac_addr(0);
257 printf("Failed to read FEC0 MAC address from OCOTP\n");
260 #ifdef CONFIG_FEC_MXC_MULTI
261 if (getenv("ethaddr")) {
262 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
264 printf("FEC MXS: Unable to init FEC0\n");
269 ret = fec_get_mac_addr(1);
271 printf("Failed to read FEC1 MAC address from OCOTP\n");
274 if (getenv("eth1addr")) {
275 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
277 printf("FEC MXS: Unable to init FEC1\n");
283 if (getenv("ethaddr")) {
284 ret = fecmxc_initialize(bis);
289 #endif /* CONFIG_FEC_MXC */
297 void show_activity(int arg)
299 static int led_state = LED_STATE_INIT;
302 if (led_state == LED_STATE_INIT) {
304 gpio_set_value(TX28_LED_GPIO, 1);
305 led_state = LED_STATE_ON;
307 if (get_timer(last) > CONFIG_SYS_HZ) {
309 if (led_state == LED_STATE_ON) {
310 gpio_set_value(TX28_LED_GPIO, 0);
312 gpio_set_value(TX28_LED_GPIO, 1);
314 led_state = 1 - led_state;
319 static const iomux_cfg_t stk5_pads[] = {
320 /* SW controlled LED on STK5 baseboard */
321 MX28_PAD_ENET0_RXD3__GPIO_4_10,
324 static const struct gpio stk5_gpios[] = {
328 static ushort tx28_cmap[256];
329 vidinfo_t panel_info = {
330 /* set to max. size supported by SoC */
334 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
338 static struct fb_videomode tx28_fb_modes[] = {
340 /* Standard VGA timing */
345 .pixclock = KHZ2PICOS(25175),
352 .vmode = FB_VMODE_NONINTERLACED,
355 /* Emerging ETV570 640 x 480 display. Syncs low active,
356 * DE high active, 115.2 mm x 86.4 mm display area
357 * VGA compatible timing
363 .pixclock = KHZ2PICOS(25175),
370 .vmode = FB_VMODE_NONINTERLACED,
373 /* Emerging ET0350G0DH6 320 x 240 display.
374 * 70.08 mm x 52.56 mm display area.
380 .pixclock = KHZ2PICOS(6500),
381 .left_margin = 68 - 34,
384 .upper_margin = 18 - 3,
387 .vmode = FB_VMODE_NONINTERLACED,
390 /* Emerging ET0430G0DH6 480 x 272 display.
391 * 95.04 mm x 53.856 mm display area.
397 .pixclock = KHZ2PICOS(9000),
404 .vmode = FB_VMODE_NONINTERLACED,
407 /* Emerging ET0500G0DH6 800 x 480 display.
408 * 109.6 mm x 66.4 mm display area.
414 .pixclock = KHZ2PICOS(33260),
415 .left_margin = 216 - 128,
417 .right_margin = 1056 - 800 - 216,
418 .upper_margin = 35 - 2,
420 .lower_margin = 525 - 480 - 35,
421 .vmode = FB_VMODE_NONINTERLACED,
424 /* Emerging ETQ570G0DH6 320 x 240 display.
425 * 115.2 mm x 86.4 mm display area.
431 .pixclock = KHZ2PICOS(6400),
435 .upper_margin = 16, /* 15 according to datasheet */
436 .vsync_len = 3, /* TVP -> 1>x>5 */
437 .lower_margin = 4, /* 4.5 according to datasheet */
438 .vmode = FB_VMODE_NONINTERLACED,
441 /* Emerging ET0700G0DH6 800 x 480 display.
442 * 152.4 mm x 91.44 mm display area.
448 .pixclock = KHZ2PICOS(33260),
449 .left_margin = 216 - 128,
451 .right_margin = 1056 - 800 - 216,
452 .upper_margin = 35 - 2,
454 .lower_margin = 525 - 480 - 35,
455 .vmode = FB_VMODE_NONINTERLACED,
458 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
459 .vmode = FB_VMODE_NONINTERLACED,
463 static int lcd_enabled = 1;
465 void lcd_enable(void)
468 * global variable from common/lcd.c
469 * Set to 0 here to prevent messages from going to LCD
470 * rather than serial console
474 karo_load_splashimage(1);
476 debug("Switching LCD on\n");
477 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
479 gpio_set_value(TX28_LCD_RST_GPIO, 1);
481 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0);
485 void lcd_disable(void)
489 void lcd_panel_disable(void)
492 debug("Switching LCD off\n");
493 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1);
494 gpio_set_value(TX28_LCD_RST_GPIO, 0);
495 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
499 static const iomux_cfg_t stk5_lcd_pads[] = {
501 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
502 /* LCD POWER_ENABLE */
503 MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
504 /* LCD Backlight (PWM) */
505 MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
508 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
509 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
510 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
511 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
512 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
513 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
514 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
515 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
516 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
517 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
518 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
519 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
520 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
521 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
522 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
523 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
524 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
525 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
526 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
527 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
528 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
529 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
530 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
531 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
532 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
533 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
534 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
535 MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
536 MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
537 MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
538 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
541 static const struct gpio stk5_lcd_gpios[] = {
542 { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
543 { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
544 { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
547 extern void video_hw_init(void *lcdbase);
549 void lcd_ctrl_init(void *lcdbase)
551 int color_depth = 24;
555 struct fb_videomode *p = tx28_fb_modes;
556 struct fb_videomode fb_mode;
557 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
560 debug("LCD disabled\n");
565 debug("Disabling LCD\n");
572 vm = getenv("video_mode");
574 debug("Disabling LCD\n");
578 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
580 debug("Using video mode from FDT\n");
584 debug("Trying compiled-in video modes\n");
585 while (p->name != NULL) {
586 if (strcmp(p->name, vm) == 0) {
587 debug("Using video mode: '%s'\n", p->name);
594 debug("Trying to decode video_mode: '%s'\n", vm);
595 while (*vm != '\0') {
596 if (*vm >= '0' && *vm <= '9') {
599 val = simple_strtoul(vm, &end, 0);
602 if (val > panel_info.vl_col)
603 val = panel_info.vl_col;
606 } else if (!yres_set) {
607 if (val > panel_info.vl_row)
608 val = panel_info.vl_row;
611 } else if (!bpp_set) {
621 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
622 end - vm, vm, color_depth);
625 } else if (!refresh_set) {
652 if (p->xres == 0 || p->yres == 0) {
653 printf("Invalid video mode: %s\n", getenv("video_mode"));
655 printf("Supported video modes are:");
656 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
657 printf(" %s", p->name);
662 p->pixclock = KHZ2PICOS(refresh *
663 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
664 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
666 debug("Pixel clock set to %lu.%03lu MHz\n",
667 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
669 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
670 mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
671 ARRAY_SIZE(stk5_lcd_pads));
673 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
674 color_depth, refresh);
676 if (karo_load_splashimage(0) == 0) {
677 debug("Initializing LCD controller\n");
678 video_hw_init(lcdbase);
680 debug("Skipping initialization of LCD controller\n");
684 #define lcd_enabled 0
685 #endif /* CONFIG_LCD */
687 static void stk5_board_init(void)
689 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
690 mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
693 static void stk5v3_board_init(void)
698 static void stk5v5_board_init(void)
702 /* init flexcan transceiver enable GPIO */
703 gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
704 "Flexcan Transceiver");
705 mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
708 int board_late_init(void)
710 const char *baseboard;
714 baseboard = getenv("baseboard");
718 if (strncmp(baseboard, "stk5", 4) == 0) {
719 printf("Baseboard: %s\n", baseboard);
720 if ((strlen(baseboard) == 4) ||
721 strcmp(baseboard, "stk5-v3") == 0) {
723 } else if (strcmp(baseboard, "stk5-v5") == 0) {
724 const char *otg_mode = getenv("otg_mode");
726 if (otg_mode && strcmp(otg_mode, "host") == 0) {
727 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
728 otg_mode, baseboard);
729 setenv("otg_mode", "none");
733 printf("WARNING: Unsupported STK5 board rev.: %s\n",
737 printf("WARNING: Unsupported baseboard: '%s'\n",
747 printf("Board: Ka-Ro TX28-4%sxx\n", TX28_MOD_SUFFIX);
751 #if defined(CONFIG_OF_BOARD_SETUP)
752 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
753 #include <jffs2/jffs2.h>
754 #include <mtd_node.h>
755 struct node_info tx28_nand_nodes[] = {
756 { "gpmi-nand", MTD_DEV_TYPE_NAND, },
759 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
762 static void tx28_fixup_flexcan(void *blob)
764 karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80032000, "transceiver-switch");
765 karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80034000, "transceiver-switch");
768 static void tx28_fixup_fec(void *blob)
770 karo_fdt_enable_node(blob, "ethernet1", 0);
773 void ft_board_setup(void *blob, bd_t *bd)
775 const char *baseboard = getenv("baseboard");
778 /* TX28-41xx (aka TX28S) has no external RTC
779 * and no I2C GPIO extender
781 karo_fdt_remove_node(blob, "ds1339");
782 karo_fdt_remove_node(blob, "gpio5");
784 if (baseboard != NULL && strcmp(baseboard, "stk5-v5") == 0) {
785 karo_fdt_remove_node(blob, "stk5led");
787 tx28_fixup_flexcan(blob);
788 tx28_fixup_fec(blob);
791 if (baseboard != NULL && strcmp(baseboard, "stk5-v3") == 0) {
792 const char *otg_mode = getenv("otg_mode");
794 if (otg_mode && (strcmp(otg_mode, "device") == 0 ||
795 strcmp(otg_mode, "gadget") == 0))
796 karo_fdt_enable_node(blob, "can1", 0);
799 fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
800 fdt_fixup_ethernet(blob);
802 karo_fdt_fixup_touchpanel(blob);
803 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
804 karo_fdt_update_fb_mode(blob, getenv("video_mode"));