board/karo/tx28/tx28.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <linux/list.h>
  27 #include <linux/fb.h>
  28 #include <asm/io.h>
  29 #include <asm/gpio.h>
  30 #include <asm/arch/iomux-mx28.h>
  31 #include <asm/arch/clock.h>
  32 #include <asm/arch/imx-regs.h>
  33 #include <asm/arch/sys_proto.h>
  34
  35 #include "../common/karo.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #define MXS_GPIO_NR(p, o)      (((p) << 5) | (o))
  40
  41 #define TX28_LCD_PWR_GPIO       MX28_PAD_LCD_ENABLE__GPIO_1_31
  42 #define TX28_LCD_RST_GPIO       MX28_PAD_LCD_RESET__GPIO_3_30
  43 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
  44
  45 #define TX28_USBH_VBUSEN_GPIO   MX28_PAD_SPDIF__GPIO_3_27
  46 #define TX28_USBH_OC_GPIO       MX28_PAD_JTAG_RTCK__GPIO_4_20
  47 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
  48 #define TX28_USBOTG_OC_GPIO     MX28_PAD_GPMI_CE3N__GPIO_0_19
  49 #define TX28_USBOTG_ID_GPIO     MX28_PAD_PWM2__GPIO_3_18
  50
  51 #define TX28_LED_GPIO           MX28_PAD_ENET0_RXD3__GPIO_4_10
  52
  53 static const struct gpio tx28_gpios[] = {
  54         { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
  55         { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
  56         { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
  57         { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
  58         { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
  59 };
  60
  61 static const iomux_cfg_t tx28_pads[] = {
  62         /* UART pads */
  63 #if CONFIG_CONS_INDEX == 0
  64         MX28_PAD_AUART0_RX__DUART_CTS,
  65         MX28_PAD_AUART0_TX__DUART_RTS,
  66         MX28_PAD_AUART0_CTS__DUART_RX,
  67         MX28_PAD_AUART0_RTS__DUART_TX,
  68 #elif CONFIG_CONS_INDEX == 1
  69         MX28_PAD_AUART1_RX__AUART1_RX,
  70         MX28_PAD_AUART1_TX__AUART1_TX,
  71         MX28_PAD_AUART1_CTS__AUART1_CTS,
  72         MX28_PAD_AUART1_RTS__AUART1_RTS,
  73 #elif CONFIG_CONS_INDEX == 2
  74         MX28_PAD_AUART3_RX__AUART3_RX,
  75         MX28_PAD_AUART3_TX__AUART3_TX,
  76         MX28_PAD_AUART3_CTS__AUART3_CTS,
  77         MX28_PAD_AUART3_RTS__AUART3_RTS,
  78 #endif
  79         /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
  80         MX28_PAD_I2C0_SCL__I2C0_SCL,
  81         MX28_PAD_I2C0_SDA__I2C0_SDA,
  82
  83         /* USBH VBUSEN, OC */
  84         MX28_PAD_SPDIF__GPIO_3_27,
  85         MX28_PAD_JTAG_RTCK__GPIO_4_20,
  86
  87         /* USBOTG VBUSEN, OC, ID */
  88         MX28_PAD_GPMI_CE2N__GPIO_0_18,
  89         MX28_PAD_GPMI_CE3N__GPIO_0_19,
  90         MX28_PAD_PWM2__GPIO_3_18,
  91 };
  92
  93 /*
  94  * Functions
  95  */
  96
  97 /* provide at least _some_ sort of randomness */
  98 #define MAX_LOOPS       100
  99
 100 static u32 random;
 101
 102 static inline void random_init(void)
 103 {
 104         struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
 105         u32 seed = 0;
 106         int i;
 107
 108         for (i = 0; i < MAX_LOOPS; i++) {
 109                 unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds);
 110
 111                 seed = get_timer(usec + random + seed);
 112                 srand(seed);
 113                 random = rand();
 114         }
 115 }
 116
 117 #define RTC_PERSISTENT0_CLK32_MASK      (RTC_PERSISTENT0_CLOCKSOURCE |  \
 118                                         RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
 119 static u32 boot_cause __attribute__((section("data")));
 120
 121 int board_early_init_f(void)
 122 {
 123         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 124         u32 rtc_stat;
 125         int timeout = 5000;
 126
 127         random_init();
 128
 129         /* IO0 clock at 480MHz */
 130         mxs_set_ioclk(MXC_IOCLK0, 480000);
 131         /* IO1 clock at 480MHz */
 132         mxs_set_ioclk(MXC_IOCLK1, 480000);
 133
 134         /* SSP0 clock at 96MHz */
 135         mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 136         /* SSP2 clock at 96MHz */
 137         mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
 138
 139         gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
 140         mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
 141
 142         while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
 143                 RTC_STAT_STALE_REGS_PERSISTENT0) {
 144                 if (timeout-- < 0)
 145                         return 0;
 146                 udelay(1);
 147         }
 148         boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
 149         if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
 150                 RTC_PERSISTENT0_CLK32_MASK) {
 151                 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
 152                         goto rtc_err;
 153                 writel(RTC_PERSISTENT0_CLK32_MASK,
 154                         &rtc_regs->hw_rtc_persistent0_set);
 155         }
 156         return 0;
 157
 158 rtc_err:
 159         serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
 160         return 0;
 161 }
 162
 163 int board_init(void)
 164 {
 165         /* Address of boot parameters */
 166 #ifdef CONFIG_OF_LIBFDT
 167         gd->bd->bi_arch_number = -1;
 168 #endif
 169         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 170         return 0;
 171 }
 172
 173 int dram_init(void)
 174 {
 175         return mxs_dram_init();
 176 }
 177
 178 #ifdef  CONFIG_CMD_MMC
 179 static int tx28_mmc_wp(int dev_no)
 180 {
 181         return 0;
 182 }
 183
 184 int board_mmc_init(bd_t *bis)
 185 {
 186         return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
 187 }
 188 #endif /* CONFIG_CMD_MMC */
 189
 190 #ifdef CONFIG_FEC_MXC
 191 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
 192
 193 #ifdef CONFIG_FEC_MXC_MULTI
 194 #define FEC_MAX_IDX                     1
 195 #else
 196 #define FEC_MAX_IDX                     0
 197 #endif
 198 #ifndef ETH_ALEN
 199 #define ETH_ALEN                        6
 200 #endif
 201
 202 static int fec_get_mac_addr(int index)
 203 {
 204         int timeout = 1000;
 205         struct mxs_ocotp_regs *ocotp_regs =
 206                 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
 207         u32 *cust = &ocotp_regs->hw_ocotp_cust0;
 208         u8 mac[ETH_ALEN];
 209         char env_name[] = "eth.addr";
 210         u32 val = 0;
 211         int i;
 212
 213         if (index < 0 || index > FEC_MAX_IDX)
 214                 return -EINVAL;
 215
 216         /* set this bit to open the OTP banks for reading */
 217         writel(OCOTP_CTRL_RD_BANK_OPEN,
 218                 &ocotp_regs->hw_ocotp_ctrl_set);
 219
 220         /* wait until OTP contents are readable */
 221         while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
 222                 if (timeout-- < 0)
 223                         return -ETIMEDOUT;
 224                 udelay(100);
 225         }
 226
 227         for (i = 0; i < sizeof(mac); i++) {
 228                 int shift = 24 - i % 4 * 8;
 229
 230                 if (i % 4 == 0)
 231                         val = readl(&cust[index * 8 + i]);
 232                 mac[i] = val >> shift;
 233         }
 234         if (!is_valid_ether_addr(mac))
 235                 return 0;
 236
 237         if (index == 0) {
 238                 printf("MAC addr from fuse: %pM\n", mac);
 239                 snprintf(env_name, sizeof(env_name), "ethaddr");
 240         } else {
 241                 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
 242         }
 243         eth_setenv_enetaddr(env_name, mac);
 244         return 0;
 245 }
 246 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
 247
 248 static const iomux_cfg_t tx28_fec_pads[] = {
 249         MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
 250         MX28_PAD_ENET0_RXD0__ENET0_RXD0,
 251         MX28_PAD_ENET0_RXD1__ENET0_RXD1,
 252 };
 253
 254 int board_eth_init(bd_t *bis)
 255 {
 256         int ret;
 257
 258         /* Reset the external phy */
 259         gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
 260
 261         /* Power on the external phy */
 262         gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
 263
 264         /* Pull strap pins to high */
 265         gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
 266         gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
 267         gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
 268         gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
 269
 270         udelay(25000);
 271         gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
 272         udelay(100);
 273
 274         mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
 275
 276         ret = cpu_eth_init(bis);
 277         if (ret) {
 278                 printf("cpu_eth_init() failed: %d\n", ret);
 279                 return ret;
 280         }
 281
 282 #ifdef CONFIG_FEC_MXC_MULTI
 283         if (getenv("ethaddr")) {
 284                 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
 285                 if (ret) {
 286                         printf("FEC MXS: Unable to init FEC0\n");
 287                         return ret;
 288                 }
 289         }
 290
 291         if (getenv("eth1addr")) {
 292                 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
 293                 if (ret) {
 294                         printf("FEC MXS: Unable to init FEC1\n");
 295                         return ret;
 296                 }
 297         }
 298 #else
 299         if (getenv("ethaddr")) {
 300                 ret = fecmxc_initialize(bis);
 301                 if (ret) {
 302                         printf("FEC MXS: Unable to init FEC\n");
 303                         return ret;
 304                 }
 305         }
 306 #endif
 307         return 0;
 308 }
 309 #endif /* CONFIG_FEC_MXC */
 310
 311 enum {
 312         LED_STATE_INIT = -1,
 313         LED_STATE_OFF,
 314         LED_STATE_ON,
 315 };
 316
 317 void show_activity(int arg)
 318 {
 319         static int led_state = LED_STATE_INIT;
 320         static ulong last;
 321
 322         if (led_state == LED_STATE_INIT) {
 323                 last = get_timer(0);
 324                 gpio_set_value(TX28_LED_GPIO, 1);
 325                 led_state = LED_STATE_ON;
 326         } else {
 327                 if (get_timer(last) > CONFIG_SYS_HZ) {
 328                         last = get_timer(0);
 329                         if (led_state == LED_STATE_ON) {
 330                                 gpio_set_value(TX28_LED_GPIO, 0);
 331                         } else {
 332                                 gpio_set_value(TX28_LED_GPIO, 1);
 333                         }
 334                         led_state = 1 - led_state;
 335                 }
 336         }
 337 }
 338
 339 static const iomux_cfg_t stk5_pads[] = {
 340         /* SW controlled LED on STK5 baseboard */
 341         MX28_PAD_ENET0_RXD3__GPIO_4_10,
 342 };
 343
 344 static const struct gpio stk5_gpios[] = {
 345 };
 346
 347 #ifdef CONFIG_LCD
 348 static ushort tx28_cmap[256];
 349 vidinfo_t panel_info = {
 350         /* set to max. size supported by SoC */
 351         .vl_col = 1600,
 352         .vl_row = 1200,
 353
 354         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 355         .cmap = tx28_cmap,
 356 };
 357
 358 static struct fb_videomode tx28_fb_modes[] = {
 359         {
 360                 /* Standard VGA timing */
 361                 .name           = "VGA",
 362                 .refresh        = 60,
 363                 .xres           = 640,
 364                 .yres           = 480,
 365                 .pixclock       = KHZ2PICOS(25175),
 366                 .left_margin    = 48,
 367                 .hsync_len      = 96,
 368                 .right_margin   = 16,
 369                 .upper_margin   = 31,
 370                 .vsync_len      = 2,
 371                 .lower_margin   = 12,
 372                 .vmode          = FB_VMODE_NONINTERLACED,
 373         },
 374         {
 375                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 376                  * DE high active, 115.2 mm x 86.4 mm display area
 377                  * VGA compatible timing
 378                  */
 379                 .name           = "ETV570",
 380                 .refresh        = 60,
 381                 .xres           = 640,
 382                 .yres           = 480,
 383                 .pixclock       = KHZ2PICOS(25175),
 384                 .left_margin    = 114,
 385                 .hsync_len      = 30,
 386                 .right_margin   = 16,
 387                 .upper_margin   = 32,
 388                 .vsync_len      = 3,
 389                 .lower_margin   = 10,
 390                 .vmode          = FB_VMODE_NONINTERLACED,
 391         },
 392         {
 393                 /* Emerging ET0350G0DH6 320 x 240 display.
 394                  * 70.08 mm x 52.56 mm display area.
 395                  */
 396                 .name           = "ET0350",
 397                 .refresh        = 60,
 398                 .xres           = 320,
 399                 .yres           = 240,
 400                 .pixclock       = KHZ2PICOS(6500),
 401                 .left_margin    = 68 - 34,
 402                 .hsync_len      = 34,
 403                 .right_margin   = 20,
 404                 .upper_margin   = 18 - 3,
 405                 .vsync_len      = 3,
 406                 .lower_margin   = 4,
 407                 .vmode          = FB_VMODE_NONINTERLACED,
 408         },
 409         {
 410                 /* Emerging ET0430G0DH6 480 x 272 display.
 411                  * 95.04 mm x 53.856 mm display area.
 412                  */
 413                 .name           = "ET0430",
 414                 .refresh        = 60,
 415                 .xres           = 480,
 416                 .yres           = 272,
 417                 .pixclock       = KHZ2PICOS(9000),
 418                 .left_margin    = 2,
 419                 .hsync_len      = 41,
 420                 .right_margin   = 2,
 421                 .upper_margin   = 2,
 422                 .vsync_len      = 10,
 423                 .lower_margin   = 2,
 424                 .vmode          = FB_VMODE_NONINTERLACED,
 425         },
 426         {
 427                 /* Emerging ET0500G0DH6 800 x 480 display.
 428                  * 109.6 mm x 66.4 mm display area.
 429                  */
 430                 .name           = "ET0500",
 431                 .refresh        = 60,
 432                 .xres           = 800,
 433                 .yres           = 480,
 434                 .pixclock       = KHZ2PICOS(33260),
 435                 .left_margin    = 216 - 128,
 436                 .hsync_len      = 128,
 437                 .right_margin   = 1056 - 800 - 216,
 438                 .upper_margin   = 35 - 2,
 439                 .vsync_len      = 2,
 440                 .lower_margin   = 525 - 480 - 35,
 441                 .vmode          = FB_VMODE_NONINTERLACED,
 442         },
 443         {
 444                 /* Emerging ETQ570G0DH6 320 x 240 display.
 445                  * 115.2 mm x 86.4 mm display area.
 446                  */
 447                 .name           = "ETQ570",
 448                 .refresh        = 60,
 449                 .xres           = 320,
 450                 .yres           = 240,
 451                 .pixclock       = KHZ2PICOS(6400),
 452                 .left_margin    = 38,
 453                 .hsync_len      = 30,
 454                 .right_margin   = 30,
 455                 .upper_margin   = 16, /* 15 according to datasheet */
 456                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 457                 .lower_margin   = 4, /* 4.5 according to datasheet */
 458                 .vmode          = FB_VMODE_NONINTERLACED,
 459         },
 460         {
 461                 /* Emerging ET0700G0DH6 800 x 480 display.
 462                  * 152.4 mm x 91.44 mm display area.
 463                  */
 464                 .name           = "ET0700",
 465                 .refresh        = 60,
 466                 .xres           = 800,
 467                 .yres           = 480,
 468                 .pixclock       = KHZ2PICOS(33260),
 469                 .left_margin    = 216 - 128,
 470                 .hsync_len      = 128,
 471                 .right_margin   = 1056 - 800 - 216,
 472                 .upper_margin   = 35 - 2,
 473                 .vsync_len      = 2,
 474                 .lower_margin   = 525 - 480 - 35,
 475                 .vmode          = FB_VMODE_NONINTERLACED,
 476         },
 477         {
 478                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 479                 .vmode          = FB_VMODE_NONINTERLACED,
 480         },
 481 };
 482
 483 static int lcd_enabled = 1;
 484
 485 void lcd_enable(void)
 486 {
 487         /* HACK ALERT:
 488          * global variable from common/lcd.c
 489          * Set to 0 here to prevent messages from going to LCD
 490          * rather than serial console
 491          */
 492         lcd_is_enabled = 0;
 493
 494         karo_load_splashimage(1);
 495         if (lcd_enabled) {
 496                 debug("Switching LCD on\n");
 497                 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
 498                 udelay(100);
 499                 gpio_set_value(TX28_LCD_RST_GPIO, 1);
 500                 udelay(300000);
 501                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0);
 502         }
 503 }
 504
 505 void lcd_disable(void)
 506 {
 507 }
 508
 509 void lcd_panel_disable(void)
 510 {
 511         if (lcd_enabled) {
 512                 debug("Switching LCD off\n");
 513                 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1);
 514                 gpio_set_value(TX28_LCD_RST_GPIO, 0);
 515                 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
 516         }
 517 }
 518
 519 static const iomux_cfg_t stk5_lcd_pads[] = {
 520         /* LCD RESET */
 521         MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
 522         /* LCD POWER_ENABLE */
 523         MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
 524         /* LCD Backlight (PWM) */
 525         MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
 526
 527         /* Display */
 528         MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
 529         MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
 530         MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
 531         MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
 532         MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
 533         MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
 534         MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
 535         MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
 536         MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
 537         MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
 538         MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
 539         MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
 540         MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
 541         MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
 542         MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
 543         MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
 544         MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
 545         MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
 546         MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
 547         MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
 548         MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
 549         MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
 550         MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
 551         MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
 552         MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
 553         MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
 554         MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
 555         MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
 556         MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
 557         MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
 558         MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
 559 };
 560
 561 static const struct gpio stk5_lcd_gpios[] = {
 562         { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 563         { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 564         { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 565 };
 566
 567 extern void video_hw_init(void *lcdbase);
 568
 569 void lcd_ctrl_init(void *lcdbase)
 570 {
 571         int color_depth = 24;
 572         char *vm;
 573         unsigned long val;
 574         int refresh = 60;
 575         struct fb_videomode *p = tx28_fb_modes;
 576         struct fb_videomode fb_mode;
 577         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 578
 579         if (!lcd_enabled) {
 580                 debug("LCD disabled\n");
 581                 return;
 582         }
 583
 584         if (tstc()) {
 585                 debug("Disabling LCD\n");
 586                 lcd_enabled = 0;
 587                 return;
 588         }
 589
 590         karo_fdt_move_fdt();
 591
 592         vm = getenv("video_mode");
 593         if (vm == NULL) {
 594                 debug("Disabling LCD\n");
 595                 lcd_enabled = 0;
 596                 return;
 597         }
 598         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 599                 p = &fb_mode;
 600                 debug("Using video mode from FDT\n");
 601                 vm += strlen(vm);
 602         }
 603         if (p->name != NULL)
 604                 debug("Trying compiled-in video modes\n");
 605         while (p->name != NULL) {
 606                 if (strcmp(p->name, vm) == 0) {
 607                         debug("Using video mode: '%s'\n", p->name);
 608                         vm += strlen(vm);
 609                         break;
 610                 }
 611                 p++;
 612         }
 613         if (*vm != '\0')
 614                 debug("Trying to decode video_mode: '%s'\n", vm);
 615         while (*vm != '\0') {
 616                 if (*vm >= '0' && *vm <= '9') {
 617                         char *end;
 618
 619                         val = simple_strtoul(vm, &end, 0);
 620                         if (end > vm) {
 621                                 if (!xres_set) {
 622                                         if (val > panel_info.vl_col)
 623                                                 val = panel_info.vl_col;
 624                                         p->xres = val;
 625                                         xres_set = 1;
 626                                 } else if (!yres_set) {
 627                                         if (val > panel_info.vl_row)
 628                                                 val = panel_info.vl_row;
 629                                         p->yres = val;
 630                                         yres_set = 1;
 631                                 } else if (!bpp_set) {
 632                                         switch (val) {
 633                                         case 8:
 634                                         case 16:
 635                                         case 18:
 636                                         case 24:
 637                                                 color_depth = val;
 638                                                 break;
 639
 640                                         default:
 641                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 642                                                         end - vm, vm, color_depth);
 643                                         }
 644                                         bpp_set = 1;
 645                                 } else if (!refresh_set) {
 646                                         refresh = val;
 647                                         refresh_set = 1;
 648                                 }
 649                         }
 650                         vm = end;
 651                 }
 652                 switch (*vm) {
 653                 case '@':
 654                         bpp_set = 1;
 655                         /* fallthru */
 656                 case '-':
 657                         yres_set = 1;
 658                         /* fallthru */
 659                 case 'x':
 660                         xres_set = 1;
 661                         /* fallthru */
 662                 case 'M':
 663                 case 'R':
 664                         vm++;
 665                         break;
 666
 667                 default:
 668                         if (*vm != '\0')
 669                                 vm++;
 670                 }
 671         }
 672         if (p->xres == 0 || p->yres == 0) {
 673                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 674                 lcd_enabled = 0;
 675                 printf("Supported video modes are:");
 676                 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
 677                         printf(" %s", p->name);
 678                 }
 679                 printf("\n");
 680                 return;
 681         }
 682         panel_info.vl_col = p->xres;
 683         panel_info.vl_row = p->yres;
 684
 685         switch (color_depth) {
 686         case 8:
 687                 panel_info.vl_bpix = LCD_COLOR8;
 688                 break;
 689         case 16:
 690                 panel_info.vl_bpix = LCD_COLOR16;
 691                 break;
 692         default:
 693                 panel_info.vl_bpix = LCD_COLOR24;
 694         }
 695
 696         p->pixclock = KHZ2PICOS(refresh *
 697                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 698                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 699                                 1000);
 700         debug("Pixel clock set to %lu.%03lu MHz\n",
 701                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 702
 703         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 704         mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
 705                                 ARRAY_SIZE(stk5_lcd_pads));
 706
 707         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
 708                 color_depth, refresh);
 709
 710         if (karo_load_splashimage(0) == 0) {
 711                 char vmode[32];
 712
 713                 /* setup env variable for mxsfb display driver */
 714                 snprintf(vmode, sizeof(vmode), "%dx%dMR-%d@%d",
 715                         p->xres, p->yres, color_depth, refresh);
 716                 setenv("videomode", vmode);
 717
 718                 debug("Initializing LCD controller\n");
 719                 video_hw_init(lcdbase);
 720                 setenv("videomode", NULL);
 721         } else {
 722                 debug("Skipping initialization of LCD controller\n");
 723         }
 724 }
 725 #else
 726 #define lcd_enabled 0
 727 #endif /* CONFIG_LCD */
 728
 729 static void stk5_board_init(void)
 730 {
 731         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 732         mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 733 }
 734
 735 static void stk5v3_board_init(void)
 736 {
 737         stk5_board_init();
 738 }
 739
 740 static void stk5v5_board_init(void)
 741 {
 742         stk5_board_init();
 743
 744         /* init flexcan transceiver enable GPIO */
 745         gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
 746                         "Flexcan Transceiver");
 747         mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
 748 }
 749
 750 int tx28_fec1_enabled(void)
 751 {
 752         const char *status;
 753         int off;
 754
 755         if (!gd->fdt_blob)
 756                 return 0;
 757
 758         off = fdt_path_offset(gd->fdt_blob, "ethernet1");
 759         if (off < 0)
 760                 return 0;
 761
 762         status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
 763         return status && (strcmp(status, "okay") == 0);
 764 }
 765
 766 int board_late_init(void)
 767 {
 768         int ret;
 769         const char *baseboard;
 770
 771         karo_fdt_move_fdt();
 772
 773         baseboard = getenv("baseboard");
 774         if (!baseboard)
 775                 return 0;
 776
 777         if (strncmp(baseboard, "stk5", 4) == 0) {
 778                 printf("Baseboard: %s\n", baseboard);
 779                 if ((strlen(baseboard) == 4) ||
 780                         strcmp(baseboard, "stk5-v3") == 0) {
 781                         stk5v3_board_init();
 782                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 783                         const char *otg_mode = getenv("otg_mode");
 784
 785                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
 786                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
 787                                         otg_mode, baseboard);
 788                                 setenv("otg_mode", "none");
 789                         }
 790                         stk5v5_board_init();
 791                 } else {
 792                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 793                                 baseboard + 4);
 794                 }
 795         } else {
 796                 printf("WARNING: Unsupported baseboard: '%s'\n",
 797                         baseboard);
 798                 return -EINVAL;
 799         }
 800
 801         ret = fec_get_mac_addr(0);
 802         if (ret < 0) {
 803                 printf("Failed to read FEC0 MAC address from OCOTP\n");
 804                 return ret;
 805         }
 806 #ifdef CONFIG_FEC_MXC_MULTI
 807         if (tx28_fec1_enabled()) {
 808                 ret = fec_get_mac_addr(1);
 809                 if (ret < 0) {
 810                         printf("Failed to read FEC1 MAC address from OCOTP\n");
 811                         return ret;
 812                 }
 813         }
 814 #endif
 815         return 0;
 816 }
 817
 818 #define BOOT_CAUSE_MASK         (RTC_PERSISTENT0_EXTERNAL_RESET |       \
 819                                 RTC_PERSISTENT0_ALARM_WAKE |            \
 820                                 RTC_PERSISTENT0_THERMAL_RESET)
 821
 822 static void thermal_init(void)
 823 {
 824         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 825         struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
 826
 827         writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
 828                 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
 829                 &power_regs->hw_power_thermal);
 830
 831         writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
 832                 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
 833                 &clkctrl_regs->hw_clkctrl_reset);
 834 }
 835
 836 int checkboard(void)
 837 {
 838         struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
 839         u32 pwr_sts = readl(&power_regs->hw_power_sts);
 840         u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
 841         const char *dlm = "";
 842
 843         printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
 844                 CONFIG_SDRAM_SIZE / SZ_128M);
 845
 846         printf("POWERUP Source: ");
 847         if (pwrup_src & (3 << 0)) {
 848                 printf("%sPSWITCH %s voltage", dlm,
 849                         pwrup_src & (1 << 1) ? "HIGH" : "MID");
 850                 dlm = " | ";
 851         }
 852         if (pwrup_src & (1 << 4)) {
 853                 printf("%sRTC", dlm);
 854                 dlm = " | ";
 855         }
 856         if (pwrup_src & (1 << 5)) {
 857                 printf("%s5V", dlm);
 858                 dlm = " | ";
 859         }
 860         printf("\n");
 861
 862         if (boot_cause & BOOT_CAUSE_MASK) {
 863                 dlm="";
 864                 printf("Last boot cause: ");
 865                 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
 866                         printf("%sEXTERNAL", dlm);
 867                         dlm = " | ";
 868                 }
 869                 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
 870                         printf("%sTHERMAL", dlm);
 871                         dlm = " | ";
 872                 }
 873                 if (*dlm != '\0')
 874                         printf(" RESET");
 875                 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
 876                         printf("%sALARM WAKE", dlm);
 877                         dlm = " | ";
 878                 }
 879                 printf("\n");
 880         }
 881
 882         while (pwr_sts & POWER_STS_THERMAL_WARNING) {
 883                 static int first = 1;
 884
 885                 if (first) {
 886                         printf("CPU too hot to boot\n");
 887                         first = 0;
 888                 }
 889                 if (tstc())
 890                         break;
 891                 pwr_sts = readl(&power_regs->hw_power_sts);
 892         }
 893
 894         if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
 895                 thermal_init();
 896
 897         return 0;
 898 }
 899
 900 #if defined(CONFIG_OF_BOARD_SETUP)
 901 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 902 #include <jffs2/jffs2.h>
 903 #include <mtd_node.h>
 904 struct node_info tx28_nand_nodes[] = {
 905         { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
 906 };
 907 #else
 908 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 909 #endif
 910
 911 static const char *tx28_touchpanels[] = {
 912         "ti,tsc2007",
 913         "edt,edt-ft5x06",
 914         "fsl,imx28-lradc",
 915 };
 916
 917 void ft_board_setup(void *blob, bd_t *bd)
 918 {
 919         const char *baseboard = getenv("baseboard");
 920         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
 921
 922 #ifdef CONFIG_TX28_S
 923         /* TX28-41xx (aka TX28S) has no external RTC
 924          * and no I2C GPIO extender
 925          */
 926         karo_fdt_remove_node(blob, "ds1339");
 927         karo_fdt_remove_node(blob, "gpio5");
 928 #endif
 929         if (stk5_v5) {
 930                 karo_fdt_remove_node(blob, "stk5led");
 931         }
 932
 933         fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
 934         fdt_fixup_ethernet(blob);
 935
 936         karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
 937                                 ARRAY_SIZE(tx28_touchpanels));
 938         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
 939         karo_fdt_fixup_flexcan(blob, stk5_v5);
 940         karo_fdt_update_fb_mode(blob, getenv("video_mode"));
 941 }
 942 #endif /* CONFIG_OF_BOARD_SETUP */