2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/regs-pinctrl.h>
26 #include <asm/arch/pinctrl.h>
27 #include <asm/arch/regs-clkctrl.h>
28 #include <asm/arch/regs-ocotp.h>
29 #include <asm/errno.h>
32 #include <imx_ssp_mmc.h>
34 /* This should be removed after it's added into mach-types.h */
36 static const int mach_type = MACH_TYPE_TX28;
38 DECLARE_GLOBAL_DATA_PTR;
40 #ifdef CONFIG_IMX_SSP_MMC
43 static struct pin_desc mmc0_pins_desc[] = {
44 { PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
45 { PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
46 { PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
47 { PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
48 { PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
49 { PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
50 { PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
51 { PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
52 { PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
53 { PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
54 { PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
57 static struct pin_group mmc0_pins = {
58 .pins = mmc0_pins_desc,
59 .nr_pins = ARRAY_SIZE(mmc0_pins_desc)
62 struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = {
63 {REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0},
64 {REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1},
69 static struct pin_desc enet_pins_desc[] = {
70 { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
71 { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
72 { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
73 { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
74 { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
75 { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
76 { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
77 { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
78 { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }
81 static struct pin_group enet_pins = {
82 .pins = enet_pins_desc,
83 .nr_pins = ARRAY_SIZE(enet_pins_desc),
86 static struct pin_desc duart_pins_desc[] = {
87 { PINID_PWM0, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
88 { PINID_PWM1, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
89 { PINID_I2C0_SCL, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
90 { PINID_I2C0_SDA, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
92 { PINID_AUART0_RTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
93 { PINID_AUART0_CTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
94 { PINID_AUART0_TX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
95 { PINID_AUART0_RX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
98 static struct pin_group duart_pins = {
99 .pins = duart_pins_desc,
100 .nr_pins = ARRAY_SIZE(duart_pins_desc),
103 static struct pin_desc gpmi_pins_desc[] = {
104 { PINID_GPMI_D00, PIN_FUN1, },
105 { PINID_GPMI_D01, PIN_FUN1, },
106 { PINID_GPMI_D02, PIN_FUN1, },
107 { PINID_GPMI_D03, PIN_FUN1, },
108 { PINID_GPMI_D04, PIN_FUN1, },
109 { PINID_GPMI_D05, PIN_FUN1, },
110 { PINID_GPMI_D06, PIN_FUN1, },
111 { PINID_GPMI_D07, PIN_FUN1, },
112 { PINID_GPMI_CE0N, PIN_FUN1, },
113 { PINID_GPMI_RDY0, PIN_FUN1, },
114 { PINID_GPMI_RDN, PIN_FUN1, },
115 { PINID_GPMI_WRN, PIN_FUN1, },
116 { PINID_GPMI_ALE, PIN_FUN1, },
117 { PINID_GPMI_CLE, PIN_FUN1, },
118 { PINID_GPMI_RESETN, PIN_FUN1, },
121 static struct pin_group gpmi_pins = {
122 .pins = gpmi_pins_desc,
123 .nr_pins = ARRAY_SIZE(gpmi_pins_desc),
129 static void duart_init(void)
131 pin_set_group(&duart_pins);
136 gd->bd->bi_arch_number = mach_type;
138 /* Address of boot parameters */
139 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
147 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
148 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
153 #ifdef CONFIG_IMX_SSP_MMC
155 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
156 int get_mmc_env_devno(void)
158 unsigned long global_boot_mode;
160 global_boot_mode = REG_RD_ADDR(GLOBAL_BOOT_MODE_ADDR);
161 return ((global_boot_mode & 0xf) == BOOT_MODE_SD1) ? 1 : 0;
166 u32 ssp_mmc_is_wp(struct mmc *mmc)
171 int ssp_mmc_gpio_init(bd_t *bis)
176 for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM; index++) {
179 /* Set up MMC pins */
180 pin_set_group(&mmc0_pins);
184 printf("Warning: more ssp mmc controllers configured(%d) than supported by the board(2)\n",
185 CONFIG_SYS_SSP_MMC_NUM);
188 status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]);
194 int board_mmc_init(bd_t *bis)
196 if (!ssp_mmc_gpio_init(bis))
204 #if defined(CONFIG_MXC_FEC) && defined(CONFIG_GET_FEC_MAC_ADDR_FROM_IIM)
205 int fec_get_mac_addr(unsigned char *mac)
210 /* set this bit to open the OTP banks for reading */
211 REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET,
212 BM_OCOTP_CTRL_RD_BANK_OPEN);
214 /* wait until OTP contents are readable */
215 while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL)) {
221 val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0));
222 mac[0] = (val >> 24) & 0xFF;
223 mac[1] = (val >> 16) & 0xFF;
224 mac[2] = (val >> 8) & 0xFF;
225 mac[3] = (val >> 0) & 0xFF;
226 val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(1));
227 mac[4] = (val >> 24) & 0xFF;
228 mac[5] = (val >> 16) & 0xFF;
234 void enet_board_init(void)
236 /* Set up ENET pins */
237 pin_set_group(&enet_pins);
239 /* Power on the external phy */
240 pin_gpio_set(PINID_PWM4, 1);
241 pin_gpio_direction(PINID_PWM4, 1);
242 pin_set_type(PINID_PWM4, PIN_GPIO);
244 /* Reset the external phy */
245 pin_gpio_set(PINID_ENET0_RX_CLK, 0);
246 pin_gpio_direction(PINID_ENET0_RX_CLK, 1);
247 pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO);
249 pin_gpio_set(PINID_ENET0_RX_CLK, 1);
252 #ifdef CONFIG_MXS_NAND
253 #include <linux/mtd/nand.h>
254 extern int mxs_gpmi_nand_init(struct mtd_info *mtd, struct nand_chip *chip);
256 int board_nand_init(struct mtd_info *mtd, struct nand_chip *chip)
258 pin_set_group(&gpmi_pins);
259 return mxs_gpmi_nand_init(mtd, chip);
265 printf("Board: Ka-Ro TX28\n");