2 * board/karo/tx48/spl.c
3 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
21 #include <fdt_support.h>
25 #include <linux/mtd/nand.h>
27 #include <asm/cache.h>
28 #include <asm/omap_common.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/ddr_defs.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/arch/nand.h>
36 #include <asm/arch/clock.h>
38 #include <asm/arch/da8xx-fb.h>
40 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
41 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
42 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
43 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
44 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
46 #define GMII_SEL (CTRL_BASE + 0x650)
49 #define UART_SYSCFG_OFFSET 0x54
50 #define UART_SYSSTS_OFFSET 0x58
52 #define UART_RESET (0x1 << 1)
53 #define UART_RESETDONE (1 << 0)
54 #define UART_IDLE_MODE(m) (((m) << 3) & UART_IDLE_MODE_MASK)
55 #define UART_IDLE_MODE_MASK (0x3 << 3)
58 #define TSICR_REG 0x54
59 #define TIOCP_CFG_REG 0x10
62 /* RGMII mode define */
63 #define RGMII_MODE_ENABLE 0xA
64 #define RMII_MODE_ENABLE 0x5
65 #define MII_MODE_ENABLE 0x0
67 #define NO_OF_MAC_ADDR 1
70 #define MUX_CFG(value, offset) { \
71 __raw_writel(value, (CTRL_BASE + (offset))); \
74 /* PAD Control Fields */
75 #define SLEWCTRL (0x1 << 6)
76 #define RXACTIVE (0x1 << 5)
77 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
78 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
79 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
80 #define MODE(val) (val)
82 DECLARE_GLOBAL_DATA_PTR;
86 * Field names corresponds to the pad signal name
178 int ecap0_in_pwm0_out;
197 int xdma_event_intr0;
198 int xdma_event_intr1;
302 #define PAD_CTRL_BASE 0x800
303 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
306 static struct pin_mux tx48_pins[] = {
307 #ifdef CONFIG_CMD_NAND
308 { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */
309 { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */
310 { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */
311 { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */
312 { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */
313 { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */
314 { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */
315 { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */
316 { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */
317 { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */
318 { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */
319 { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */
320 { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */
321 { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */
322 { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */
325 { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */
326 { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */
328 #ifndef CONFIG_NO_ETH
330 { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */
331 { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */
332 { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */
333 { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */
334 { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */
335 { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */
336 { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */
337 { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */
338 { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */
339 { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */
340 { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */
341 { OFFSET(emu1), MODE(7), }, /* nRST */
345 static struct gpio tx48_gpios[] = {
346 /* configure this pin early to prevent flicker of the LCD */
347 { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
350 static struct pin_mux tx48_mmc_pins[] = {
351 #ifdef CONFIG_OMAP_HSMMC
353 { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */
354 { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */
355 { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */
356 { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */
357 { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */
358 { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */
359 { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */
364 * Configure the pin mux for the module
366 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
371 for (i = 0; i < num_pins; i++)
372 MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
375 static struct pin_mux tx48_uart0_pins[] = {
376 #ifdef CONFIG_SYS_NS16550_COM1
377 /* UART0 for early boot messages */
378 { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */
379 { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */
380 { OFFSET(uart0_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART0_CTS */
381 { OFFSET(uart0_rtsn), MODE(0) | PULLUDEN, }, /* UART0_RTS */
383 #ifdef CONFIG_SYS_NS16550_COM2
385 { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */
386 { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */
387 { OFFSET(uart1_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART1_CTS */
388 { OFFSET(uart1_rtsn), MODE(0) | PULLUDEN, }, /* UART1_RTS */
390 #ifdef CONFIG_SYS_NS16550_COM3
392 { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART5_RXD */
393 { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART5_TXD */
394 { OFFSET(mmc0_dat1), MODE(2) | PULLUP_EN | RXACTIVE, }, /* UART5_CTS */
395 { OFFSET(mmc0_dat0), MODE(2) | PULLUDEN, }, /* UART5_RTS */
400 * early system init of muxing and clocks.
402 static void enable_uart0_pin_mux(void)
404 tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins));
407 static void enable_mmc0_pin_mux(void)
409 tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins));
412 #define SDRAM_CLK CONFIG_SYS_DDR_CLK
414 #define ns_TO_ck(ns) (((ns) * SDRAM_CLK + 999) / 1000)
415 #define ck_TO_ns(ck) ((ck) * 1000 / SDRAM_CLK)
418 static inline unsigned ck_val_check(unsigned ck, unsigned offs, unsigned max,
422 printf("value %u for parameter %s is out of range (min: %u\n",
427 printf("value %u for parameter %s is out of range (max: %u\n",
433 #define CK_VAL(ck, offs, max) ck_val_check(ck, offs, max, #ck)
435 #define CK_VAL(ck, offs, max) ((ck) - (offs))
438 #define DDR3_NT5CB128 1
439 #define DDR3_H5TQ2G8 2
442 #define SDRAM_TYPE DDR3_NT5CB128
444 #define SDRAM_TYPE DDR3_H5TQ2G8
448 #error No SDRAM_TYPE specified
449 #elif (SDRAM_TYPE == DDR3_NT5CB128) || (SDRAM_TYPE == DDR3_H5TQ2G8)
450 #define tRP ns_TO_ck(14)
451 #define tRCD ns_TO_ck(14)
452 #define tWR ns_TO_ck(15)
453 #define tRAS ns_TO_ck(35)
454 #define tRC ns_TO_ck(49)
455 #define tRRD max(ns_TO_ck(8), 4)
456 #define tWTR max(ns_TO_ck(8), 4)
458 #define tXP max(ns_TO_ck(6), 3)
459 #define tXPR max(5, ns_TO_ck(ck_TO_ns(tRFC + 1) + 10))
460 #define tODT ns_TO_ck(9)
461 #define tXSNR max(5, ns_TO_ck(ck_TO_ns(tRFC + 1) + 10))
463 #define tRTP max(ns_TO_ck(8), 4)
464 #define tCKE max(ns_TO_ck(6), 3)
468 #define tRFC ns_TO_ck(160)
471 static inline int cwl(u32 sdram_clk)
473 if (sdram_clk <= 300)
475 else if (sdram_clk > 300 && sdram_clk <= 333)
477 else if (sdram_clk > 333 && sdram_clk <= 400)
479 else if (sdram_clk > 400 && sdram_clk <= 533)
481 else if (sdram_clk > 533 && sdram_clk <= 666)
483 else if (SDRAM_TYPE != DDR3_H5TQ2G8)
485 else if (sdram_clk > 666 && sdram_clk <= 800)
488 printf("SDRAM clock out of range\n");
491 #define CWL cwl(SDRAM_CLK)
493 static inline int cl(u32 sdram_clk)
495 if (sdram_clk <= 300)
497 else if (sdram_clk > 300 && sdram_clk <= 333)
499 else if (sdram_clk > 333 && sdram_clk <= 400)
501 else if (sdram_clk > 400 && sdram_clk <= 533)
503 else if (sdram_clk > 533 && sdram_clk <= 666)
504 return (SDRAM_TYPE == DDR3_H5TQ2G8) ? 10 : 9;
505 else if (SDRAM_TYPE != DDR3_H5TQ2G8)
507 else if (sdram_clk > 666 && sdram_clk <= 800)
510 printf("SDRAM clock out of range\n");
513 #define CL cl(SDRAM_CLK)
515 #define ROW_ADDR_BITS 14
516 #define SDRAM_PG_SIZE 1024
518 #error Unsupported SDRAM_TYPE specified
521 #define SDRAM_CONFIG_VAL ( \
522 (3 << 29) /* SDRAM type: 0: DDR1 1: LPDDR1 2: DDR2 3: DDR3 */ | \
523 (0 << 27) /* IBANK pos */ | \
524 (2 << 24) /* termination resistor value 0: disable 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ | \
525 (0 << 23) /* DDR2 differential DQS */ | \
526 (1 << 21) /* dynamic ODT 0: off 1: RZQ/4 2: RZQ/2 */ | \
527 (0 << 20) /* DLL disable */ | \
528 (1 << 18) /* drive strength 0: RZQ/6 1: RZQ/7 */ | \
529 ((CWL - 5) << 16) /* CWL 0: 5 ... 3: 8 */ | \
530 (1 << 14) /* SDRAM data bus width 0: 32 1: 16 */ | \
531 (((CL - 4) * 2) << 10) /* CAS latency 2: 5 4: 6 6: 8 ... 14: 11 (DDR3) */ | \
532 ((ROW_ADDR_BITS - 9) << 7) /* # of row addr bits 0: 9 ... 7: 16 */ | \
533 (3 << 4) /* # of SDRAM internal banks 0: 1 1: 2 2: 4 3: 8 */ | \
534 (0 << 3) /* # of CS lines */ | \
535 ((ffs(SDRAM_PG_SIZE / 256) - 1) << 0) /* page size 0: 256 1: 512 2: 1024 3:2048 */ | \
538 #define SDREF_VAL ( \
540 (1 << 29) /* self refresh temperature range 1: extended temp range */ | \
541 (0 << 28) /* auto self refresh enable */ | \
542 (0 << 24) /* partial array self refresh */ | \
543 ((SDRAM_CLK * 7800 / 1000) << 0) /* refresh interval */ | \
546 #define tFAW ns_TO_ck(45)
548 #define SDRAM_TIM1_VAL ((CK_VAL(tRP, 1, 16) << 25) | \
549 (CK_VAL(tRCD, 1, 16) << 21) | \
550 (CK_VAL(tWR, 1, 16) << 17) | \
551 (CK_VAL(tRAS, 1, 32) << 12) | \
552 (CK_VAL(tRC, 1, 64) << 6) | \
553 (CK_VAL(tRRD, 1, 8) << 3) | \
554 (CK_VAL(tWTR, 1, 8) << 0))
556 #define SDRAM_TIM2_VAL ((CK_VAL(max(tCKE, tXP), 1, 8) << 28) | \
557 (CK_VAL(tODT, 0, 8) << 25) | \
558 (CK_VAL(tXSNR, 1, 128) << 16) | \
559 (CK_VAL(tXSRD, 1, 1024) << 6) | \
560 (CK_VAL(tRTP, 1, 8) << 3) | \
561 (CK_VAL(tCKE, 1, 8) << 0))
563 #define SDRAM_TIM3_VAL ((CK_VAL(DIV_ROUND_UP(tPDLL_UL, 128), 0, 16) << 28) | \
564 (CK_VAL(tZQCS, 1, 64) << 15) | \
565 (CK_VAL(tRFC, 1, 1024) << 4) | \
566 (CK_VAL(tRAS_MAX, 0, 16) << 0))
568 #define ZQ_CONFIG_VAL ( \
569 (1 << 31) /* ZQ calib for CS1 */ | \
570 (0 << 30) /* ZQ calib for CS0 */ | \
571 (0 << 29) /* dual calib */ | \
572 (1 << 28) /* ZQ calib on SR/PWDN exit */ | \
573 (2 << 18) /* ZQCL intervals for ZQINIT */ | \
574 (4 << 16) /* ZQCS intervals for ZQCL */ | \
575 (80 << 0) /* refr periods between ZQCS commands */ | \
578 static struct ddr_data tx48_ddr3_data = {
580 .datardsratio0 = 0x04010040,
581 .datawdsratio0 = 0x0,
582 .datafwsratio0 = 0x0,
583 .datawrsratio0 = 0x04010040,
587 static struct cmd_control tx48_ddr3_cmd_ctrl_data = {
597 static void ddr3_calib_start(void)
599 static struct emif_reg_struct *emif_reg = (void *)EMIF4_0_CFG_BASE;
604 debug("Starting DDR3 calibration\n");
606 /* wait for DDR PHY ready */
607 while (!((emif_status = readl(&emif_reg->emif_status)) & (1 << 2))) {
608 if (loops++ > 100000)
612 debug("EMIF status: %08x after %u loops\n", emif_status, loops);
614 /* enable DDR3 write levelling */
616 writel(EMIF_REG_RDWRLVLFULL_START_MASK, &emif_reg->emif_rd_wr_lvl_ctl);
618 regval = readl(&emif_reg->emif_rd_wr_lvl_ctl);
619 if (!(regval & EMIF_REG_RDWRLVLFULL_START_MASK))
622 } while (loops++ < 100000);
623 if (regval & EMIF_REG_RDWRLVLFULL_START_MASK) {
624 printf("Full WRLVL timed out\n");
626 debug("Full Write Levelling done after %u us\n", loops);
628 writel(0, &emif_reg->emif_rd_wr_lvl_rmp_ctl);
629 writel(0, &emif_reg->emif_rd_wr_lvl_rmp_win);
630 writel(0x0f808080, &emif_reg->emif_rd_wr_lvl_ctl);
631 debug("DDR3 calibration done\n");
634 static void tx48_ddr_init(void)
636 struct emif_regs r = {0};
638 debug("Initialising SDRAM timing for %u MHz DDR clock\n", SDRAM_CLK);
640 r.sdram_config = SDRAM_CONFIG_VAL;
641 r.ref_ctrl = SDREF_VAL;
642 r.sdram_tim1 = SDRAM_TIM1_VAL;
643 r.sdram_tim2 = SDRAM_TIM2_VAL;
644 r.sdram_tim3 = SDRAM_TIM3_VAL;
645 r.zq_config = ZQ_CONFIG_VAL;
646 r.emif_ddr_phy_ctlr_1 = 0x0000030b;
648 config_ddr(SDRAM_CLK, 0x04, &tx48_ddr3_data,
649 &tx48_ddr3_cmd_ctrl_data, &r, 0);
653 debug("%s: config_ddr done\n", __func__);
656 #ifdef CONFIG_HW_WATCHDOG
657 static inline void tx48_wdog_disable(void)
661 static inline void tx48_wdog_disable(void)
663 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
665 /* WDT1 is already running when the bootloader gets control
666 * Disable it to avoid "random" resets
668 writel(0xAAAA, &wdtimer->wdtwspr);
669 while (readl(&wdtimer->wdtwwps) != 0x0)
671 writel(0x5555, &wdtimer->wdtwspr);
672 while (readl(&wdtimer->wdtwwps) != 0x0)
679 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
682 /* Setup the PLLs and the clocks for the peripherals */
687 enable_uart0_pin_mux();
690 writel(readl(&uart_base->uartsyscfg) | UART_RESET,
691 &uart_base->uartsyscfg);
692 while (!(readl(&uart_base->uartsyssts) & UART_RESETDONE)) {
698 /* Disable smart idle */
699 writel((readl(&uart_base->uartsyscfg) & ~UART_IDLE_MODE_MASK) |
700 UART_IDLE_MODE(1), &uart_base->uartsyscfg);
704 preloader_console_init();
707 printf("Timeout waiting for UART RESET\n");
717 enable_mmc0_pin_mux();
719 gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
720 tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins));