2 * board/karo/tx48/spl.c
3 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
21 #include <fdt_support.h>
25 #include <linux/mtd/nand.h>
27 #include <asm/cache.h>
28 #include <asm/omap_common.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/ddr_defs.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/arch/nand.h>
36 #include <asm/arch/clock.h>
38 #include <asm/arch/da8xx-fb.h>
40 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
41 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
42 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
43 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
44 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
46 #define GMII_SEL (CTRL_BASE + 0x650)
49 #define UART_SYSCFG_OFFSET 0x54
50 #define UART_SYSSTS_OFFSET 0x58
52 #define UART_RESET (0x1 << 1)
53 #define UART_CLK_RUNNING_MASK 0x1
54 #define UART_SMART_IDLE_EN (0x1 << 0x3)
57 #define TSICR_REG 0x54
58 #define TIOCP_CFG_REG 0x10
61 /* RGMII mode define */
62 #define RGMII_MODE_ENABLE 0xA
63 #define RMII_MODE_ENABLE 0x5
64 #define MII_MODE_ENABLE 0x0
66 #define NO_OF_MAC_ADDR 1
69 #define MUX_CFG(value, offset) { \
70 __raw_writel(value, (CTRL_BASE + (offset))); \
73 /* PAD Control Fields */
74 #define SLEWCTRL (0x1 << 6)
75 #define RXACTIVE (0x1 << 5)
76 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
77 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
78 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
79 #define MODE(val) (val)
83 * Field names corresponds to the pad signal name
175 int ecap0_in_pwm0_out;
194 int xdma_event_intr0;
195 int xdma_event_intr1;
299 #define PAD_CTRL_BASE 0x800
300 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
303 static struct pin_mux tx48_pins[] = {
304 #ifdef CONFIG_CMD_NAND
305 { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */
306 { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */
307 { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */
308 { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */
309 { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */
310 { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */
311 { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */
312 { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */
313 { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */
314 { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */
315 { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */
316 { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */
317 { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */
318 { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */
319 { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */
322 { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */
323 { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */
325 #ifndef CONFIG_NO_ETH
327 { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */
328 { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */
329 { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */
330 { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */
331 { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */
332 { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */
333 { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */
334 { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */
335 { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */
336 { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */
337 { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */
338 { OFFSET(emu1), MODE(7), }, /* nRST */
342 static struct gpio tx48_gpios[] = {
343 /* configure this pin early to prevent flicker of the LCD */
344 { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
347 static struct pin_mux tx48_mmc_pins[] = {
348 #ifdef CONFIG_OMAP_HSMMC
350 { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */
351 { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */
352 { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */
353 { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */
354 { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */
355 { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */
356 { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */
361 * Configure the pin mux for the module
363 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
368 for (i = 0; i < num_pins; i++)
369 MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
372 static struct pin_mux tx48_uart0_pins[] = {
373 #ifdef CONFIG_SYS_NS16550_COM1
374 /* UART0 for early boot messages */
375 { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */
376 { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */
377 { OFFSET(uart0_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART0_CTS */
378 { OFFSET(uart0_rtsn), MODE(0) | PULLUDEN, }, /* UART0_RTS */
380 #ifdef CONFIG_SYS_NS16550_COM2
382 { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */
383 { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */
384 { OFFSET(uart1_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART1_CTS */
385 { OFFSET(uart1_rtsn), MODE(0) | PULLUDEN, }, /* UART1_RTS */
387 #ifdef CONFIG_SYS_NS16550_COM3
389 { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART5_RXD */
390 { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART5_TXD */
391 { OFFSET(mmc0_dat1), MODE(2) | PULLUP_EN | RXACTIVE, }, /* UART5_CTS */
392 { OFFSET(mmc0_dat0), MODE(2) | PULLUDEN, }, /* UART5_RTS */
397 * early system init of muxing and clocks.
399 void enable_uart0_pin_mux(void)
401 tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins));
404 void enable_mmc0_pin_mux(void)
406 tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins));
409 static const struct ddr_data tx48_ddr3_data = {
410 .datardsratio0 = MT41J128MJT125_RD_DQS,
411 .datawdsratio0 = MT41J128MJT125_WR_DQS,
412 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
413 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
414 .datadldiff0 = PHY_DLL_LOCK_DIFF,
417 static const struct cmd_control tx48_ddr3_cmd_ctrl_data = {
418 .cmd0csratio = MT41J128MJT125_RATIO,
419 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
420 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
422 .cmd1csratio = MT41J128MJT125_RATIO,
423 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
424 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
426 .cmd2csratio = MT41J128MJT125_RATIO,
427 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
428 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
431 static struct emif_regs tx48_ddr3_emif_reg_data = {
432 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
433 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
434 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
435 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
436 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
437 .zq_config = MT41J128MJT125_ZQ_CFG,
438 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
443 #ifndef CONFIG_HW_WATCHDOG
444 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
446 /* WDT1 is already running when the bootloader gets control
447 * Disable it to avoid "random" resets
449 writel(0xAAAA, &wdtimer->wdtwspr);
450 while (readl(&wdtimer->wdtwwps) != 0x0)
452 writel(0x5555, &wdtimer->wdtwspr);
453 while (readl(&wdtimer->wdtwwps) != 0x0)
456 /* Setup the PLLs and the clocks for the peripherals */
461 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
463 enable_uart0_pin_mux();
465 regVal = readl(&uart_base->uartsyscfg);
466 regVal |= UART_RESET;
467 writel(regVal, &uart_base->uartsyscfg);
468 while ((readl(&uart_base->uartsyssts) &
469 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
472 /* Disable smart idle */
473 regVal = readl(&uart_base->uartsyscfg);
474 regVal |= UART_SMART_IDLE_EN;
475 writel(regVal, &uart_base->uartsyscfg);
477 /* Initialize the Timer */
480 preloader_console_init();
482 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &tx48_ddr3_data,
483 &tx48_ddr3_cmd_ctrl_data, &tx48_ddr3_emif_reg_data);
486 enable_mmc0_pin_mux();
488 gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
489 tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins));