board/karo/tx51/tx51.c

   1 /*
   2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <libfdt.h>
  22 #include <fdt_support.h>
  23 #include <lcd.h>
  24 #include <netdev.h>
  25 #include <mmc.h>
  26 #include <fsl_esdhc.h>
  27 #include <video_fb.h>
  28 #include <ipu.h>
  29 #include <mxcfb.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/iomux-mx51.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40
  41 #define TX51_FEC_RST_GPIO       IMX_GPIO_NR(2, 14)
  42 #define TX51_FEC_PWR_GPIO       IMX_GPIO_NR(1, 3)
  43 #define TX51_FEC_INT_GPIO       IMX_GPIO_NR(3, 18)
  44 #define TX51_LED_GPIO           IMX_GPIO_NR(4, 10)
  45
  46 #define TX51_LCD_PWR_GPIO       IMX_GPIO_NR(4, 14)
  47 #define TX51_LCD_RST_GPIO       IMX_GPIO_NR(4, 13)
  48 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
  49
  50 #define TX51_RESET_OUT_GPIO     IMX_GPIO_NR(2, 15)
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  55
  56 #define FEC_PAD_CTRL            MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
  57                                         PAD_CTL_SRE_FAST)
  58 #define FEC_PAD_CTRL2           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
  59 #define GPIO_PAD_CTRL           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
  60
  61 static iomux_v3_cfg_t tx51_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* RESET_OUT */
  65         MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
  66
  67         /* UART pads */
  68 #if CONFIG_MXC_UART_BASE == UART1_BASE
  69         MX51_PAD_UART1_RXD__UART1_RXD,
  70         MX51_PAD_UART1_TXD__UART1_TXD,
  71         MX51_PAD_UART1_RTS__UART1_RTS,
  72         MX51_PAD_UART1_CTS__UART1_CTS,
  73 #endif
  74 #if CONFIG_MXC_UART_BASE == UART2_BASE
  75         MX51_PAD_UART2_RXD__UART2_RXD,
  76         MX51_PAD_UART2_TXD__UART2_TXD,
  77         MX51_PAD_EIM_D26__UART2_RTS,
  78         MX51_PAD_EIM_D25__UART2_CTS,
  79 #endif
  80 #if CONFIG_MXC_UART_BASE == UART3_BASE
  81         MX51_PAD_UART3_RXD__UART3_RXD,
  82         MX51_PAD_UART3_TXD__UART3_TXD,
  83         MX51_PAD_EIM_D18__UART3_RTS,
  84         MX51_PAD_EIM_D17__UART3_CTS,
  85 #endif
  86         /* internal I2C */
  87         MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
  88         MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
  89
  90         /* FEC PHY GPIO functions */
  91         MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL,    /* PHY POWER */
  92         MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL,   /* PHY RESET */
  93         MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
  94
  95         /* FEC functions */
  96         MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
  97         MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
  98         MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
  99         MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
 100         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
 101         MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
 102         MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
 103         MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
 104         MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
 105         MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
 106
 107         /* strap pins for PHY configuration */
 108         MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
 109         MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL,  /* RXD0/Mode0 */
 110         MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL,   /* RXD1/Mode1 */
 111         MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL,   /* RXD2/Mode2 */
 112         MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL,   /* RXD3/nINTSEL */
 113         MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
 114         MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL,   /* CRS/PHYAD4 */
 115
 116         /* unusable pins on TX51 */
 117         MX51_PAD_GPIO1_0__GPIO1_0,
 118         MX51_PAD_GPIO1_1__GPIO1_1,
 119 };
 120
 121 static const struct gpio tx51_gpios[] = {
 122         /* RESET_OUT */
 123         { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
 124
 125         /* FEC PHY control GPIOs */
 126         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
 127         { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
 128         { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },         /* PHY INT (TX_ER) */
 129
 130         /* FEC PHY strap pins */
 131         { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", },  /* RX_CLK/REGOFF */
 132         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", },   /* RXD0/Mode0 */
 133         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", },   /* RXD1/Mode1 */
 134         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", },   /* RXD2/Mode2 */
 135         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
 136         { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", },    /* COL/RMII/CRSDV */
 137         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", },  /* CRS/PHYAD4 */
 138
 139         /* module internal I2C bus */
 140         { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
 141         { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
 142
 143         /* Unconnected pins */
 144         { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 145         { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 146 };
 147
 148 /*
 149  * Functions
 150  */
 151 /* placed in section '.data' to prevent overwriting relocation info
 152  * overlayed with bss
 153  */
 154 static u32 wrsr __attribute__((section(".data")));
 155
 156 #define WRSR_POR        (1 << 4)
 157 #define WRSR_TOUT       (1 << 1)
 158 #define WRSR_SFTW       (1 << 0)
 159
 160 static void print_reset_cause(void)
 161 {
 162         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 163         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 164         u32 srsr;
 165         char *dlm = "";
 166
 167         printf("Reset cause: ");
 168
 169         srsr = readl(&src_regs->srsr);
 170         wrsr = readw(wdt_base + 4);
 171
 172         if (wrsr & WRSR_POR) {
 173                 printf("%sPOR", dlm);
 174                 dlm = " | ";
 175         }
 176         if (srsr & 0x00004) {
 177                 printf("%sCSU", dlm);
 178                 dlm = " | ";
 179         }
 180         if (srsr & 0x00008) {
 181                 printf("%sIPP USER", dlm);
 182                 dlm = " | ";
 183         }
 184         if (srsr & 0x00010) {
 185                 if (wrsr & WRSR_SFTW) {
 186                         printf("%sSOFT", dlm);
 187                         dlm = " | ";
 188                 }
 189                 if (wrsr & WRSR_TOUT) {
 190                         printf("%sWDOG", dlm);
 191                         dlm = " | ";
 192                 }
 193         }
 194         if (srsr & 0x00020) {
 195                 printf("%sJTAG HIGH-Z", dlm);
 196                 dlm = " | ";
 197         }
 198         if (srsr & 0x00040) {
 199                 printf("%sJTAG SW", dlm);
 200                 dlm = " | ";
 201         }
 202         if (srsr & 0x10000) {
 203                 printf("%sWARM BOOT", dlm);
 204                 dlm = " | ";
 205         }
 206         if (dlm[0] == '\0')
 207                 printf("unknown");
 208
 209         printf("\n");
 210 }
 211
 212 static void tx51_print_cpuinfo(void)
 213 {
 214         u32 cpurev;
 215
 216         cpurev = get_cpu_rev();
 217
 218         printf("CPU:   Freescale i.MX51 rev%d.%d at %d MHz\n",
 219                 (cpurev & 0x000F0) >> 4,
 220                 (cpurev & 0x0000F) >> 0,
 221                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 222
 223         print_reset_cause();
 224 }
 225
 226 int board_early_init_f(void)
 227 {
 228         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 229
 230         gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
 231         imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
 232
 233         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 234         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 235
 236         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 237         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 238         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 239         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 240         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 241
 242         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 243         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 244
 245         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 246         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 247         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 248         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 249         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 250
 251         writel(0xffcfffff, &ccm_regs->CCGR0);
 252         writel(0x003fffff, &ccm_regs->CCGR1);
 253         writel(0x030c003c, &ccm_regs->CCGR2);
 254         writel(0x000000ff, &ccm_regs->CCGR3);
 255         writel(0x00000000, &ccm_regs->CCGR4);
 256         writel(0x003fc003, &ccm_regs->CCGR5);
 257         writel(0x00000000, &ccm_regs->CCGR6);
 258         writel(0x00000000, &ccm_regs->cmeor);
 259 #ifdef CONFIG_CMD_BOOTCE
 260         /* WinCE fails to enable these clocks */
 261         writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
 262         writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
 263         writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
 264 #endif
 265         return 0;
 266 }
 267
 268 int board_init(void)
 269 {
 270         /* Address of boot parameters */
 271         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 272
 273         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 274                 printf("CTRL-C detected; Skipping boot critical setup\n");
 275                 return 1;
 276         }
 277         return 0;
 278 }
 279
 280 int dram_init(void)
 281 {
 282         int ret;
 283
 284         /* dram_init must store complete ramsize in gd->ram_size */
 285         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 286                                 PHYS_SDRAM_1_SIZE);
 287
 288         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 289                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 290         if (ret)
 291                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 292                         CONFIG_SYS_SDRAM_CLK, ret);
 293         else
 294                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 295                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 296                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 297                         CONFIG_SYS_SDRAM_CLK);
 298         return ret;
 299 }
 300
 301 void dram_init_banksize(void)
 302 {
 303         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 304         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 305                         PHYS_SDRAM_1_SIZE);
 306 #if CONFIG_NR_DRAM_BANKS > 1
 307         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 308         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 309                         PHYS_SDRAM_2_SIZE);
 310 #endif
 311 }
 312
 313 #ifdef  CONFIG_CMD_MMC
 314 static const iomux_v3_cfg_t mmc0_pads[] = {
 315         MX51_PAD_SD1_CMD__SD1_CMD,
 316         MX51_PAD_SD1_CLK__SD1_CLK,
 317         MX51_PAD_SD1_DATA0__SD1_DATA0,
 318         MX51_PAD_SD1_DATA1__SD1_DATA1,
 319         MX51_PAD_SD1_DATA2__SD1_DATA2,
 320         MX51_PAD_SD1_DATA3__SD1_DATA3,
 321         /* SD1 CD */
 322         MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
 323 };
 324
 325 static const iomux_v3_cfg_t mmc1_pads[] = {
 326         MX51_PAD_SD2_CMD__SD2_CMD,
 327         MX51_PAD_SD2_CLK__SD2_CLK,
 328         MX51_PAD_SD2_DATA0__SD2_DATA0,
 329         MX51_PAD_SD2_DATA1__SD2_DATA1,
 330         MX51_PAD_SD2_DATA2__SD2_DATA2,
 331         MX51_PAD_SD2_DATA3__SD2_DATA3,
 332         /* SD2 CD */
 333         MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
 334 };
 335
 336 static struct tx51_esdhc_cfg {
 337         const iomux_v3_cfg_t *pads;
 338         int num_pads;
 339         struct fsl_esdhc_cfg cfg;
 340         int cd_gpio;
 341 } tx51_esdhc_cfg[] = {
 342         {
 343                 .pads = mmc0_pads,
 344                 .num_pads = ARRAY_SIZE(mmc0_pads),
 345                 .cfg = {
 346                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 347                         .max_bus_width = 4,
 348                 },
 349                 .cd_gpio = IMX_GPIO_NR(3, 8),
 350         },
 351         {
 352                 .pads = mmc1_pads,
 353                 .num_pads = ARRAY_SIZE(mmc1_pads),
 354                 .cfg = {
 355                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 356                         .max_bus_width = 4,
 357                 },
 358                 .cd_gpio = IMX_GPIO_NR(3, 6),
 359         },
 360 };
 361
 362 static inline struct tx51_esdhc_cfg *to_tx51_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 363 {
 364         return container_of(cfg, struct tx51_esdhc_cfg, cfg);
 365 }
 366
 367 int board_mmc_getcd(struct mmc *mmc)
 368 {
 369         struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
 370
 371         if (cfg->cd_gpio < 0)
 372                 return cfg->cd_gpio;
 373
 374         debug("SD card %d is %spresent\n",
 375                 cfg - tx51_esdhc_cfg,
 376                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 377         return !gpio_get_value(cfg->cd_gpio);
 378 }
 379
 380 int board_mmc_init(bd_t *bis)
 381 {
 382         int i;
 383
 384         for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
 385                 struct mmc *mmc;
 386                 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
 387                 int ret;
 388
 389                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 390                                                 cfg->num_pads);
 391                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 392
 393                 ret = gpio_request_one(cfg->cd_gpio,
 394                                 GPIOF_INPUT, "MMC CD");
 395                 if (ret) {
 396                         printf("Error %d requesting GPIO%d_%d\n",
 397                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 398                         continue;
 399                 }
 400
 401                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 402                 fsl_esdhc_initialize(bis, &cfg->cfg);
 403
 404                 mmc = find_mmc_device(i);
 405                 if (mmc == NULL)
 406                         continue;
 407                 if (board_mmc_getcd(mmc) > 0)
 408                         mmc_init(mmc);
 409         }
 410         return 0;
 411 }
 412 #endif /* CONFIG_CMD_MMC */
 413
 414 #ifdef CONFIG_FEC_MXC
 415
 416 #ifndef ETH_ALEN
 417 #define ETH_ALEN 6
 418 #endif
 419
 420 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 421 {
 422         int i;
 423         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 424         struct fuse_bank *bank = &iim->bank[1];
 425         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 426
 427         if (dev_id > 0)
 428                 return;
 429
 430         for (i = 0; i < ETH_ALEN; i++)
 431                 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
 432 }
 433
 434 static iomux_v3_cfg_t tx51_fec_pads[] = {
 435         /* reconfigure strap pins for FEC function */
 436         MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
 437         MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
 438         MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
 439         MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
 440         MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
 441         MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
 442         MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
 443 };
 444
 445 /* take bit 4 of PHY address from configured PHY address or
 446  * set it to 0 if PHYADDR is -1 (probe for PHY)
 447  */
 448 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
 449
 450 static struct gpio tx51_fec_gpios[] = {
 451         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
 452         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", },       /* RXD0/Mode0 */
 453         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", },       /* RXD1/Mode1 */
 454         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", },       /* RXD2/Mode2 */
 455         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", },     /* RXD3/nINTSEL */
 456 #if PHYAD4
 457         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 458 #else
 459         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 460 #endif
 461 };
 462
 463 int board_eth_init(bd_t *bis)
 464 {
 465         int ret;
 466
 467         /* Power up the external phy and assert strap options */
 468         gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
 469
 470         /* delay at least 21ms for the PHY internal POR signal to deassert */
 471         udelay(22000);
 472
 473         /* Deassert RESET to the external phy */
 474         gpio_set_value(TX51_FEC_RST_GPIO, 1);
 475
 476         /* Without this delay the PHY won't work, though nothing in
 477          * the datasheets suggests that it should be necessary!
 478          */
 479         udelay(400);
 480         imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
 481                                         ARRAY_SIZE(tx51_fec_pads));
 482
 483         ret = cpu_eth_init(bis);
 484         if (ret)
 485                 printf("cpu_eth_init() failed: %d\n", ret);
 486
 487         return ret;
 488 }
 489 #endif /* CONFIG_FEC_MXC */
 490
 491 enum {
 492         LED_STATE_INIT = -1,
 493         LED_STATE_OFF,
 494         LED_STATE_ON,
 495 };
 496
 497 void show_activity(int arg)
 498 {
 499         static int led_state = LED_STATE_INIT;
 500         static ulong last;
 501
 502         if (led_state == LED_STATE_INIT) {
 503                 last = get_timer(0);
 504                 gpio_set_value(TX51_LED_GPIO, 1);
 505                 led_state = LED_STATE_ON;
 506         } else {
 507                 if (get_timer(last) > CONFIG_SYS_HZ) {
 508                         last = get_timer(0);
 509                         if (led_state == LED_STATE_ON) {
 510                                 gpio_set_value(TX51_LED_GPIO, 0);
 511                         } else {
 512                                 gpio_set_value(TX51_LED_GPIO, 1);
 513                         }
 514                         led_state = 1 - led_state;
 515                 }
 516         }
 517 }
 518
 519 static const iomux_v3_cfg_t stk5_pads[] = {
 520         /* SW controlled LED on STK5 baseboard */
 521         MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
 522
 523         /* USB PHY reset */
 524         MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
 525         /* USBOTG OC */
 526         MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
 527         /* USB PHY clock enable */
 528         MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
 529         /* USBH1 VBUS enable */
 530         MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
 531         /* USBH1 OC */
 532         MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
 533 };
 534
 535 static const struct gpio stk5_gpios[] = {
 536         { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 537
 538         { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
 539         { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
 540         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
 541         { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 542         { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
 543 };
 544
 545 #ifdef CONFIG_LCD
 546 static u16 tx51_cmap[256];
 547 vidinfo_t panel_info = {
 548         /* set to max. size supported by SoC */
 549         .vl_col = 1600,
 550         .vl_row = 1200,
 551
 552         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 553         .cmap = tx51_cmap,
 554 };
 555
 556 static struct fb_videomode tx51_fb_modes[] = {
 557         {
 558                 /* Standard VGA timing */
 559                 .name           = "VGA",
 560                 .refresh        = 60,
 561                 .xres           = 640,
 562                 .yres           = 480,
 563                 .pixclock       = KHZ2PICOS(25175),
 564                 .left_margin    = 48,
 565                 .hsync_len      = 96,
 566                 .right_margin   = 16,
 567                 .upper_margin   = 31,
 568                 .vsync_len      = 2,
 569                 .lower_margin   = 12,
 570                 .sync           = FB_SYNC_CLK_LAT_FALL,
 571         },
 572         {
 573                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 574                  * DE high active, 115.2 mm x 86.4 mm display area
 575                  * VGA compatible timing
 576                  */
 577                 .name           = "ETV570",
 578                 .refresh        = 60,
 579                 .xres           = 640,
 580                 .yres           = 480,
 581                 .pixclock       = KHZ2PICOS(25175),
 582                 .left_margin    = 114,
 583                 .hsync_len      = 30,
 584                 .right_margin   = 16,
 585                 .upper_margin   = 32,
 586                 .vsync_len      = 3,
 587                 .lower_margin   = 10,
 588                 .sync           = FB_SYNC_CLK_LAT_FALL,
 589         },
 590         {
 591                 /* Emerging ET0350G0DH6 320 x 240 display.
 592                  * 70.08 mm x 52.56 mm display area.
 593                  */
 594                 .name           = "ET0350",
 595                 .refresh        = 60,
 596                 .xres           = 320,
 597                 .yres           = 240,
 598                 .pixclock       = KHZ2PICOS(6500),
 599                 .left_margin    = 68 - 34,
 600                 .hsync_len      = 34,
 601                 .right_margin   = 20,
 602                 .upper_margin   = 18 - 3,
 603                 .vsync_len      = 3,
 604                 .lower_margin   = 4,
 605                 .sync           = FB_SYNC_CLK_LAT_FALL,
 606         },
 607         {
 608                 /* Emerging ET0430G0DH6 480 x 272 display.
 609                  * 95.04 mm x 53.856 mm display area.
 610                  */
 611                 .name           = "ET0430",
 612                 .refresh        = 60,
 613                 .xres           = 480,
 614                 .yres           = 272,
 615                 .pixclock       = KHZ2PICOS(9000),
 616                 .left_margin    = 2,
 617                 .hsync_len      = 41,
 618                 .right_margin   = 2,
 619                 .upper_margin   = 2,
 620                 .vsync_len      = 10,
 621                 .lower_margin   = 2,
 622                 .sync           = FB_SYNC_CLK_LAT_FALL,
 623         },
 624         {
 625                 /* Emerging ET0500G0DH6 800 x 480 display.
 626                  * 109.6 mm x 66.4 mm display area.
 627                  */
 628                 .name           = "ET0500",
 629                 .refresh        = 60,
 630                 .xres           = 800,
 631                 .yres           = 480,
 632                 .pixclock       = KHZ2PICOS(33260),
 633                 .left_margin    = 216 - 128,
 634                 .hsync_len      = 128,
 635                 .right_margin   = 1056 - 800 - 216,
 636                 .upper_margin   = 35 - 2,
 637                 .vsync_len      = 2,
 638                 .lower_margin   = 525 - 480 - 35,
 639                 .sync           = FB_SYNC_CLK_LAT_FALL,
 640         },
 641         {
 642                 /* Emerging ETQ570G0DH6 320 x 240 display.
 643                  * 115.2 mm x 86.4 mm display area.
 644                  */
 645                 .name           = "ETQ570",
 646                 .refresh        = 60,
 647                 .xres           = 320,
 648                 .yres           = 240,
 649                 .pixclock       = KHZ2PICOS(6400),
 650                 .left_margin    = 38,
 651                 .hsync_len      = 30,
 652                 .right_margin   = 30,
 653                 .upper_margin   = 16, /* 15 according to datasheet */
 654                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 655                 .lower_margin   = 4, /* 4.5 according to datasheet */
 656                 .sync           = FB_SYNC_CLK_LAT_FALL,
 657         },
 658         {
 659                 /* Emerging ET0700G0DH6 800 x 480 display.
 660                  * 152.4 mm x 91.44 mm display area.
 661                  */
 662                 .name           = "ET0700",
 663                 .refresh        = 60,
 664                 .xres           = 800,
 665                 .yres           = 480,
 666                 .pixclock       = KHZ2PICOS(33260),
 667                 .left_margin    = 216 - 128,
 668                 .hsync_len      = 128,
 669                 .right_margin   = 1056 - 800 - 216,
 670                 .upper_margin   = 35 - 2,
 671                 .vsync_len      = 2,
 672                 .lower_margin   = 525 - 480 - 35,
 673                 .sync           = FB_SYNC_CLK_LAT_FALL,
 674         },
 675         {
 676                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 677                 .refresh        = 60,
 678                 .left_margin    = 48,
 679                 .hsync_len      = 96,
 680                 .right_margin   = 16,
 681                 .upper_margin   = 31,
 682                 .vsync_len      = 2,
 683                 .lower_margin   = 12,
 684                 .sync           = FB_SYNC_CLK_LAT_FALL,
 685         },
 686 };
 687
 688 static int lcd_enabled = 1;
 689 static int lcd_bl_polarity;
 690
 691 static int lcd_backlight_polarity(void)
 692 {
 693         return lcd_bl_polarity;
 694 }
 695
 696 void lcd_enable(void)
 697 {
 698         /* HACK ALERT:
 699          * global variable from common/lcd.c
 700          * Set to 0 here to prevent messages from going to LCD
 701          * rather than serial console
 702          */
 703         lcd_is_enabled = 0;
 704
 705         if (lcd_enabled) {
 706                 karo_load_splashimage(1);
 707
 708                 debug("Switching LCD on\n");
 709                 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
 710                 udelay(100);
 711                 gpio_set_value(TX51_LCD_RST_GPIO, 1);
 712                 udelay(300000);
 713                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
 714                         lcd_backlight_polarity());
 715         }
 716 }
 717
 718 void lcd_disable(void)
 719 {
 720         if (lcd_enabled) {
 721                 printf("Disabling LCD\n");
 722                 ipuv3_fb_shutdown();
 723         }
 724 }
 725
 726 void lcd_panel_disable(void)
 727 {
 728         if (lcd_enabled) {
 729                 debug("Switching LCD off\n");
 730                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO,
 731                         !lcd_backlight_polarity());
 732                 gpio_set_value(TX51_LCD_RST_GPIO, 0);
 733                 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
 734         }
 735 }
 736
 737 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 738         /* LCD RESET */
 739         MX51_PAD_CSI2_VSYNC__GPIO4_13,
 740         /* LCD POWER_ENABLE */
 741         MX51_PAD_CSI2_HSYNC__GPIO4_14,
 742         /* LCD Backlight (PWM) */
 743         MX51_PAD_GPIO1_2__GPIO1_2,
 744
 745         /* Display */
 746         MX51_PAD_DISP1_DAT0__DISP1_DAT0,
 747         MX51_PAD_DISP1_DAT1__DISP1_DAT1,
 748         MX51_PAD_DISP1_DAT2__DISP1_DAT2,
 749         MX51_PAD_DISP1_DAT3__DISP1_DAT3,
 750         MX51_PAD_DISP1_DAT4__DISP1_DAT4,
 751         MX51_PAD_DISP1_DAT5__DISP1_DAT5,
 752         MX51_PAD_DISP1_DAT6__DISP1_DAT6,
 753         MX51_PAD_DISP1_DAT7__DISP1_DAT7,
 754         MX51_PAD_DISP1_DAT8__DISP1_DAT8,
 755         MX51_PAD_DISP1_DAT9__DISP1_DAT9,
 756         MX51_PAD_DISP1_DAT10__DISP1_DAT10,
 757         MX51_PAD_DISP1_DAT11__DISP1_DAT11,
 758         MX51_PAD_DISP1_DAT12__DISP1_DAT12,
 759         MX51_PAD_DISP1_DAT13__DISP1_DAT13,
 760         MX51_PAD_DISP1_DAT14__DISP1_DAT14,
 761         MX51_PAD_DISP1_DAT15__DISP1_DAT15,
 762         MX51_PAD_DISP1_DAT16__DISP1_DAT16,
 763         MX51_PAD_DISP1_DAT17__DISP1_DAT17,
 764         MX51_PAD_DISP1_DAT18__DISP1_DAT18,
 765         MX51_PAD_DISP1_DAT19__DISP1_DAT19,
 766         MX51_PAD_DISP1_DAT20__DISP1_DAT20,
 767         MX51_PAD_DISP1_DAT21__DISP1_DAT21,
 768         MX51_PAD_DISP1_DAT22__DISP1_DAT22,
 769         MX51_PAD_DISP1_DAT23__DISP1_DAT23,
 770         MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
 771         MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
 772 };
 773
 774 static const struct gpio stk5_lcd_gpios[] = {
 775         { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 776         { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 777         { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 778 };
 779
 780 void lcd_ctrl_init(void *lcdbase)
 781 {
 782         int color_depth = 24;
 783         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 784         const char *vm;
 785         unsigned long val;
 786         int refresh = 60;
 787         struct fb_videomode *p = &tx51_fb_modes[0];
 788         struct fb_videomode fb_mode;
 789         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 790         int pix_fmt;
 791         int lcd_bus_width;
 792         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 793         unsigned long di_clk_rate = 65000000;
 794
 795         if (!lcd_enabled) {
 796                 debug("LCD disabled\n");
 797                 return;
 798         }
 799
 800         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 801                 debug("Disabling LCD\n");
 802                 lcd_enabled = 0;
 803                 setenv("splashimage", NULL);
 804                 return;
 805         }
 806
 807         karo_fdt_move_fdt();
 808         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 809
 810         if (video_mode == NULL) {
 811                 debug("Disabling LCD\n");
 812                 lcd_enabled = 0;
 813                 return;
 814         }
 815         vm = video_mode;
 816         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 817                 p = &fb_mode;
 818                 debug("Using video mode from FDT\n");
 819                 vm += strlen(vm);
 820                 if (fb_mode.xres > panel_info.vl_col ||
 821                         fb_mode.yres > panel_info.vl_row) {
 822                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 823                                 fb_mode.xres, fb_mode.yres,
 824                                 panel_info.vl_col, panel_info.vl_row);
 825                         lcd_enabled = 0;
 826                         return;
 827                 }
 828         }
 829         if (p->name != NULL)
 830                 debug("Trying compiled-in video modes\n");
 831         while (p->name != NULL) {
 832                 if (strcmp(p->name, vm) == 0) {
 833                         debug("Using video mode: '%s'\n", p->name);
 834                         vm += strlen(vm);
 835                         break;
 836                 }
 837                 p++;
 838         }
 839         if (*vm != '\0')
 840                 debug("Trying to decode video_mode: '%s'\n", vm);
 841         while (*vm != '\0') {
 842                 if (*vm >= '0' && *vm <= '9') {
 843                         char *end;
 844
 845                         val = simple_strtoul(vm, &end, 0);
 846                         if (end > vm) {
 847                                 if (!xres_set) {
 848                                         if (val > panel_info.vl_col)
 849                                                 val = panel_info.vl_col;
 850                                         p->xres = val;
 851                                         panel_info.vl_col = val;
 852                                         xres_set = 1;
 853                                 } else if (!yres_set) {
 854                                         if (val > panel_info.vl_row)
 855                                                 val = panel_info.vl_row;
 856                                         p->yres = val;
 857                                         panel_info.vl_row = val;
 858                                         yres_set = 1;
 859                                 } else if (!bpp_set) {
 860                                         switch (val) {
 861                                         case 8:
 862                                         case 16:
 863                                         case 24:
 864                                         case 32:
 865                                                 color_depth = val;
 866                                                 break;
 867
 868                                         default:
 869                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 870                                                         end - vm, vm, color_depth);
 871                                         }
 872                                         bpp_set = 1;
 873                                 } else if (!refresh_set) {
 874                                         refresh = val;
 875                                         refresh_set = 1;
 876                                 }
 877                         }
 878                         vm = end;
 879                 }
 880                 switch (*vm) {
 881                 case '@':
 882                         bpp_set = 1;
 883                         /* fallthru */
 884                 case '-':
 885                         yres_set = 1;
 886                         /* fallthru */
 887                 case 'x':
 888                         xres_set = 1;
 889                         /* fallthru */
 890                 case 'M':
 891                 case 'R':
 892                         vm++;
 893                         break;
 894
 895                 default:
 896                         if (*vm != '\0')
 897                                 vm++;
 898                 }
 899         }
 900         if (p->xres == 0 || p->yres == 0) {
 901                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 902                 lcd_enabled = 0;
 903                 printf("Supported video modes are:");
 904                 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
 905                         printf(" %s", p->name);
 906                 }
 907                 printf("\n");
 908                 return;
 909         }
 910         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 911                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 912                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 913                 lcd_enabled = 0;
 914                 return;
 915         }
 916         panel_info.vl_col = p->xres;
 917         panel_info.vl_row = p->yres;
 918
 919         switch (color_depth) {
 920         case 8:
 921                 panel_info.vl_bpix = LCD_COLOR8;
 922                 break;
 923         case 16:
 924                 panel_info.vl_bpix = LCD_COLOR16;
 925                 break;
 926         default:
 927                 panel_info.vl_bpix = LCD_COLOR24;
 928         }
 929
 930         p->pixclock = KHZ2PICOS(refresh *
 931                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 932                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 933                                 1000);
 934         debug("Pixel clock set to %lu.%03lu MHz\n",
 935                 PICOS2KHZ(p->pixclock) / 1000,
 936                 PICOS2KHZ(p->pixclock) % 1000);
 937
 938         if (p != &fb_mode) {
 939                 int ret;
 940
 941                 debug("Creating new display-timing node from '%s'\n",
 942                         video_mode);
 943                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
 944                 if (ret)
 945                         printf("Failed to create new display-timing node from '%s': %d\n",
 946                                 video_mode, ret);
 947         }
 948
 949         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 950         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 951                                         ARRAY_SIZE(stk5_lcd_pads));
 952
 953         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
 954         switch (lcd_bus_width) {
 955         case 24:
 956                 pix_fmt = IPU_PIX_FMT_RGB24;
 957                 break;
 958
 959         case 18:
 960                 pix_fmt = IPU_PIX_FMT_RGB666;
 961                 break;
 962
 963         case 16:
 964                 pix_fmt = IPU_PIX_FMT_RGB565;
 965                 break;
 966
 967         default:
 968                 lcd_enabled = 0;
 969                 printf("Invalid LCD bus width: %d\n", lcd_bus_width);
 970                 return;
 971         }
 972         if (karo_load_splashimage(0) == 0) {
 973                 int ret;
 974                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 975                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
 976
 977                 /* MIPI HSC clock is required for initialization */
 978                 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
 979
 980                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3DEX;
 981
 982                 debug("Initializing LCD controller\n");
 983                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 984                 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
 985                 if (ret) {
 986                         printf("Failed to initialize FB driver: %d\n", ret);
 987                         lcd_enabled = 0;
 988                 }
 989         } else {
 990                 debug("Skipping initialization of LCD controller\n");
 991         }
 992 }
 993 #else
 994 #define lcd_enabled 0
 995 #endif /* CONFIG_LCD */
 996
 997 static void stk5_board_init(void)
 998 {
 999         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1000         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1001 }
1002
1003 static void stk5v3_board_init(void)
1004 {
1005         stk5_board_init();
1006 }
1007
1008 static void tx51_set_cpu_clock(void)
1009 {
1010         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1011
1012         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1013                 return;
1014
1015         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1016                 return;
1017
1018         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1019                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1020                 printf("CPU clock set to %lu.%03lu MHz\n",
1021                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1022         } else {
1023                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1024         }
1025 }
1026
1027 static void tx51_init_mac(void)
1028 {
1029         u8 mac[ETH_ALEN];
1030
1031         imx_get_mac_from_fuse(0, mac);
1032         if (!is_valid_ether_addr(mac)) {
1033                 printf("No valid MAC address programmed\n");
1034                 return;
1035         }
1036
1037         printf("MAC addr from fuse: %pM\n", mac);
1038         eth_setenv_enetaddr("ethaddr", mac);
1039 }
1040
1041 int board_late_init(void)
1042 {
1043         int ret = 0;
1044         const char *baseboard;
1045
1046         env_cleanup();
1047
1048         tx51_set_cpu_clock();
1049         karo_fdt_move_fdt();
1050
1051         baseboard = getenv("baseboard");
1052         if (!baseboard)
1053                 goto exit;
1054
1055         printf("Baseboard: %s\n", baseboard);
1056
1057         if (strncmp(baseboard, "stk5", 4) == 0) {
1058                 if ((strlen(baseboard) == 4) ||
1059                         strcmp(baseboard, "stk5-v3") == 0) {
1060                         stk5v3_board_init();
1061                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1062                         printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
1063                                 baseboard);
1064                         stk5v3_board_init();
1065                 } else {
1066                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1067                                 baseboard + 4);
1068                 }
1069         } else {
1070                 printf("WARNING: Unsupported baseboard: '%s'\n",
1071                         baseboard);
1072                 ret = -EINVAL;
1073         }
1074
1075 exit:
1076         tx51_init_mac();
1077
1078         gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1079         clear_ctrlc();
1080         return ret;
1081 }
1082
1083 int checkboard(void)
1084 {
1085         tx51_print_cpuinfo();
1086 #if CONFIG_NR_DRAM_BANKS > 1
1087         printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
1088 #else
1089         printf("Board: Ka-Ro TX51-8xx0\n");
1090 #endif
1091         return 0;
1092 }
1093
1094 #if defined(CONFIG_OF_BOARD_SETUP)
1095 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1096 #include <jffs2/jffs2.h>
1097 #include <mtd_node.h>
1098 static struct node_info nodes[] = {
1099         { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1100 };
1101 #else
1102 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1103 #endif
1104
1105 static const char *tx51_touchpanels[] = {
1106         "ti,tsc2007",
1107         "edt,edt-ft5x06",
1108 };
1109
1110 void ft_board_setup(void *blob, bd_t *bd)
1111 {
1112         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1113         int ret;
1114
1115         ret = fdt_increase_size(blob, 4096);
1116         if (ret)
1117                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1118
1119         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1120         fdt_fixup_ethernet(blob);
1121
1122         karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
1123                                 ARRAY_SIZE(tx51_touchpanels));
1124         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1125         karo_fdt_update_fb_mode(blob, video_mode);
1126 }
1127 #endif /* CONFIG_OF_BOARD_SETUP */